JPH0682791B2 - Complementary semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a complementary semiconductor integrated circuit device, and more particularly to connection between an output transistor and a power supply wiring.

[Conventional technology]

Conventionally, for example, as a layout pattern of an output circuit part of a multi-bit complementary MOS memory circuit device and its equivalent circuit, as shown in FIGS. 3 and 4, as shown in FIGS. The aluminum wiring 33 for the _CC power source, the source region 35 of the N-channel output transistor 34, and the aluminum wiring 36 for the GND power source are ohmic-connected. On the other hand, the output terminal bonding pad 37 is directly ohmic-connected to the drain region 38 of the P-channel output transistor 31 by aluminum wiring.
The drain region 39 of the channel output transistor 34 is N ⁺
It was ohmic-connected with aluminum wiring via the diffusion resistance 40.

[Problems to be solved by the invention]

In the conventional output circuit pattern layout method described above, V _CC
Since the aluminum wiring for power supply passes over the drain region of the N-channel output transistor, it is necessary to extend the N ⁺ diffusion layer in the drain region to form a tunnel wiring. Normally, the layer resistance of the N ⁺ diffusion layer is about 50 Ω / □, and in the above-mentioned tunnel wiring pattern layout, a tunnel resistance of several tens of ohms is formed, which causes circuit characteristics such as output current, output voltage, and operating speed. It has the drawback of having an adverse effect.

In particular, in a multi-bit complementary MOS memory circuit device having a plurality of output circuits, the GND and V _CC both power supply aluminum wiring widths become thick and the tunnel resistance value becomes large. As a method of reducing the tunnel resistance value described above, there is a method of widening the width of the N ⁺ diffusion layer and reducing the length / width ratio, but this is not a real problem due to an increase in terminal capacitance and a limitation on the pattern layout area. Become.

[Means for solving problems]

The present invention uses polycide tunnel wiring for the connection between the source region of the output transistor of the output circuit and the power supply.

A complementary semiconductor integrated circuit device according to the present invention is characterized in that, in a complementary semiconductor integrated circuit device having a plurality of output circuits, a source region of an output transistor forming an output circuit and a power supply wiring are connected by a polycide wiring. And

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is an output circuit layout pattern of a complementary MOS memory circuit, and FIG. 2 is an equivalent circuit including the tunnel resistance of FIG. The source region 12 of the N-channel output transistor 11 is directly ohmic-connected to the aluminum wiring 13 for GND power supply. On the other hand, the source region 15 of the P-channel output transistor 14 is ohmic-connected to the V _CC power supply aluminum wiring 17 through the tunnel wiring of the polycide wiring 16 of tungsten polycide. From the bonding pad 18 for the output terminal, the drain regions 19, 2 of the N-channel output transistor 11 and the P-channel output transistor 14 are connected.
Ohmic connection to 0 is made by aluminum wiring 21 and 22, respectively.

〔The invention's effect〕

As described above, the present invention uses the polycide wiring for connecting the source region of the output transistor and the power supply line, and thus has a resistance value of one digit compared with the case of using the conventional N ⁺ diffusion layer wiring. Therefore, the layout pattern area is not required to be increased, and there is an effect that it contributes to improvement of circuit characteristics such as output current, output voltage, and operation speed.

In the present embodiment, the polycide wiring is used to connect the source region of the P-channel output transistor and the aluminum wiring for the V _CC power supply. Conversely, the polycide wiring is connected to the source region of the N-channel output transistor and the aluminum wiring for the GND power supply. You may use it. In addition to tungsten, polycide made of molybdenum or titanium may be used for the polycide wiring.

[Brief description of drawings]

FIG. 1 is a layout pattern diagram of an output circuit of an embodiment of the present invention, FIG. 2 is an equivalent circuit of FIG. 1, FIG. 3 is a layout pattern diagram of a conventional output circuit, and FIG. 4 is a diagram of FIG. It is an equivalent circuit diagram. 11,34 …… N-channel output transistor, 14,31 …… P-channel output transistor, 12,35 …… N-channel output transistor source area, 15,32 …… P-channel output transistor source area, 13,36… … Ground power aluminum wiring, 17,33 …… V _CC power aluminum wiring, 18,37 …… Output terminal bonding pad, 16 …… Polycide wiring, 40 …… N ⁺ diffusion layer wiring.

Claims (1)

[Claims] 1. A complementary semiconductor integrated circuit device including a MOS transistor of one conductivity type and a MOS transistor of the opposite conductivity type which constitute an output circuit, wherein a formation region of the MOS transistor of the one conductivity type and the MOS transistor of the opposite conductivity type. An output wiring made of an aluminum wiring connected to the output end on one side perpendicular to the extending direction of each gate electrode in the transistor formation region, a formation region of the one conductivity type MOS transistor, and the opposite conductivity type It has a first power supply wiring and a second power supply wiring made of aluminum wiring provided on the other side of the formation region of the MOS transistor, and the drain region of the MOS transistor of one conductivity type and the MOS of the opposite conductivity type. A drain region of the transistor is connected to the output wiring by an aluminum wiring, and a source region of the one conductivity type MOS transistor is connected to the first power wiring. Complementary semiconductor integrated circuit device, characterized in that connected in Risaido wiring.