JPH0682945B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0682945B2 JPH0682945B2 JP4342787A JP4342787A JPH0682945B2 JP H0682945 B2 JPH0682945 B2 JP H0682945B2 JP 4342787 A JP4342787 A JP 4342787A JP 4342787 A JP4342787 A JP 4342787A JP H0682945 B2 JPH0682945 B2 JP H0682945B2
- Authority
- JP
- Japan
- Prior art keywords
- power element
- circuit pattern
- semiconductor device
- main circuit
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/10—Integrated devices
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)
- Power Conversion In General (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、外来ノイズが印加されたときの誤動作耐量を
改善した半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device with improved malfunction tolerance when external noise is applied.
ホトカプラとパワーデバイス（例えばトライアック，サ
イリスタ，トランジスタ等）とを接続し、ホトカプラの
LEDに電流を流してそれに応答してパワーデバイスをオ
ン・オフする制御方式は一般によく使用されている。ソ
リッドステートリレーという呼び名の製品はこの方式を
用いたものである。この方式による製品或いは回路で
は、入力回路とパワーデバイスが接続されている出力回
路とはホトカプラによって絶縁されている。カプラ内部
の光結合によって信号は伝達されるが、耐圧的には絶縁
されている。ところで、このカプラとパワーデバイスを
結合した半導体装置では、その構造上外来ノイズに弱く
なることがある。Connect the photocoupler and power device (eg, triac, thyristor, transistor, etc.) to
A control method in which a current is passed through the LED and the power device is turned on / off in response to the current is commonly used. The product called solid state relay uses this method. In the product or circuit according to this method, the input circuit and the output circuit to which the power device is connected are insulated by a photocoupler. Signals are transmitted by optical coupling inside the coupler, but they are insulated in terms of pressure resistance. By the way, the semiconductor device in which the coupler and the power device are coupled may be vulnerable to external noise due to its structure.
このような従来の半導体装置について、以下、ソリッド
ステートリレーを例にあげて説明していく。Such a conventional semiconductor device will be described below by taking a solid state relay as an example.
第６図は従来のソリッドステートリレーの断面構造図で
あり、第７図はその回路図である。第７図に示す回路に
おいて、1,2は出力端子、3,4は入力端子、５は制御用素
子でここではトライアックカプラ、6,9,10は抵抗器、７
はトライアック、８はコンデンサである。このような回
路構成を第６図に示す構造の装置に納めてある。この第
６図中、端子1,2,3,4、トライアックカプラ５、トライ
アック７以外の回路部品は示されていない。11は絶縁基
板、12は金属板、13はケース、14は注型樹脂である。FIG. 6 is a sectional structural view of a conventional solid state relay, and FIG. 7 is a circuit diagram thereof. In the circuit shown in FIG. 7, 1 and 2 are output terminals, 3 and 4 are input terminals, 5 is a control element, here a triac coupler, 6, 9 and 10 are resistors, and 7
Is a triac and 8 is a capacitor. Such a circuit configuration is housed in a device having the structure shown in FIG. In FIG. 6, circuit components other than the terminals 1, 2, 3, 4 and the triac coupler 5 and the triac 7 are not shown. 11 is an insulating substrate, 12 is a metal plate, 13 is a case, and 14 is a casting resin.
パワー素子７は電流が流れると大きな電力損失が発生す
るので、絶縁基板11を通して金属板12へ放熱される。更
に、この金属板12は放熱器に取り付けされて放熱を良く
する。絶縁基板11には、一般にセラミック或いはプリン
ト基板が使われる。また、金属板と絶縁基板が一体とな
ったいわゆる金属基板が使われることもある。いずれに
しても、絶縁体11を通してパワー素子７に発生する電力
損失が放熱される。このため、良好な放熱を得ようとす
れば、この絶縁体11の厚みはできる限り薄くする方が良
い。あまり薄くすると金属板12と絶縁基板11上の回路間
の絶縁耐力がもたなくなるが、その絶縁耐力に耐える限
界まで薄くすることが放熱上望ましい。しかし、この絶
縁基板11を薄く（例えば100μｍ〜500μｍ程度）する
と、金属板12と絶縁基板11上の回路間が容量で結合され
た状態となり、回路と金属板12間に外来ノイズ電圧が印
加されるとこの容量を通して電流が流れ、パワー素子７
が誤動作することになる。従って、外来ノイズに弱い半
導体装置となる。Since a large power loss occurs in the power element 7 when a current flows, it is radiated to the metal plate 12 through the insulating substrate 11. Further, the metal plate 12 is attached to a radiator to improve heat dissipation. As the insulating substrate 11, a ceramic or a printed circuit board is generally used. Also, a so-called metal substrate in which a metal plate and an insulating substrate are integrated may be used. In any case, the power loss generated in the power element 7 is radiated through the insulator 11. Therefore, in order to obtain good heat dissipation, it is better to make the thickness of the insulator 11 as thin as possible. If the thickness is too thin, the dielectric strength between the metal plate 12 and the circuit on the insulating substrate 11 will be low, but it is desirable for heat dissipation to make it as thin as possible to withstand the dielectric strength. However, when the insulating substrate 11 is made thin (for example, about 100 μm to 500 μm), the metal plate 12 and the circuit on the insulating substrate 11 are capacitively coupled, and an external noise voltage is applied between the circuit and the metal plate 12. Then, current flows through this capacitance, and power element 7
Will malfunction. Therefore, the semiconductor device is weak against external noise.
第８図は上記の装置に外来ノイズが印加された時の回路
図を示している。第７図の回路に負荷15と交流電源16が
追加して示されており、また、17は外来ノイズであり、
アースと交流電源16の１端子間に加えられたと仮定した
ものである。Cgは、トライアック７のゲート端子とアー
ス間、即ち絶縁基板11に存在する容量を示している。絶
縁基板11が薄い程この容量が大きくなる。この第８図に
おいて、外来ノイズ17、例えば立上り数ns〜１μｓの巾
のノイズ電圧が印加されると、Cgに充電電流が流れ、そ
れがトライアック７のゲート，T1端子間に接続された抵
抗10にも流れ、そこに電圧が現われる。この充電電流は
トライアック７のゲートからT1へも流れて、トリガ信号
として働く。この電流でトライアック７は誤動作してし
まうことがある。Cgが小さければこの充電電流は小さ
く、外来ノイズ耐量を上げることができる。しかし、Cg
を小さくするために絶縁基板11の厚みを厚くするので
は、トライアック７に発生する電力損失を放熱できなく
なってしまう。FIG. 8 shows a circuit diagram when external noise is applied to the above device. A load 15 and an AC power supply 16 are additionally shown in the circuit of FIG. 7, and 17 is external noise,
It is assumed that it is applied between the ground and one terminal of the AC power supply 16. Cg represents the capacitance existing between the gate terminal of the triac 7 and the ground, that is, the insulating substrate 11. This capacitance increases as the insulating substrate 11 becomes thinner. In FIG. 8, when an external noise 17, for example, a noise voltage having a rising width of ns to 1 μs is applied, a charging current flows in Cg, which is a resistor connected between the gate of the triac 7 and the T 1 terminal. It also flows to 10, and the voltage appears there. This charging current also flows from the gate of the triac 7 to T 1 and acts as a trigger signal. This current may cause the triac 7 to malfunction. If Cg is small, this charging current is small, and the external noise immunity can be increased. But Cg
If the thickness of the insulating substrate 11 is increased in order to reduce the power consumption, the power loss generated in the triac 7 cannot be radiated.
従来の半導体装置は以上のように構成されているので、
良好な放熱を得ようとすると、外来ノイズに弱くなって
しまうという問題点があった。Since the conventional semiconductor device is configured as described above,
There is a problem in that when trying to obtain good heat dissipation, it becomes vulnerable to external noise.
本発明は上記のような問題点を解消するためになされた
もので、放熱が良好であるとともに、外来ノイズ耐量の
高い半導体装置を得ることを目的とする。The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor device which has good heat dissipation and high external noise immunity.
この発明に係る半導体装置は、パワー素子とこのパワー
素子を制御する制御用素子とを結合してなる半導体装置
において、放熱のための金属板と上記制御用素子が接続
された制御回路パターンとの間に、上記金属板，制御回
路パターンそれぞれと絶縁層を介して配設されたシール
ド用金属層を有してなるとともに上記制御回路パターン
に隣接し上記パワー素子の主回路パターンが配設された
絶縁基板を備え、上記シールド用金属層と上記主回路パ
ターンとを導電体で接続することによりノイズによる電
流を上記シールド用金属層で捕捉し、該電流を上記パワ
ー素子の主回路の一部へ流すようにしたものである。A semiconductor device according to the present invention is a semiconductor device in which a power element and a control element for controlling the power element are combined, and a metal plate for heat dissipation and a control circuit pattern to which the control element is connected are provided. A shield metal layer is provided between the metal plate and the control circuit pattern via an insulating layer, and a main circuit pattern of the power element is disposed adjacent to the control circuit pattern. An insulating substrate is provided, and a current due to noise is captured by the shield metal layer by connecting the shield metal layer and the main circuit pattern with a conductor, and the current is supplied to a part of the main circuit of the power element. It was made to flow.
更に、この発明にかかる半導体装置は、パワー素子とこ
のパワー素子を制御する制御用素子とを結合してなる半
導体装置において、放熱のための金属板表面上に配設さ
れ、表面に第１の絶縁層を備えた絶縁基板と、上記第１
の絶縁層の表面上に配設されるとともに上記パワー素子
が接続された主回路パターンと、この主回路パターンの
表面上の一部に配設された第２の絶縁層と、この第２の
絶縁層の表面上に形成された上記制御用素子の制御回路
パターンとを備え、ノイズによる電流を上記主回路パタ
ーンで捕捉し、該電流を上記パワー素子の主回路の一部
に流すようにしたものである。Further, the semiconductor device according to the present invention is a semiconductor device in which a power element and a control element for controlling the power element are coupled to each other. An insulating substrate having an insulating layer, and the first
A main circuit pattern provided on the surface of the insulating layer and connected to the power element, a second insulating layer provided on a part of the surface of the main circuit pattern, and a second insulating layer A control circuit pattern of the control element formed on the surface of an insulating layer is provided, and a current due to noise is captured by the main circuit pattern, and the current is caused to flow in a part of the main circuit of the power element. It is a thing.
この発明においては、上記のように構成して、ノイズ電
流を上記シールド用金属層で捕捉し、該電流を上記パワ
ー素子の主回路の一部へ流すようにしたので、上記パワ
ー素子の放熱が良好となるように上記絶縁基板を薄くし
ても、上記ノイズ電流がパワー素子の誤動作電流となる
ことを防止することができる。In the present invention, since the noise current is captured by the shielding metal layer and the current is caused to flow to a part of the main circuit of the power element, the heat radiation of the power element is prevented. Even if the insulating substrate is thin so as to be favorable, it is possible to prevent the noise current from becoming a malfunction current of the power element.
第１図は、本発明の一実施例による絶縁基板を示す図で
あり、（ａ）は上面図，（ｂ）は側面図である。図にお
いて、18は３層のメタライズ層を有する構造のセラミッ
ク基板である。セラミック112の下面全面に、メタライ
ズ層111がメタライズされ更にNiメッキがほどこされて
いる。113は中間のメタライズ層である。セラミック114
の上面には、従来図（第６図，第７図）において説明し
たトライアック7,トライアックカプラ５等の半導体チッ
プ及び入力端子1,2をはじめとする上記半導体チップ以
外の他の回路部品が載置されるパターン115がメタライ
ズとメッキによって描かれている。FIG. 1 is a view showing an insulating substrate according to an embodiment of the present invention, (a) is a top view and (b) is a side view. In the figure, 18 is a ceramic substrate having a structure having three metallized layers. A metallized layer 111 is metallized on the entire lower surface of the ceramic 112 and further plated with Ni. 113 is an intermediate metallization layer. Ceramic 114
On the upper surface of the semiconductor chip, the semiconductor chips such as the triac 7, the triac coupler 5 and the input terminals 1 and 2 described in the conventional drawings (FIGS. 6 and 7) and other circuit components other than the above semiconductor chip are mounted. The pattern 115 to be placed is drawn by metallization and plating.
このセラミック基板18がソリッドステートリレーに使わ
れる場合、放熱のための金属板とメタライズ層111との
間が半田を介して半田付けされ、メタライズ層115の上
面に部品を半田付けして回路接続される。なお、第２図
はこのような装置を示す斜視図であり、図中のセラミッ
ク114の上面に厚みを有することなく描かれているパタ
ーンが上記メタライズ層115に対応している。ここで、
このセラミック基板18の中間メタライズ層113が本実施
例の骨子となる点である。メタライズ層111はこのセラ
ミック基板18の裏面全面となっており、中間メタライズ
層113もセラミック基板18の端面より内部へ僅か距離を
とってほぼ全面に形成されている。そして、メタライズ
層115aにトライアックチップが半田付けされるが、この
メタライズ層115aがトライアックのT2電極となる。そし
て、この電極115aとメタライズ層113はスルーホール116
を介して半田によって電気的に接続される。When this ceramic substrate 18 is used in a solid-state relay, the metal plate for heat dissipation and the metallization layer 111 are soldered via solder, and the components are soldered to the upper surface of the metallization layer 115 for circuit connection. It Note that FIG. 2 is a perspective view showing such a device, and a pattern drawn on the upper surface of the ceramic 114 in the drawing without having a thickness corresponds to the metallized layer 115. here,
The intermediate metallization layer 113 of the ceramic substrate 18 is the main feature of this embodiment. The metallized layer 111 is on the entire back surface of the ceramic substrate 18, and the intermediate metallized layer 113 is also formed on almost the entire surface with a slight distance from the end surface of the ceramic substrate 18 to the inside. Then, the triac chip is soldered to the metallized layer 115a, and this metallized layer 115a becomes the T 2 electrode of the triac. Then, the electrode 115a and the metallized layer 113 are connected to the through hole 116.
It is electrically connected by soldering through.
このような装置の回路図を第３図に示す。この図におい
て、Csはメタライズ層111とメタライズ層113間の容量で
あり、その上にメタライズ層113とトライアック７のゲ
ート極間の容量Cgが存在する。CgとCs間はスルーホール
116によってトライアック７のT2電極に接続されてい
る。この回路で外来ノイズ17が加えられると、Csを通る
充電電流はすべてトライアック７のT2電極へ流れ、負荷
15,電源16を通って外来ノイズ17の他端子の閉回路を貫
流するため、トライアック７のゲート極へは流れず、誤
動作の対象とはならない。従って、このセラミック基板
18の絶縁層であるセラミック112,114の厚みを薄くして
も、中間メタライズ層113により外来ノイズ17による誤
動作を防止でき、放熱性も良くすることができる。A circuit diagram of such a device is shown in FIG. In this figure, Cs is the capacitance between the metallization layer 111 and the metallization layer 113, and the capacitance Cg between the metallization layer 113 and the gate electrode of the triac 7 exists on it. Through hole between Cg and Cs
It is connected to the T 2 electrode of the triac 7 by 116. When extraneous noise 17 is added in this circuit, all the charging current passing through Cs flows to the T 2 electrode of TRIAC 7 and the load
Since the external noise 17 flows through the closed circuit of the other terminal through the power supply 15, it does not flow to the gate pole of the triac 7 and is not the target of malfunction. Therefore, this ceramic substrate
Even if the thickness of the ceramics 112, 114, which are 18 insulating layers, is reduced, the intermediate metallization layer 113 can prevent malfunction due to the external noise 17 and improve heat dissipation.
第４図は本発明の他の実施例による絶縁基板を示す図で
ある。この図において、20はセラミック基板、201は裏
面のメタライズ層、202は回路部品，半導体チップが載
るメタライズ層であり、特にトライアックが半田付けさ
れるメタライズ層202aのパターン面積は第１図に示した
ものに比べ大きくなっている。203はフィルム基板であ
り、メタライズ層202上に接着され、そのフィルム厚は
数十μｍと薄い。フィルム基板203の上にもパターン205
が描かれている。なお、第５図は本実施例によるセラミ
ック基板20を用いたソリッドステートリレーを示す断面
構造図である。FIG. 4 is a view showing an insulating substrate according to another embodiment of the present invention. In this figure, 20 is a ceramic substrate, 201 is a back side metallization layer, 202 is a metallization layer on which circuit components and semiconductor chips are mounted, and the pattern area of the metallization layer 202a to which the triac is soldered is shown in FIG. It is bigger than the ones. Reference numeral 203 denotes a film substrate, which is adhered onto the metallized layer 202 and has a thin film thickness of several tens of μm. Pattern 205 on the film substrate 203
Is drawn. FIG. 5 is a sectional structural view showing a solid state relay using the ceramic substrate 20 according to this embodiment.
このような構造の基板は、第１図に示した基板と同じ機
能となっている。即ち、メタライズ層202が中間メタラ
イズ層113と同じ働きをするパターンとなっている。ト
ライアック７のゲート極が位置する所の下がトライアッ
ク７のT2電極でシールドされておれば、第１図の場合と
同じ原理によるシールド効果を示す。トライアック７の
ゲート極とゲート抵抗10が搭載されるパターン205はフ
ィルム基板203上にあって、トライアック７のT2電極と
なるパターン202aでシールドされている。なお、第１図
の３層のメタライズ層を有するセラミック基板18は構造
上高価とならざるを得ないが、本実施例によるセラミッ
ク基板20は通常の両面セラミック204とフィルム基板203
で構成されているので、外来ノイズ耐量は同じで、さら
に安価にできる特長をもっている。The substrate having such a structure has the same function as the substrate shown in FIG. That is, the metallized layer 202 has a pattern having the same function as the intermediate metallized layer 113. If the T 2 electrode of the triac 7 is shielded below the position where the gate pole of the triac 7 is located, the shielding effect based on the same principle as in the case of FIG. 1 is exhibited. The pattern 205 on which the gate pole of the triac 7 and the gate resistor 10 are mounted is on the film substrate 203, and is shielded by the pattern 202a serving as the T 2 electrode of the triac 7. Although the ceramic substrate 18 having the three metallized layers in FIG. 1 is inevitably expensive in structure, the ceramic substrate 20 according to this embodiment is a normal double-sided ceramic 204 and a film substrate 203.
Since it is composed of, it has the same external noise immunity, and has the feature that it can be made even cheaper.
以上のように、この発明に係る半導体装置によれば、パ
ワー素子とこのパワー素子を制御する制御用素子とを結
合してなる半導体装置において、放熱のための金属板と
上記制御用素子が接続された制御回路パターンとの間
に、上記金属板，制御回路パターンそれぞれと絶縁層を
介して配設されたシールド用金属層を有してなるととも
に上記制御回路パターンに隣接し上記パワー素子の主回
路パターンが配設された絶縁基板を備え、上記シールド
用金属層と上記主回路パターンとを導電体で接続するこ
とによりノイズによる電流を上記シールド用金属層で捕
捉し、該電流を上記パワー素子の主回路の一部へ流すよ
うにしたので、上記パワー素子の放熱が良好となるよう
に上記絶縁基板を薄くしても、上記ノイズ電流がパワー
素子の誤動作電流となることを防止することができ、放
熱性が良好な外来ノイズに強いものを得ることかできる
効果がある。As described above, according to the semiconductor device of the present invention, in the semiconductor device including the power element and the control element for controlling the power element, the metal plate for heat dissipation is connected to the control element. And a metal layer for shielding disposed between the metal plate and the control circuit pattern with an insulating layer interposed between the metal plate and the control circuit pattern, and adjacent to the control circuit pattern. An insulating substrate provided with a circuit pattern is provided, and a current due to noise is captured by the shield metal layer by connecting the shield metal layer and the main circuit pattern with a conductor, and the current is supplied to the power element. Since it is made to flow to a part of the main circuit of the power element, even if the insulating substrate is made thin so that the heat dissipation of the power element is good, the noise current is a malfunction current of the power element. Rukoto can be prevented, there is an effect that can either be obtained stronger the better external noise heat dissipation.
更に、この発明にかかる半導体装置によれば、パワー素
子とこのパワー素子を制御する制御用素子とを結合して
なる半導体装置において、放熱のための金属板表面上に
配設され、表面に第１の絶縁層を備えた絶縁基板と、上
記第１の絶縁層の表面上に配設されるとともに上記パワ
ー素子が接続された主回路パターンと、この主回路パタ
ーンの表面上の一部に配設された第２の絶縁層と、この
第２の絶縁層の表面上に形成された上記制御用素子の制
御回路パターンとを備え、ノイズによる電流を上記主回
路パターンで捕捉し、該電流を上記パワー素子の主回路
の一部に流すようにしたので、上記パワー素子の放熱が
良好となるように上記絶縁基板を薄くしても、上記ノイ
ズ電流がパワー素子の誤動作電流となることを防止する
ことができ、放熱性が良好な外来ノイズに強いものを得
ることができる効果がある。Further, according to the semiconductor device of the present invention, in a semiconductor device in which a power element and a control element for controlling the power element are combined, the power element is disposed on the surface of a metal plate for heat dissipation, An insulating substrate having a first insulating layer, a main circuit pattern disposed on the surface of the first insulating layer and connected to the power element, and a main circuit pattern disposed on a part of the surface of the main circuit pattern. A second insulating layer provided and a control circuit pattern of the control element formed on the surface of the second insulating layer are provided, a current due to noise is captured by the main circuit pattern, and the current is Since it is made to flow in a part of the main circuit of the power element, the noise current is prevented from becoming a malfunction current of the power element even if the insulating substrate is made thin so that the heat dissipation of the power element is good. Can heat dissipation There is an effect that it is possible to obtain a stronger good external noise.
第１図はこの発明の一実施例による半導体装置の絶縁基
板を示す図、第２図はこの発明の一実施例による半導体
装置を示す斜視図、第３図はこの発明の一実施例による
半導体装置の回路図、第４図はこの発明の他の実施例に
よる半導体装置の絶縁基板を示す図、第５図はそれを用
いた半導体装置の断面構造図、第６図は従来の半導体装
置を示す断面構造図、第７図はその回路図、第８図は第
７図の回路に外来ノイズが印加された場合の回路図であ
る。 ５はトライアックカプラ、７はトライアック、12は金属
板、17は外来ノイズ、18,20はセラミック基板、112,11
4,204はセラミック、113,115,202はメタライズ層、203
はフィルム基板、205はパターン。 なお、図中同一符号は、同一又は相当部分を示す。1 is a view showing an insulating substrate of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a perspective view showing a semiconductor device according to an embodiment of the present invention, and FIG. 3 is a semiconductor according to an embodiment of the present invention. FIG. 4 is a circuit diagram of the device, FIG. 4 is a view showing an insulating substrate of a semiconductor device according to another embodiment of the present invention, FIG. 5 is a sectional structural view of a semiconductor device using the same, and FIG. 6 is a conventional semiconductor device. FIG. 7 is a sectional view showing the circuit diagram, and FIG. 8 is a circuit diagram when an external noise is applied to the circuit of FIG. 5 is a triac coupler, 7 is a triac, 12 is a metal plate, 17 is external noise, 18 and 20 are ceramic substrates, 112 and 11
4,204 is ceramic, 113,115,202 is metallized layer, 203
Is a film substrate and 205 is a pattern. The same reference numerals in the drawings indicate the same or corresponding parts.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０５Ｋ 7/20 Ｄ 8727−4Ｅ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H05K 7/20 D 8727-4E
Claims (3)
御用素子とを結合してなる半導体装置において、 放熱のための金属板と上記制御用素子が接続された制御
回路パターンとの間に、上記金属板，制御回路パターン
それぞれと絶縁層を介して配設されたシールド用金属層
を有してなるとともに上記制御回路パターンに隣接し上
記パワー素子の主回路パターンが配設された絶縁基板を
備え、 上記シールド用金属層と上記主回路パターンとを導電体
で接続することによりノイズによる電流を上記シールド
用金属層で捕捉し、該電流を上記パワー素子の主回路の
一部へ流すようにしたことを特徴とする半導体装置。1. A semiconductor device comprising a power element and a control element for controlling the power element, which are coupled to each other, between a metal plate for heat dissipation and a control circuit pattern to which the control element is connected. An insulating substrate having a shielding metal layer disposed via an insulating layer with each of the metal plate and the control circuit pattern and having a main circuit pattern of the power element adjacent to the control circuit pattern. Comprising, by connecting the metal layer for shielding and the main circuit pattern with a conductor, a current due to noise is captured by the metal layer for shielding, and the current is passed to a part of the main circuit of the power element. A semiconductor device characterized by the above.
御用素子とを結合してなる半導体装置において、 放熱のための金属板表面上に配設され、表面に第１の絶
縁層を備えた絶縁基板と、 上記第１の絶縁層の表面上に配設されるとともに上記パ
ワー素子が接続された主回路パターンと、 この主回路パターンの表面上の一部に配設された第２の
絶縁層と、 この第２の絶縁層の表面上に形成された上記制御用素子
の制御回路パターンとを備え、 ノイズによる電流を上記主回路パターンで捕捉し、該電
流を上記パワー素子の主回路の一部に流すようにしてな
ることを特徴とする半導体装置。2. A semiconductor device in which a power element and a control element for controlling the power element are coupled to each other, wherein the semiconductor element is provided on a surface of a metal plate for heat dissipation and has a first insulating layer on the surface. An insulating substrate, a main circuit pattern provided on the surface of the first insulating layer and connected to the power element, and a second insulation provided on a part of the surface of the main circuit pattern. A layer and a control circuit pattern of the control element formed on the surface of the second insulating layer, a current due to noise is captured by the main circuit pattern, and the current is detected by the main circuit of the power element. A semiconductor device characterized by being made to flow to a part.
上記第２の絶縁層はフィルム基板であることを特徴とす
る特許請求の範囲第２項記載の半導体装置。3. The first insulating layer is made of ceramic,
The semiconductor device according to claim 2, wherein the second insulating layer is a film substrate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4342787A JPH0682945B2 (en) | 1987-02-25 | 1987-02-25 | Semiconductor device |
| US07/406,179 US4916502A (en) | 1987-02-25 | 1989-09-13 | Semiconductor device to be coupled with a control circuit by a photocoupler |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4342787A JPH0682945B2 (en) | 1987-02-25 | 1987-02-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63209198A JPS63209198A (en) | 1988-08-30 |
| JPH0682945B2 true JPH0682945B2 (en) | 1994-10-19 |
Family
ID=12663400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4342787A Expired - Lifetime JPH0682945B2 (en) | 1987-02-25 | 1987-02-25 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4916502A (en) |
| JP (1) | JPH0682945B2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2636602B2 (en) * | 1991-11-05 | 1997-07-30 | 三菱電機株式会社 | Semiconductor device |
| JP2956363B2 (en) * | 1992-07-24 | 1999-10-04 | 富士電機株式会社 | Power semiconductor device |
| JP2912526B2 (en) * | 1993-07-05 | 1999-06-28 | 三菱電機株式会社 | Semiconductor power module and composite board |
| DE4329083A1 (en) * | 1993-08-30 | 1995-03-02 | Telefunken Microelectron | Assembly for receiving electronic components |
| JP2973792B2 (en) * | 1993-09-21 | 1999-11-08 | 富士電機株式会社 | Resin-sealed semiconductor device |
| JP3540471B2 (en) * | 1995-11-30 | 2004-07-07 | 三菱電機株式会社 | Semiconductor module |
| US6227723B1 (en) * | 1999-06-30 | 2001-05-08 | Kyocera Corporation | Substrate for mounting an optical component and optical module provided with the same |
| AU2001229547A1 (en) * | 2000-01-18 | 2001-07-31 | Sunrisetek, Llc | Dual-sided, surface mountable integrated circuit package |
| CN112563258A (en) * | 2020-12-11 | 2021-03-26 | 浙江华晶整流器有限公司 | Light-operated module |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS605141U (en) * | 1983-06-22 | 1985-01-14 | 富士通株式会社 | Insulating sheet with shield for transistors |
| JPS604241A (en) * | 1983-06-22 | 1985-01-10 | Nec Corp | Semiconductor device |
| JPS60187038A (en) * | 1984-03-07 | 1985-09-24 | Hitachi Ltd | Multilayer interconnection structure |
| JPS60224244A (en) * | 1984-04-20 | 1985-11-08 | Hitachi Micro Comput Eng Ltd | Semiconductor device |
| JPS61180571A (en) * | 1985-02-06 | 1986-08-13 | Matsushita Electric Ind Co Ltd | semiconductor insulation equipment |
| JPS61239649A (en) * | 1985-04-13 | 1986-10-24 | Fujitsu Ltd | High-speed integrated circuit package |
| JPH06181655A (en) * | 1992-10-30 | 1994-07-05 | Kankyo Riyokuka Shigen Kaihatsu Center:Kk | Method for proliferating himalayan cherry tree |
-
1987
- 1987-02-25 JP JP4342787A patent/JPH0682945B2/en not_active Expired - Lifetime
-
1989
- 1989-09-13 US US07/406,179 patent/US4916502A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US4916502A (en) | 1990-04-10 |
| JPS63209198A (en) | 1988-08-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |