JPH0683072B2 - A / D conversion circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for converting an analog signal into a digital code, and more particularly to a structure suitable for converting a high speed converting means into a monolithic integrated circuit.

(Conventional technology and its problems) Conventionally, high-speed conversion of analog signals into digital codes (A /
D) 2 ^N when the resolution is N bits as the conversion method
-So-called fully parallel type A / D using one voltage comparator
Transducers have been used. However, it is known that if an attempt is made to increase the resolution, the number of required voltage comparators becomes too large, and the offset voltage of the voltage comparators needs to be made small, which makes practical implementation difficult.

Therefore, with a resolution of more than 10 bits at several M samples / sec or more
As an A / D converter, a cascade connection type A / D converter as shown in FIG. 2 is realized and used on a hybrid IC or a printed circuit board. Regarding this method, H. Schmid's "El
ectronic Analog / Digital Converters "(VAN NOSTRAND
The details are omitted because they are explained in detail on page 318 of REINHOLD), but in Figure 2, there are three 3-bit parallel A / D converters AD1, AD2, AD3, and a 3-bit D / A. Converter DA1, DA
Using two of the two, the input signal input from the input terminal is first encoded by the first A / D converter AD1 to obtain the output code of the upper 3 bits from B8, B7, B6 and the output code of the first of
Reproduced by the D / A converter DA1 and subtracted from the input signal, amplified by 2 ³ or 8 times by the amplifier A1 and input to the second A / D converter AD2 to obtain the next 3-bit output code. . This code is further D / A converted, subtracted from the input voltage of AD2, further amplified by 8 times by A2, and applied to the third A / D converter AD3 to obtain a 3-bit code. Got the sign. In this case, the number of comparators required to form the 3-bit A / D converter is 7, so that a total of 21 comparators are required. Since all parallel type requires 511, it can be seen that the cascade type can expect a significant reduction in hardware compared to this.

However, particularly in the cascade type, both the first A / D converter and the D / A converter require an accuracy equal to or higher than the final resolution, in this example, 9-bit accuracy. Otherwise, the second stage
Since the error is amplified by 8 times and applied to the input of the A / D converter, the conversion after the second stage becomes meaningless.
Such a constraint condition can be solved by selecting parts when assembling on a printed circuit board, but when integrating the whole into an integrated circuit, a significant reduction in yield is accompanied, which is not suitable for the integrated circuit. It was a method.

(Object of the Invention) The present invention significantly compromises the requirements for the accuracy of the internal A / D converter that constitutes the serial-parallel A / D converter, and combines a battery array that is relatively easy to realize with an MIS type integrated circuit. This provides a means for realizing a serial / parallel A / D converter on a monolithic IC.

(Structure of the Invention) The present invention relates to a parallel A / D converter and a voltage corresponding to a code which is smaller than the output code of the A / D converter by the minimum resolution voltage. A circuit consisting of means for subtracting from the input voltage of the D converter and means for amplifying the subtracted voltage by 2 ^N-1 times when the resolution of the A / D converter is N bits is connected in cascade. Then, the A / D conversion circuit is characterized in that it has means for adding the output codes of the respective parallel A / D converters in accordance with the weights of the respective A / D converters.

(Embodiment) Next, an embodiment of the present invention will be described with reference to FIG.

In this embodiment, the voltage comparators CP0 to CP7 and the resistor R0
A 3-bit parallel A / D converter composed of R8 and decoder 1 and the output of each voltage comparator of this parallel A / D converter are controlled by the signal input terminal and the ground potential or negative reference potential. -V _R , 8 switches, one electrode is connected to each of the switches and the other is commonly connected, and a capacitor having the same capacitance value and a negative input are connected to the commonly connected node of the capacitor. A first A / D composed of an operational amplifier connected and whose positive input is grounded, a switch SF connected in parallel between the output of the operational amplifier and a negative input, and a capacitor having a capacitance value twice that of the capacitor. After subtracting from the input voltage of the first A / D converter a voltage corresponding to a code which is smaller than the output code of the converter by the voltage of the minimum resolution 2
Addition is performed according to the weight of the output of the means for amplifying ^N-1 times and the output of this operational amplifier, another 3-bit parallel A / D converter and two parallel A / D converters. It is composed of an adder that performs. Here, R1 to R7 are selected to have the same resistance value, and R0 and R8 are selected to have half the resistance value of R1. Also, R11 to R17 are selected to have the same resistance value, and R10 and R18 are selected to have half the resistance value of R11. Furthermore, S0, unlike S1 to S7, always switches between the input terminal and ground potential.

Next, the operation of this circuit will be described. In the initial state of operation, SF is turned on S0 to S7 are pushed to the input terminal side. Here first
The 3-bit A / D converter voltage comparators CP0 to CP7 are operated. Of the comparator of this first A / D converter, CP0 and
The CP1 is shown because it matches the format of the second-stage A / D converter, but it is not always necessary. A negative input voltage Vi Here, the potential and 0 (GND in FIG. 1) grounded and a negative reference potential -V _R. It is also assumed that each voltage comparator outputs logic 1 as an output when the input signal voltage is lower than the reference voltage. For example, if the input voltage is Suppose If each voltage comparator has no offset voltage, CP0 to CP4 will be logic 1 and CP5 to C
It becomes a logical zero until P8. But here, if the voltage comparator That is, in the case of the 3-bit A / D converter of this example, If there is variation in the offset of, the input voltage Vi Then CP4 may be zero. The input voltage Vi is Then CP5 may be logic 1. Conventional series-parallel type A
In these two cases, the normal A / D converter output could not be obtained with the / D converter. Now the above input Then on CP4 There is an offset voltage of. Then CP4 becomes logical 0 where it should have become logical 1. Therefore, when the output of the first parallel A / D converter is full scale in the negative direction, it is "100" at what is originally "101". At this time, "011" obtained by subtracting 1 from the output code is output to the first decoder. This data is multiplied by 2 ^3-1 = 4 and sent to the adder. 4 times can be realized by 2 bit shift. It can be realized by this decoder ROM, PLA or a simple logic circuit. At this time SF is opened. The output of each of the voltage comparators is sent to the first decoder and controls the switches from S2 to S7, and the switch that outputs logic 1 is turned to the −V _R side and outputs logic zero. Is pushed to the ground side. Here, S0 and S1 are always pushed to the ground side. From If S1 of this embodiment to S3 are brought down V _R side, from S0 and S4 until S7 being defeated to the ground. Now the R switch is V _R
If it is turned to the side, the output voltage of the operational amplifier that can be easily calculated using the law of conservation of charge is Is output. In the case of this example, k = 3. Becomes

This voltage is digitized by the parallel A / D converter in the next stage. First after the parallel A / D conversion in the next stage starts operation
The switches S0 to S7 associated with the parallel A / D converters in stages are turned to the input terminal side, and SF is closed. The offset voltage of the second-stage parallel A / D converter is also In the following cases, the output code of the second stage is "110". This result is added to the output 01100 from the first-stage parallel A / D converter, and as a result, 10010 5-bit data is obtained. The original analog input voltage is Therefore, if you write this as a digital value, it becomes 10010,
It can be seen that the correct result is obtained despite the 1-bit error in the first A / D converter.

In this example, the case where the 2-stage 3-bit A / D converter is used has been described, but the present invention is not limited to 3-stage each stage and is arbitrary. Further, by connecting a similar serial / parallel type A / D converter to the output of the operational amplifier, a configuration having three or more stages can be adopted. At this time, during the operation of the first stage, the second stage is inputting the differential voltage, during the operation of the second stage, the third stage is inputting the differential voltage, and the first stage can apply the next input voltage. . Therefore, it is possible to perform a so-called pipeline operation.

(Effects of the Invention) With the present invention, Even if a parallel type A / D converter having an error of is used, an A / D converter with higher accuracy can be realized. Therefore, it is possible to easily realize a high-speed A / D converter having a double or more accuracy by using a parallel type A / D converter, which is usually difficult to improve the accuracy as the speed is increased. . This means that the yield as an A / D converter can be dramatically improved when integrated into an integrated circuit.

[Brief description of drawings]

FIG. 1 is a diagram of a circuit that realizes a 5-bit A / D converter by using two 3-bit parallel A / D converters in a serial-parallel A / D converter according to the present invention. FIG. 2 is a block diagram showing the configuration of a conventional serial-parallel type A / D converter.

Claims (1)

[Claims] 1. A parallel type A / D converter, and a voltage corresponding to a code smaller than the output code of the A / D converter by the minimum resolution voltage is input to the first A / D converter. Means for subtracting from the voltage, and the resolution of the A / D converter is N
When the number of bits is set to 2 ^N-1 times, circuits consisting of means for amplification are cascaded in multiple stages, and the output code of each parallel A / D converter is set according to the weight of each A / D converter. An A / D conversion circuit having means for adding.