JPH0683160B2 - Multiplex demodulator - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplex demodulator used in, for example, an FM stereo tuner and an audio section circuit of a television receiver compatible with US audio multiplex broadcasting.

2. Description of the Related Art With recent advances in digital technology and LSI technology, it has become relatively easy to implement digital LSI in the field where processing was conventionally performed by analog circuits.

As a conventional technique, for example, there is a multiplex demodulation device which switches an input composite signal to extract a stereo demodulation signal by turning on and off a diode.

Hereinafter, the multiplex demodulation device as described above will be described with reference to the drawings.

FIG. 3 shows a circuit configuration of a conventional multiplex demodulation device. In FIG. 3, reference numeral 21 is a multiplex signal input terminal, 22 is a bandpass filter for extracting a pilot signal, 23 is a subcarrier generation circuit for generating a signal having a frequency twice that of the pilot signal, and 24 is a subcarrier generation. A switching signal generation circuit for generating a switching signal according to the polarity of the output signal of the circuit 23, 24a to 24e
Is a constituent element of the switching signal generating circuit 24,
Is a coupling transformer, 24b and 24c are resistors, 24d and 24e are diodes, 25 is a low-pass filter that extracts a composite signal from the input signal, 26 is an output signal of the switching signal generation circuit 24, and switches the output composite signal of the low-pass filter 25. A switching circuit for extracting a stereo signal, 26a to 26h are elements constituting the switching circuit 26, 26a, 26c, 26e to 26h are resistors, 26b is a transistor, 26d is a capacitor, 27 and 28 are left and right respectively. It is an output terminal.

The operation of the multiplex demodulation device configured as described above will be described below.

In the multiplex signal input from the input terminal 21, the pilot signal of frequency Fp obtained through the bandpass filter 22 is converted by the subcarrier generation circuit 23 into a signal of frequency 2 × Fp. When the polarity of the signal thus obtained is positive, the diode 24d becomes conductive and the potential on the anode side of the diode 24d becomes zero, that is, the left output terminal 27 is switched off.

At this time, the composite signal obtained through the low pass filter 25 is output from the right output terminal 28. On the contrary, when the polarity of the output signal of the subcarrier generating circuit 23 is negative, the diode 24e becomes conductive, the right output terminal is switched off, and the composite signal appears at the left output terminal 27. The state of the signal waveform during the above operation is shown in FIG.

Problems to be Solved by the Invention However, when the analog circuit is configured as described above, it is difficult to make the filter into an LSI, so that the circuit scale becomes large, the adjustment process is required, and the reliability due to secular change etc. Had sex problems.

The present invention has been made in view of the above problems, and provides a multiplex demodulation device that realizes stereo demodulation by digital signal processing.

Means for Solving the Problems In order to achieve this object, a multiplex demodulator of the present invention is a composite signal composed of a main signal in an audio band and a sub-signal modulated by a carrier suppression sideband (hereinafter referred to as DSB). A digital bandpass filter for extracting a pilot signal from an analog-digital converted multiplex signal including a pilot signal necessary for stereo demodulation, a first digital lowpass filter for extracting a composite signal, and the digital bandpass filter output A zero-crossing detector that detects a change point of the sign of the signal, a count that starts counting from zero by the output signal of the zero-crossing detector, a divider that divides the output data of the counter by 2, and a counter of the counter. A register that stores the output data of the divider according to the output signal. A comparator for detecting whether or not the output data of the counter and the output data of the register have the same value; a delay device for delaying the code data of the digital bandpass filter by the output signal of the comparator; A gate circuit that takes an exclusive OR of the code data of the digital band pass filter and the output data of the delay device; and a switching circuit that switches the output data of the first digital low pass filter by the output signal of the gate circuit,
It is composed of a second digital low-pass filter that extracts only an audio signal from the output data of the switching circuit.

By configuring the circuit digitally in this way,
The filter part can be integrated into LSI, the adjustment process can be reduced or automated, and the reliability will improve as it does not change over time.

Embodiment One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a multiplex demodulation device according to an embodiment of the present invention.

In FIG. 1, 1 is an input terminal for a multiplex signal which has been converted from analog to digital, 2 is a first digital low-pass filter (hereinafter referred to as the first LPF), 3 is a digital band-pass filter (hereinafter referred to as the BPF), 4 Is a zero-crossing detector, 5 is a counter, 6 is a divider, 7 is a register,
8 is a comparator, 9 is a delay device, 10 is an exclusive OR gate circuit
Reference numeral 11 is a switching circuit, 12 is a second digital low-pass filter (hereinafter referred to as a second LPF), and 13 is an output terminal.

The sign data of the data obtained from the input terminal 1 via the BPF 3 is input to the zero-crossing detector 4, and the detection signal of the zero-crossing detector 4 is connected to the reset terminal of the counter 5 and via the divider 6. Is input to the load terminal of the register 7 that stores the data of the counter 5, the output of the register 7 is connected to one input terminal 8a of the comparator 8, and the other input terminal 8b
The output of the counter 5 is connected to the exclusive OR gate circuit 10 which receives the output code data of BPF3 delayed by the delay device 9 using the output of the comparator 8 as a clock and the original output code data of BPF3. Is used as a control signal, and the two outputs of the switching circuit 11 that receives data from the input terminal 1 via the first LPF 2 are input to the second LPF 12, and the output of the second LPF 12 is connected to the output terminal 13.

The operation of the multiplex demodulation device configured as above will be described.

The pilot signal is extracted from the signal input from the input terminal 1 by the BPF 3. The output data of the counter 5, which is reset by the detection pulse of the zero-crossing detector 4 which detects the change point of the sign of the extracted pilot signal and which starts the counting operation immediately after that, becomes a half value by the divider 6. It is input to the data input terminal of the register 7. The value held by the register 7 is the value immediately before the counter 5 is reset. That is, the value stored in the register 7 is counted by the counter 5 during the difference Δt between the time tn _-1 at which the detection pulse immediately before the data is loaded and the time tn at which the detection pulse immediately before that is generated. It is half of the value. The comparator 8 compares the current value of the counter 5 with the value of the register 7 and outputs a pulse when they match. However, since the frequency of the pilot signal is substantially constant, the maximum count number of the counter 5 is also substantially constant. Therefore, the output pulse of the comparator 8 is always output approximately in the middle of the two time-adjacent detection pulses of the zero-crossing detector 4.

When the code data of the data output from the BPF 3 is delayed by the delay device 9 which uses the output pulse of the comparator 8 as a clock, data whose phase is shifted by 90 ° from the original code data is obtained. When the original coded data and the data whose phase is shifted by 90 ° are input to the exclusive OR gate circuit 10, a signal having a frequency twice that of the pilot signal is obtained. By this signal, the composite signal obtained from the input through the first LPF is input to the switching circuit 11 to separate the multiplex signal, and the second LPF allows only the audio signal to pass,
Extract the demodulated signal. Here, the switching circuit 11 is the first L
Exclusive-OR gate circuit with each bit of PF2 output data 1
The logical product of the output data of 0 is taken as the L channel output, and the logical product of each bit of the output data of the first LPF2 and the inverted output data of the exclusive OR gate circuit 10 is taken as the R channel output. I took it out. The state of the signal waveform during the above operation is shown in FIG. The divider 6 can be easily constructed by bit shifting.

EFFECTS OF THE INVENTION The present invention extracts a pilot signal from an analog-digital converted multiplet signal including a main signal in an audio band, a composite signal composed of a DSB-modulated sub-signal, and a pilot signal necessary for stereo demodulation. BPF, the first LPF that extracts the composite signal, and the B
A zero-crossing detector that detects the change point of the sign of the PF output signal,
A counter that starts counting from zero by the output signal of the zero-crossing detector, a divider that divides the output data of the counter by 2, and a register that stores the output data of the divider by the output signal of the counter. A comparator that detects whether the output data of the counter and the output data of the register have the same value, and a delay device that delays the code data of the BPF by the output signal of the comparator,
From the output data of the switching circuit, a gate circuit which takes the exclusive OR of the code data of the BPF and the output data of the delay device, the switching circuit which switches the output data of the first LPF by the output signal of the gate circuit, Since the second LPF for extracting only the audio signal is provided and the stereo demodulated signal is extracted from the second LPF, the demodulation of the multiplex signal as described above can be performed by all digital elements, and therefore the analog circuit has a large scale. It is possible to realize an excellent multiplex demodulation device that can improve reliability because the filter part can be integrated into an LSI, the adjustment process can be reduced or automated, and there is no secular change. Furthermore, since the blocks except the filter section can be configured with a relatively simple and small-scale circuit, the cost can be further reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a multiplex demodulator in one embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the present invention, FIG. 3 is a circuit diagram of a conventional example, and FIG. FIG. 6 is a waveform diagram for explaining an example operation. 1 ... input terminal, 2 ... first digital low-pass filter, 3 ... digital band-pass filter, 4 ... zero crossing detector, 5 ... counter, 6 ... divider, 7 ... register, 8 ... … Comparator, 9 …… Delayer, 10 …… Exclusive OR gate circuit, 11 …… Switching circuit, 12 …… Second
Digital low-pass filter, 13 ... Output terminal.

Claims (1)

[Claims] 1. A pilot signal from an analog-to-digital converted multiplex signal including a composite signal including a main signal in an audio band, a side signal modulated by carrier suppression sideband modulation, and a pilot signal required for stereo demodulation. , A first digital low-pass filter that extracts the composite signal, a zero-crossing detector that detects a change point of the sign of the output signal of the digital band-pass filter, and an output of the zero-crossing detector. A counter that starts counting from zero by a signal and output data of the counter
A divider for dividing by, a register for storing the output data of the divider by the output signal of the counter, a comparator for detecting whether the output data of the counter and the output data of the register have the same value, A delay device for delaying the code data of the digital band pass filter by the output signal of the comparator, a gate circuit for taking an exclusive OR of the code data of the digital band pass filter and the output data of the delay device, and the gate. A multiplex demodulation device comprising a switching circuit for switching the output data of the first digital low-pass filter according to the output signal of the circuit, and a second digital low-pass filter for extracting only an audio signal from the output data of the switching circuit.