JPH0683173B2 - Speed conversion bit multiplex circuit device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a circuit for increasing the bit rate of digital data to multiplex additional bits, and particularly transmits arbitrary data at an arbitrary beat rate without input of an external clock. Speed conversion bit multiplexing circuit device.

[Conventional technology]

In the conventional speed conversion bit multiplexing circuit device, the bit rate (secondary clock rate) after speed conversion is phase-compared according to the bit rate (primary clock rate) of the data input before speed conversion, and the voltage controlled oscillator ( The secondary clock rate is determined by adding a control voltage to VCO).

That is, in FIG. 2, the inputs from the data input terminal 18 and the primary clock input terminal 19 are the speed conversion bit multiplexing circuits.
When input to 11, the PLL (phase-locked loop) voltage output of the phase comparator in the speed conversion bit multiplexing circuit 11 and VCO14
Determines the secondary clock rate needed to add bits to the data. This clock is input to the VCO input terminal of the speed conversion bit multiplexing circuit 11, and the data obtained by multiplexing the speed converted clock and the additional bit is output to the data output terminal 12 and the clock input terminal 13.

Although data input is usually input from outside the device,
In the case of sending certain specific data to the device, for example for testing, the clock generator 1 is operated by the switches 20 and 21.
6 and pattern generator 17, select this clock oscillator 16
The data generated by the pattern generator 17 based on the above is input to the speed conversion bit multiplexing circuit 11.

[Problems to be Solved by the Invention]

In the above-described conventional circuit device, when transmitting internally generated data for testing, the clock oscillator 16 as a primary clock is required. This is because the secondary clock is determined by the phase comparison with the primary clock, so that the primary clock must have a frequency corresponding to the variable range of the VCO of the secondary clock. Therefore, in the conventional multiplex circuit, it is necessary to provide a clock oscillator used at the time of testing, which causes a problem that the circuit configuration becomes complicated and the cost becomes high.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a speed conversion bit multiplexing circuit device which does not require a clock oscillator and can be simplified in structure.

[Means for Solving the Problems]

The speed conversion bit multiplexing circuit device of the present invention is configured so that an arbitrary control voltage can be applied to the VCO that generates the secondary clock of the speed conversion bit multiplexing circuit, and the output part of this VCO is divided. The speed conversion bit multiplex circuit is provided with a clock frequency divider for inputting as a primary clock, and the output of this clock frequency divider and the primary clock that can be input to the speed conversion bit multiplex circuit device along with digital data are selected. It is configured to be input to the speed conversion bit multiplexing circuit.

[Action]

In the above-mentioned configuration, since the primary clock is generated by using the output of the VCO, the independent clock oscillator is not required, the data transmission of the arbitrary clock can be performed with the arbitrary control voltage, and the circuit configuration can be simplified. Can be planned.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a structure for transmitting test data for testing an apparatus is shown. That is, the configuration shows that the primary clock is not supplied from the outside.

In the figure, the data output end of the speed conversion bit multiplexing circuit 1
DATA OUT and clock output terminal CLK OUT are connected to data output terminal 2 and clock output terminal 3, respectively, and PLL output terminal P
VCO4 is connected between LL V and VCO control terminal VCO CLK IN. An external voltage control terminal 5 is connected to the input side of this VCO 4, and an arbitrary voltage is applied to it from the outside. A clock frequency divider 6 is connected to the output side of the VCO 4, and its output is input to the clock input terminal CLK IN of the speed conversion bit multiplexing circuit 1 and the pattern generator 7, respectively. The output of the pattern generator 7 is input to the data input terminal DATA IN of the speed conversion bit multiplexing circuit 1.

According to this structure, first, an arbitrary voltage is externally supplied to the external voltage control terminal 5 of the VCO 4, and the oscillation frequency of the VCO 4 is forcibly set to an arbitrary voltage. The output clock of VCO4 is input to the speed conversion bit multiplexing circuit 1, the secondary clock is determined, and the clock is input to the frequency divider 6 at the same time. The frequency division ratio of the frequency divider 6 is given by the following equation.

Frequency division ratio = n / (n + 1) where n: number of data bits for one additional bit.

That is, in bit multiplexing, one additional bit is multiplexed with the data bit, and the secondary clock is n / (n +
If the frequency is divided into 1), speed conversion can be synchronized between the primary clock and the secondary clock.

Next, the clock frequency-divided by the frequency divider 6 is input to the pattern generator 7, and this clock and the output of the pattern generator 7 are input to the speed conversion bit multiplexing circuit 1 to be used as the primary clock input and data input. . As a result, additional bits are multiplexed with the output data of the pattern generator 7, and the data and clock after speed conversion are output to the terminals 2 and 3.

Therefore, in this circuit, since the output of VCO4 is frequency-divided to generate the primary clock, an independent clock oscillator is not required, and the structure can be simplified.

Needless to say, external data can be input by attaching switches as shown in FIG. 2 to the data input terminal and the clock input terminal of the speed conversion bit multiplexing circuit 1 in FIG.

〔The invention's effect〕

As described above, according to the present invention, the VCO control voltage is externally applied to generate the secondary clock, and the secondary clock is divided to generate the primary clock. Therefore, the clock for generating the primary clock is generated. Arbitrary data can be transmitted without using an oscillator, and the circuit configuration can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional multiplex circuit. 1,11 …… Speed conversion bit multiplexing circuit, 2,12 …… Data output terminal, 3,13 …… Clock output terminal, 4,14 …… VCO, 5…
… External voltage control terminal, 6 …… Clock divider, 7,17 ……
Pattern generator, 16 …… Clock oscillator, 18 …… Data input terminal, 19 …… Clock input terminal, 20,21 …… Switch.

Claims (1)

[Claims] 1. A speed conversion bit multiplexing circuit for multiplying digital data input based on a primary clock to a bit rate of a secondary clock higher than this output from a voltage controlled oscillator to multiplex additional bits. In the device, the voltage controlled oscillator for generating the secondary clock is provided with an external voltage control terminal so that an arbitrary control voltage can be applied, and a part of the output of the voltage controlled oscillator is divided to perform the speed control. A clock frequency divider for inputting as a primary clock to the conversion bit multiplexing circuit is provided, and the output of the clock frequency divider and the primary clock that can be input along with the digital data are selectively input to the speed conversion bit multiplexing circuit. A speed conversion bit multiplex circuit device characterized by being configured to input.