JPH0683179B2 - Spread spectrum receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention is suitable for a receiver used in a spread spectrum communication system, particularly when there is a level difference in the correlation spike level between the positive polarity and the negative polarity of the correlation output. The present invention relates to a correlation pulse generation circuit.

B. Summary of the Invention A correlation pulse generation circuit of a receiver used in a spread spectrum communication system according to the present invention generates a threshold value from a peak hold circuit that holds a peak value of a correlation spike of positive and negative polarities. It is composed of a threshold value setting circuit and a comparison circuit that generates a correlation pulse by comparing the threshold value with the correlation spike, and if there is a level difference between the positive and negative correlation spike levels of the correlation output, hold them independently. And the threshold value can be independently generated based on it.

C. Conventional technology In the spread spectrum communication system, even if the correlator output fluctuates, it is necessary to follow it and obtain an appropriate threshold value to detect the target correlation output.

As a conventional system, for example, there is a system shown in Japanese Patent Publication No. 60-5639 "Reception circuit in spread spectrum communication system".

In this method, the positive and negative correlation spikes of the matched filter output are respectively peak-held by the peak-hold circuit, then synthesized, and a threshold value proportional to this peak-hold value is generated, and the threshold circuit is used to detect the correlation spike
Data demodulation is performed, and its circuit configuration is shown in FIG. In FIG. 3, 21 is a correlator, 22 is a peak hold circuit,
23 is an arithmetic circuit, 24 is a flip-flop, 25 is a shift clock generator, 26 is a shift circuit, 27 is a PN code, 28 is a delay circuit, 29 and 30 are multipliers. Play a role. That is, the peak hold circuit 31
Holds a positive peak, and the peak hold circuit 32 holds a negative peak. Variable peak resistance R ₃
A threshold value is obtained through the comparator 33, the comparator 33 detects a positive correlation spike, and the comparator 34 detects a negative correlation spike.

D. Problems to be Solved by the Invention However, this circuit configuration has the following problems. When the peak hold circuit 22 completely peak-holds the correlation spike, the width of the correlation spike is very small.
The time constant due to the internal resistance of the diode D ₁ or D ₂ and the capacitor C ₁ or C ₂ must be made very small. That is, it is necessary to reduce the charging time constant.

On the contrary, when holding this peak value for one cycle of the correlation spike, in order to suppress the decrease of the hold value called droop, the resistance R ₁ or R ₂ and the capacitor C ₁ or
The time constant of C ₂ must be increased. That is, it is necessary to increase the discharge time constant.

With the circuit configuration shown in FIG. 3, the discharge time constant R ₁ C ₁ or R ₂ C ₂ of the peak hold circuit 31 or 32 is set in setting the threshold value that changes corresponding to the changing correlation spike φ (t). It is clear that the must be large, as shown in FIG.

Next, when considering the follow-up to the fluctuation of the peak value, in the case of a peak-hold circuit having a good hold property, that is, a peak-hold circuit having a large discharge time constant, the follow-up property to the decrease of the peak value becomes poor. This will be described with reference to FIG.

When the correlation spike φ (t) (in this case, the data corresponds to 1,1,0,0,) causing the level fluctuation as shown in FIG. 5 is input to the peak hold circuit 22, The values of the peak hold circuits 31 and 32 are S _{A in} b) and c).
And S _B.

Here, when the correlation spike 2 smaller than the positive correlation spike 1 or the correlation spike 4 smaller than the negative correlation spike 3 is obtained, the capacitor C ₁ or C ₂
Will not be charged and will continue to discharge. That is, when the peak value decreases more than the droop due to the discharge, the peak value cannot be detected. Furthermore, the threshold value S _C and the threshold S _C threshold S _D multiplied by -1 in multiplier 30 the is, FIG. 5 a)
When set as above, the correlation spike 1 can be detected, but the correlation spikes 2, 3, and 4 cannot be detected.

As a result, the demodulated data d (t) becomes erroneous with respect to the input data. In FIG. 5, d) and e) are the third
The waveforms of S _E and d (t) are shown in the figure, respectively.

That is, when the correlation spike φ (t) fluctuates as shown in FIG. 5A, it is difficult to detect the correlation spike as long as the same positive and negative thresholds S _C and S _D are used.

Further, as shown in FIG. 6, even when the received signal does not fluctuate in level, there is a difference in level between the positive and negative correlation spikes due to performance problems of the circuits and elements used (see In the case of FIG. 6, the positive correlation spike is always larger than the negative correlation spike.) Similar to the above, it is difficult to detect the correlation spike by the obtained thresholds S _C and S _D via the peak hold circuit 22. .

An object of the present invention is to set an appropriate threshold and set a correlation pulse even when the correlator output fluctuates according to the fluctuation of the received signal level and there is a level difference between the positive and negative correlation spike levels of the correlation output. By providing the above, it is possible to provide a circuit capable of performing reliable data demodulation.

E. Means for Solving the Problems In order to achieve the above object, a correlation spike is obtained by correlating a received signal and a reference signal by a correlator according to the present invention, and the correlation spike is correlated through a comparison circuit. In a spread spectrum receiver for obtaining a pulse, a first peak hold circuit that holds a peak value of a positive correlation spike, a first threshold setting circuit that generates a first threshold from the peak value, and a first threshold value And a first comparison circuit for generating a first correlation pulse by comparing the correlation spike with
A second peak hold circuit that holds the peak value of the negative correlation spike, a second threshold setting circuit that generates a second threshold from the peak value, and a second threshold comparison circuit that compares the second threshold with the correlation spike. The gist is to include a second comparison circuit for generating the correlation pulse of

In an advantageous aspect of the present invention, first and second hold circuits are provided between the first and second peak hold circuits of positive and negative polarities and the first and second threshold setting circuits, respectively. The outputs of the first and second hold circuits are applied to the first and second threshold value setting circuits, respectively. Further, the means for clearing the hold value held by the first and second peak hold circuits at a desired timing, and the first and second threshold value setting circuits,
Outputting a value obtained by multiplying the output values of the first and second hold circuits by a multiplication coefficient, and outputting the hold values of the first and second peak hold circuits by the first and second hold circuits. A control means for controlling whether to hold or not is included. The control means is controlled in response to the outputs of the first and second comparison circuits, and the multiplication coefficient is controlled by the CPU.

F. Examples Hereinafter, the present invention will be described in more detail using examples with reference to the drawings, but they are merely examples, and various modifications and improvements can be made without departing from the scope of the present invention. Of course it is possible.

FIG. 1 is a block diagram showing the configuration of a correlation pulse generating circuit used in a spread spectrum receiver according to the present invention, and FIG.
The drawing is a timing chart of signals in each part of the circuit shown in FIG. In FIG. 1, 1 is a correlator and PDI (Pos
t Detection Integration: Integrator circuit) 2, A / D converter, 3 Inversion circuit, 4, 5, 8, 11 Latch circuit, 6, 7, 14, 15
Is a comparison circuit, 9 and 10 are gate circuits, 12 and 13 are threshold value setting circuits, and 16 and 17 are peak hold circuits.

The A / D converter 2 A / D-converts the correlation spike a based on the sampling signal b to obtain an output c. Here, the result of sampling the period in which the correlation spike a exists is A / D
It is in the sloped part of the output c of the converter 2.

Next, the output c of the A / D converter 2 is branched into the path 1 and the path 2. Path 1 is a path for detecting a positive correlation spike, and path 2 is a path for detecting a negative correlation spike.

The path 2 can be realized with the same circuit configuration as the path 1 by inverting the polarity of the N-bit data of the output c of the A / D converter 2. Therefore, after the A / D converter 2, the path 2 is input to the inverting circuit 3. In the path 2, the circuit configuration of the inverting circuit 3 and the subsequent parts is the same as that of the path 1, so the operation of only the path 1 will be described.

The output c of the A / D converter 2 is the latch circuit 4 and the comparison circuit 6.
Entered in. In the comparison circuit 6, the output c of the A / D converter 2
And the data f stored in the latch circuit 4 are compared,
When it is determined that the data of the output c of the A / D converter 2 is larger, the pulse output d is obtained. Using this pulse d as a trigger, the latch circuit 4 stores the data of the output c of the A / D converter 2 and updates the data f of the latch circuit 4.

In this way, the output c of the A / D converter 2 and the data f of the latch circuit 4 are sequentially compared, and the data f stored by the latch circuit 4 is stored.
To form the peak hold circuit 16 for obtaining the maximum value of the output c of the A / D converter 2.

The latch circuit 4 outputs a clear signal e every period of the correlation spike.
The content f stored by is cleared and a peak hold for one cycle of a new correlation spike is performed. The cycle of the pulse of the clear signal e is the same as the cycle of the correlation spike. That is, with the peak hold circuit having this circuit configuration, the peak value for one cycle of the correlation spike can be reliably held.

Next, the maximum value of the output c of the A / D converter 2 for one cycle of the correlation spike stored in the latch circuit 4 is cleared by the signal h before the latch circuit 4 is cleared by the clear signal e.
Is stored in the latch circuit 8 as a trigger. Here, when the positive correlation pulse j is input before the pulse of the clear signal e is input, the gate circuit 9 passes the enable signal g and inputs the signal h to the latch circuit 8.

When the positive correlation pulse j does not exist, the gate is closed, nothing is output to the signal h, and the latch circuit 8 does not receive the trigger pulse, so the output i of the latch circuit 8 does not change.

The latch circuit 8 holds the peak value for one cycle of the correlation spike, and due to the presence of the positive correlation pulse, the peak value data for the one cycle of the correlation spike currently held is updated in the next one cycle of the correlation spike. Determine whether to do or not.

By adopting such a configuration, the peak value of the correlation spike can be surely held within one cycle of the correlation spike a, the fluctuation of the peak value can be followed, and the malfunction when the polarity of the correlation spike changes. Can be eliminated.

Next, the output data i of the latch circuit 8 is input to the threshold setting circuit 12. Here, the output data i of the latch circuit 8 and the control signal k representing the multiplication coefficient are calculated to generate the threshold value l. The threshold l is an N-bit digital signal. The control signal k is generated by, for example, a CPU or the like.

Next, the threshold value l obtained by the threshold value setting circuit 12 is input to the comparison circuit 14. The comparison circuit 14 compares the output c of the A / D converter 2 with the threshold value l, and the output c of the A / D converter 2 larger than the threshold value l.
When is input, the output j is obtained. Thus, the correlation pulse j corresponding to the correlation spike is obtained.

Further, supplementally, the peak value of the output c of the A / D converter 2 within one cycle of the correlation spike obtained by the peak hold circuit 16 is stored in the latch circuit 8 to set the threshold l in the next cycle. You can do it. Even if there is no output c of the A / D converter 2 that exceeds the threshold value l within the one cycle and the correlation pulse j is not obtained, the data i of the latch circuit 8 is still held, so that The threshold value l is set to the same value in one cycle.

Therefore, as shown in FIG. 2, the data f stored in the latch circuit 4 of the peak hold circuit 16 in the period in which the negative correlation spike exists indicates the noise level, but the previous period As long as the peak value of 1 is held in the latch circuit 8, the comparator circuit 14 does not erroneously detect the correlation pulse j.

Further, the threshold l for detecting the correlation spike in the next cycle of the negative correlation spike is the output i of the latch circuit 8.
Can be set by, and only the correlation spike can be detected.

From the above, by branching to the paths 1 and 2, the peak hold can be independently performed, and the threshold value 1 can be independently set, and even when the correlation spike a changes, the positive and negative poles of the correlation spike a are also changed. Even if there is a level difference, there is no problem such as erroneous detection.

Although the above-described peak hold circuit configuration is premised on digital signal processing, the present invention can be applied by replacing the latch circuit with a hold circuit even when analog signal processing is performed.

G. Effects of the Invention As described above, according to the present invention, even when a correlator output fluctuation occurs due to a fluctuation of the input level, and when there is a level difference between the positive and negative correlation spike levels of the correlator output. However, there is an advantage that accurate data demodulation can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a correlation pulse generating circuit used in a spread spectrum receiver according to the present invention, and FIG.
The figure is a timing chart of signals in each part of the circuit shown in FIG. 1, FIG. 3 is a circuit diagram of a conventional correlation pulse generation circuit, and FIG. 4 is a voltage waveform when the discharge time constant is small and when the discharge time constant is large. 5 and FIG. 5 are signal waveform diagrams in each part of the circuit shown in FIG. 3, and FIG. 6 is a signal waveform diagram in each part of the circuit shown in FIG. 3 when there is a level difference in the correlation spike. 1 ... Correlator and PDI, 2 ... A / D converter, 3 ... Inversion circuit, 4,5,8,11 ... Latch circuit, 6,7,14,15 ... Comparison circuit, 9,10 ...... Gate circuit, 12,13 …… Threshold setting circuit, 16,
17 …… Peak hold circuit.

Claims (7)

[Claims] 1. A spread spectrum receiver for obtaining a correlation spike by correlating a received signal and a reference signal with a correlator, and obtaining the correlation pulse through the comparison circuit, comprising: (a) a positive correlation spike A first peak hold circuit that holds the peak value of (b) a first threshold value setting circuit that generates a first threshold value from the peak value, (c) a first threshold value and a correlation spike (D) a second peak hold circuit for holding the peak value of the negative correlation spike, and (e) a second threshold value for generating a second threshold value from the peak value. A spread spectrum receiver including: a setting circuit; and (f) a second comparison circuit that generates a second correlation pulse by comparing a second threshold with a correlation spike. 2. The first and second positive and negative polarities
Between the peak hold circuit and the first and second threshold value setting circuits, respectively.
The spread spectrum receiver according to claim 1, wherein the outputs of the first and second hold circuits are provided to the first and second threshold value setting circuits, respectively. 3. A spread spectrum receiver according to claim 1, further comprising means for clearing the hold values held by the first and second peak hold circuits at desired timing. 4. The first and second threshold value setting circuits output a value obtained by multiplying output values of the first and second hold circuits by a multiplication coefficient. Spread spectrum receiver according to the item. 5. A control means for controlling whether or not the hold values of the first and second peak hold circuits are held by the first and second hold circuits. A spread spectrum receiver according to the first and second aspects. 6. A spread spectrum receiver according to claim 5, wherein said control means is controlled in response to the outputs of said first and second comparison circuits. 7. The spread spectrum receiver according to claim 4, wherein the multiplication coefficient is controlled by a CPU.