JPH0683184B2 - Sequential decoding device - Google Patents

Description

The present invention relates to a successive decoding device.

[Conventional technology]

In order to detect and correct a transmission error of data, the data is divided into several information symbols, convolutionally coded by an error correction encoder to form a code symbol, and the transmitted code symbol is an error correction decoder (hereinafter referred to as a decoder). It is said that sequential decoding is performed using the Fano algorithm.

Such an error correction encoder comprises a state holding circuit and a function generating circuit. The state holding circuit is composed of, for example, a shift register, holds an internal state, and changes the internal state by inputting an information symbol. The function generator inputs internal states and generates code symbols.

The received signal (hard decision thereof) received by the decoder corresponding to one code symbol does not always match the delayed code symbol due to a transmission error.

If the decoder proceeds decoding in code symbol units,
It has a circuit (hereinafter referred to as encoder duplication) having the same function as the corresponding error correction encoder, and inputs all possible information symbols to the encoder duplication each time a received signal corresponding to one code symbol is received. Each of the code symbols output by the encoder replica at this time is compared with the received signal received, and the information symbol that gives the closest code symbol to the received signal is estimated to be the transmitted information symbol. A likelihood called Fano likelihood is used as a measure of closeness. In the Fano algorithm, basically, the information symbol sequence having the largest cumulative likelihood of Fano likelihood is determined to be the transmitted information symbol sequence.

However, if transmission errors occur frequently, it is possible that the wrong information symbol is determined to be the sent information symbol. Once an erroneous decision is made, the internal state of the encoder copy after that is inconsistent with the internal state of the error correction encoder, and after that, even if you try to find an information symbol with a large Fano likelihood, it will not be found, so in the past It is possible to detect that an incorrect decision has been made. When it is detected that an erroneous decision is made, the internal state of the encoder copy is returned to the past state, and the information symbol having the next largest Fano likelihood is sent after the information symbol selected in the past. Judge and retry the decoding. Even if an information symbol having the next largest Fano likelihood is to be found, if it cannot be found because it has already been searched, it returns to another past state and performs the same operation. Since decoding may be performed by repeating trial and error in this way and the output code result may be changed later, the decoder requires a buffer for the input received signal and a buffer for the decoding result.

The Fano algorithm described above is based on the American Fano (R.
Invented by M. Fano), IEEE Transactions on Inf
ormation Theory, IT-9 (1963) (US) p. 64-74. The error correction encoder and decoder as described above can be realized by a circuit described in US Pat. No. 3,665,396 of George David Forney, Jr., for example.

By the way, in order to compare the code symbol output from the encoder duplication with the received signal, 1 to 1
It is necessary to know whether it corresponds to a code symbol. In other words, it is necessary to perform this comparison in code synchronization with the received signal. Normally, the received signal does not include this code synchronization timing information in a simple form like the synchronization signal, so that the conventional sequential decoding device performs code synchronization by trial and error as described below.

If the code synchronization is incorrect, it is equivalent to including a transmission error in the received signal with an extremely high probability, so decoding does not proceed,
Received signal buffer overflows. If this overflow determines that the code synchronization is incorrect,
The phase of code synchronization is shifted by one code bit of the code symbol, and thereafter, decoding is performed from the received signal newly input to the received signal buffer. If decoding does not proceed due to this code synchronization attempt and the buffer of the received signal overflows, the same attempt is performed again. Assuming that one code symbol is composed of n code bits, the number of possible phases of code synchronization is n.
-1) Code synchronization is always correct if repeated 1 times. Assuming that the decoding does not proceed at all if the code synchronization is incorrect, one trial takes time to accumulate the received signal in the entire buffer of the received signal, and (n-1) times this time is the code. It is the maximum value of synchronization pull-in time. In addition, every time the trial is performed, all reception signals accumulated in the buffer at that time are discarded.

[Problems to be Solved by the Invention]

As described above, the conventional iterative decoding apparatus has the maximum time (n-
1) A long code synchronization pull-in time is required, and there is a drawback that the received signal received during this period cannot be decoded.

An object of the present invention is to provide a sequential decoding device in which the code synchronization pull-in time is short.

[Means for Solving the Problems]

A successive decoding apparatus of the present invention is a received signal storage means capable of storing a predetermined number of received signals obtained by transmitting and demodulating a modulated signal modulated by a code symbol of a convolutional code, and the received signal. Decoding result storage means capable of storing the decoding result of the first number, and the received signals are sequentially written into the received signal storage means, and at the same time, the decoding results already written from the decoding result storage means are written. When sequentially decoding and outputting to the outside, performing sequential decoding in code synchronization with the received signal read from the received signal storage means by trial and error, and when the decoding is completed, writing the decoding result to the decoding result storage means At the same time, the received signal written next to the received signal that has just been decoded is read out from the received signal storage means and an attempt is made to decode it. When the received signal written before the received signal read out immediately before from the received signal storage means is read out, at the same time when the received signal to be read out is decoded previously, the decoding result storage means Then, the decoding result written in is read out to perform decoding again, and the received signal written immediately before the received signal read immediately before from the received signal storage means is rewritten by the newly input received signal. Each time it is determined that there is an error in the code synchronization due to the delay in decoding, the code synchronization is performed again, and the predetermined number is predetermined from the latest received signal written in the received signal storage means, which is less than the first number, And a sequential decoding means for repeating the reset operation for reading the received signal previously written by the second number and attempting decoding.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings illustrating an embodiment.

FIG. 1 is a block diagram showing an embodiment of the successive decoding apparatus of the present invention.

Reference numeral 1 is a RAM for buffering a received signal, and 2 is a RAM for buffering a decoding result. The RAMs _{1 and 2} each have an address number of m ₁ . A decoding processing unit 3 controls writing and reading of the RAMs ₁ and ₂ by the control signals B ₁ and B ₂ , and therefore outputs an address signal and sequentially decodes the received signal. D
₀ is a received signal input from a demodulator (not shown) at the receiving end, and CL is a clock signal of the received signal D ₀ .

The decoding processing unit 3 includes counters 31 and 32, a selector 33, a control circuit 34, and a decoding circuit 35. The counter 31 counts the clock signal CL and outputs the count value as an address signal.
A counter m ₁ binary outputs as al. Counter 32 too
m _1- ary counter, address signal A 2 and control signal B ³
Is output. The selector 33 is a control signal from the control circuit 34.
Select either address signal A1 or A2 with B6
Output to AM1 and AM2.

When a new reception signal D ₀ is input, the counter 31 counts the clock signal CL and the address signal A 1 increases by one. At this time, the control circuit 34 responds to the control signal B5 from the counter 31 and outputs the control signal B6. The selector 33 outputs the address signal A1 in response to the control signal B6 to write the received signal D ₀ input to the address A1 of the RAM1 and read the decoding result E written to the address A1 of the RAM2. Output to the outside. Therefore, the address signal A1 is, shows the latest address of the received signal D _0, which is written to RAM1.

Meanwhile, the address signal A2 indicates the address in the RAM1 of the received signal D ₁ to the decoding circuit 35 is currently decoding.
When the decoding circuit 35 completes decoding the reception signal D ₁ just read from the RAM ₁ , the decoding circuit 35 outputs a control signal B4 informing the completion of decoding. The control circuit 34 outputs control signals B1, B2, B3, B6 in response to the control signal B4. The selector 33 outputs the address signal A2 in response to the control signal B6. The decoding circuit 35 writes the decoding result D ₂ in the address A2 of the RAM 2 under the control of the control signal B2. The counter 32 increments the address signal A2 by one in response to the control signal B3 from the control circuit 34. Then, the decoding circuit 35 reads the next reception signal D ₁ from the address A 2 (incremented by 1) of the RAM 1 by the control signal B ₁ , and shifts to the next decoding process.

Since the cycle of the decoding process is sufficiently shorter than the cycle of the clock signal CL, if the received signal D ₀ has few transmission errors and the decoding proceeds smoothly, the address signal A2 catches up with the address signal A1 and the latest received signal written in RAM1. Decoding process of D ₀ comes to be performed. As a result, since there is no new received signal D ₁ to be read any more, when the address signal A2 becomes equal to the address signal A1, the control circuit 34 outputs the control signal B4, and the decoding circuit 35 responds to the control signal B4 and decodes it. Suspend processing.

When retracting the decoding, the control circuit 34 controls the control signals B1, B2, B3.
Is output. The counter 32 decrements the address signal A2 by one in response to the control signal B3. Decoding circuit 35 is a control signal
Outputs B1, B2, B3. The counter 32 decrements the address signal A2 by one in response to the control signal B3. The decoding circuit 35
With the control signals B1 and B2, the reception signal D ₁ (which has been previously decoded) and the decoding result D ₂ are read from the address A2 of the RAMs ₁ and ₂ , and the decoding is performed again.

In this way, the decoding circuit 35 successively decodes the received signal D ₁ .

The reception signal D ₁ (the address in the RAM ₁ is A2) immediately before the reception signal D ₁ read from the RAM ₁ immediately before (the address is A2-1) is rewritten by the newly input reception signal D ₀ ( The address of this writing is by A1),
In other words, if the decoding is delayed until A2-1 = A1,
Next, the received signal D ₀ that has not been completely decoded (address A2) will be rewritten by the newly input received signal D ₀ . Therefore, the decoding circuit 35 determines that the RAM1 has overflowed if the decoding is delayed until A2-1 = A1.

When the quality of the transmission path deteriorates and many transmission errors occur in the received signal D ₀ , the decoding does not proceed and the RAM 1 overflows. If the transmission quality is normal, the number of addresses m ₁ of RAM1 (and 2) is set so that the probability of overflow of RAM1 becomes extremely small.

By the way, since the decoding processing unit 3 performs code synchronization by trial and error, as will be described in detail below, the RAM 1 overflows due to this code synchronization error.

When the control circuit 34 determines that the RAM1 has overflowed due to a code synchronization error, it outputs the control signals B3, B4, B1. The counter 32 responds to the control signal B3 and outputs the address signal A2.
Is reset to a value smaller than address A1 by m ₂ (however, m ₂ <m ₁ ). The decoding circuit 35 uses 1 of the code symbols of the convolutional code.
Shifting the phase of the symbol synchronism by bits, resuming reading decodes the received signal D ₁ from (reset) address A2 of RAM1 by a control signal B1. In other words, the received signal D ₀ written m ₂ times before the latest received signal D ₀ written in the RAM ₁ is read and the decoding process is performed. Even if the code synchronization is redone and the address signal A2 is reset (these are collectively referred to as a reset operation) and the code synchronization is not correct and the RAM1 overflows again, the reset operation is performed again. Assuming that the code synchronization is not correct after the reset operation and the RAM1 overflows again, assuming that decoding does not proceed at all during this period, the period of the clock signal CL is approximately (m ₁ −m ₂ ).
Doubled. If the number of bits constituting one code symbol is n, shifting the phase of code synchronization by one code bit is repeated a maximum of (n-1) times, in other words, if the reset operation is repeated a maximum of (n-1) times. It has already been mentioned that code synchronization is always correct.

If the code synchronization is correct, the code will proceed smoothly,
It can be expected that RAM1 will no longer overflow even if (m ₁ −m ₂ ) is made much smaller than m ₁ . As described above, since the conventional sequential decoding device resets the address signal A2 equally to the address signal A1 after re-execution of the code synchronization, after the reset operation, the cycle of the clock signal CL is almost equal before the RAM1 overflows again. It took ₁ m times as long. In the embodiment shown in FIG. 1, since this time is approximately (m ₁ −m ₂ ) times the period of the clock signal CL,
The maximum required time for code synchronization acquisition in the embodiment shown in FIG. 1 is (m ₁
-M ₂ ) / m ₁ In this way, by reducing (m ₁ −m ₂ ), it is possible to shorten the code synchronization lead-in time of the embodiment shown in FIG.

The number of received signals D ₀ that cannot be decoded and discarded for each reset operation is (m ₁ −m ₂ −1). Therefore, the amount of the received signal D ₀ to be discarded during the code synchronization pull-in is also reduced at a rate substantially equal to the rate of shortening the code synchronization pull-up maximum required time as compared with the conventional sequential decoding device.

Although the code synchronization has been described here as accurately dividing one code symbol from the received data sequence (herein referred to as branch synchronization), when the orthogonal modulation method is adopted as the transmission path modulation method. Synchronization function to remove the 4-phase phase uncertainty of the above, and resynchronization function to lead from the buffer overflow state to the steady state well known in the successive decoding method, even if interpreted as code synchronization. You can However, at this time, it is necessary to separately determine whether the branch synchronization, the synchronization for removing the four-phase phase uncertainty, or the resynchronization in the sequential decoding method is performed for the overflow of RAM1.

〔The invention's effect〕

As described in detail above, the successive decoding apparatus of the present invention determines that there is an error in the code synchronization by overflowing the buffer of the reception signal and re-executes the code synchronization. Since the decoding cycle is restarted from the received signal written in the buffer to shorten the repeat cycle of code synchronization redo, there is an effect that the code synchronization lead-in time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the successive decoding apparatus of the present invention. 1,2 ...... RAM, 3 …… Decoding processing unit, 31,32 …… Counter, 3
3 ... Selector, 34 ... Control circuit, 35 ... Decoding circuit.

Claims (1)

[Claims] 1. A reception signal storage unit capable of storing a predetermined number of reception signals obtained by transmitting and demodulating a modulation signal modulated by a code symbol of a convolutional code, and a decoding result of the reception signal. And a decoding result storage means for storing the received signal in the received signal storage means, and at the same time sequentially reading the already-decoded decoding result from the decoding result storage means. When the decoding is completed, the decoding result is output to the outside and the decoding is sequentially performed by code synchronization with the reception signal read out from the reception signal storage means by trial and error. When the received signal written next to the received signal that has just been decoded is read out from the signal storage means and an attempt is made to decode it, and there is a possibility that the previous decoding has an error When the previous reception signal written before the reception signal read out immediately before from the reception signal storage means is read out, the reception signal to be read out at the same time is written in the decoding result storage means when the decoding is completed previously. The decoding result is read and the decoding is redone, and the decoding is performed until the received signal written immediately before the received signal read immediately before from the received signal storage means is rewritten by the newly input received signal. Every time it is determined that there is an error in the code synchronization, a second number smaller than the first number, which is predetermined from the latest received signal written in the received signal storage means by re-executing the code synchronization, And a successive decoding processing means for repeating the reset operation for reading the received signal written before and attempting decoding.