JPH0683282B2 - Timing synchronizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A jitter amount is improved by converting a phase error into an analog amount and feeding it back in a PLL circuit.

[Industrial application field]

The present invention relates to a timing PLL circuit synchronization system used in a modem.

The conventional timing PLL circuit has a drawback that the suppression of jitter is incomplete, and improvement thereof has been strongly demanded.

[Conventional technology]

In modems that adopt modulation methods such as PSK and QAM,
The receiving side uses the circuit of the following timing synchronization system to match the sampling frequency and phase.

FIG. 4 is a diagram showing an example of a conventional timing synchronization method.

In the figure, 1 is an AD converter, 2 is a timing extraction circuit, 3
Is a vector conversion circuit, 4 is a low-pass filter, 5 is a polarity determination circuit, and 6 is a voltage controlled oscillator. The same symbols represent the same objects throughout the drawings.

When the received signal enters the modem, it is first input to the A / D converter 1, where it is sampled at the frequency f (for example, 9600 bps) and then input to the digital signal processor DSP.

Conventionally, signal processing in this kind of modem is performed by data processing using a digital signal processor DSP.

In the digital signal processor DSP, the timing extraction circuit 2 first enters as shown in FIG. From the received signal sampled here, the timing signal (2400bp
s) is extracted.

This timing signal is sent to the vector conversion circuit 3, where the scalar quantity is converted into a vector, and the absolute value of the timing signal is corrected to a unit length. It is input to the circuit 5.

In the polarity determination circuit 5, a polarity bit is generated by determining whether the phase of the vector is advanced or delayed, and the voltage controlled oscillator 6 is controlled by this polarity bit to control the phase of the sampling clock of the AD converter 1. The reception timing RT is set by the so-called ± polarity determination method PLL that controls the.

Here, the timing extraction circuit 2 and the vector conversion circuit 3
This is as described in the description of the conventional example in Japanese Patent Application No. 60-123772 relating to the invention of the present inventor.

That is, the timing extraction circuit 2 and the vector conversion circuit 3 are shown in FIG.

In FIG. 5, the real and imaginary parts A from the A / D converter 1
The X and AY components are input to the timing extraction circuit 2, and the timing extraction filters 21 and 22 extract the timing components in the band of the timing signal.

Timing extraction filters 21 and 22 have Nyquist frequency
Extract half the frequency component of the baud rate equal to 1/2 frequency.

The outputs of the filters 21 and 22 are squared by squaring circuits 23 and 24,
A frequency that is twice the half the Nyquist frequency is extracted as the timing signal.

The outputs of the squaring circuits 23 and 24 are added by an adder 25 to reduce the influence of carrier frequency offset.

This addition is because one component may become zero due to the frequency offset, and even in that case, the output is not made zero.

This output is output as the timing component TX by the bandpass filter 26 for Nyquist frequency extraction.

In the vector conversion circuit 3, the X timing component TX of the bandpass filter 26 is rotated by 90 ° in the 90 ° component detection unit 31 to Y.
Output timing component TY.

The rotation angle of the vector formed by the outputs TX and TY represents the amount of synchronization deviation.

That is, the real part of the vector formed by the outputs TX and TY is amplitude information, and the imaginary part is phase information.

Therefore, the value of TX or TY is used as the amount of synchronization deviation,
Here, the real part is discarded and only the output TY of the imaginary part, which is the phase information, is used.

[Problems to be solved by the invention]

However, in the above-mentioned conventional method, the voltage-controlled oscillator 6 is controlled depending on whether the phase of the vector is advanced or delayed, which is an on / off control type, and it is difficult to suppress the jitter.

It is an object of the present invention to provide an analog, ie, continuous timing synchronization system in which jitter is suppressed.

[Means for solving problems]

The above problem is a timing synchronization in which a received signal is sampled, A / D-converted, a timing signal is extracted from the sampling value, vectorized, and a voltage-controlled oscillator is controlled based on the vector to adjust the phase of a sampling clock. A modem adopting the method is provided with an APC circuit, and after adjusting the level diagram of the vector in the APC circuit, limiter processing is performed, and when the integrated value of the vector reaches a certain constant value, a voltage controlled oscillator Is advanced by one step and the integral value is reset to 0, and when the constant value is not reached, integration is continued without controlling the voltage controlled oscillator. It

[Action]

According to the present invention, the effect that the jitter is suppressed can be obtained because the phase control of the sampling pulse is performed in an analog manner, that is, continuously, instead of the on / off control method like the conventional method.

〔Example〕

FIG. 1 is a diagram showing an embodiment of a timing synchronization system according to the present invention.

In the figure, 7 is an APC circuit, and 8 is a voltage controlled oscillator circuit.

In the present invention, the received signal is A-
The D converter 1 samples and converts it into a digital amount, the timing extraction circuit 2 extracts a timing signal (2400 bps) from the received signal, the vector conversion circuit 3 converts the scalar amount into a vector, and the absolute value thereof is obtained. The unit length is set and the high-pass component is removed by the low-pass filter 4.

In the present invention, this unit length vector is input to the APC circuit 7. In the APC circuit 7, unlike the conventional method of controlling the polarity of ±, the phase of the sampling frequency is changed in an analog manner, that is, continuously according to the phase of the input vector.

FIG. 2 is an explanatory diagram of an embodiment of the APC circuit according to the present invention.

FIG. 3 is an operation explanatory diagram of the APC circuit according to the present invention.

In the figure, 10 and 11 are multipliers, 12, 13 and 15 are adders,
14 is a tap and 16 is a polarity determiner.

When the signal corresponding to the synchronization deviation enters the APC circuit 7, first of all, it is multiplied by the multiplier to bring it to the level required for the input of the subsequent limiter.
At 10, the parameter α is multiplied.

For example, when the synchronization tracking range is ± 200 ppm and the input level of the multiplier 11 is set to +2 level when the synchronization shift is +200 ppm, and it is set to -2 level when -200 ppm, the output signal of the low-pass filter 4 is set. Multiply the level by α and adjust to the set level.

Next, the multiplier 11 multiplies the parameter β, and the adder 12 further adds the parameter γ.

This arithmetic processing is to set +2 to -2 of the input level of the multiplier 11 to +2 to 0 by the input of the integrating circuit 13. In this case, parameter β = 0.25 and parameter γ =
It becomes 0.5.

This arithmetic processing defines the synchronization tracking range to ± 200 ppm, so it is called limiter processing.

Next, the output of the adder 12 is input to an integrating circuit including an adder 13 and a tap 14 which is a delay line storage element. In the adder 13, the output of the adder 12 and the output of the tap 14 are added and stored again in the tap 14, and this becomes the next addition input repeatedly.

Therefore, the integrated value of the output of the adder 13 gradually increases until it is reset as shown in FIG.

Next, the output of the adder 13 is input to the adder 15, and -1 is added in the adder 15. -1 is a threshold value.

By this process, the adder 15 outputs a positive or negative level. That is, if the output of the adder 13, that is, the integrated value is +1 or less, the output of the adder 15 has a negative value, and if it is +1 or more, it has a positive value.

The output of the adder 15 is input to the polarity determination circuit 16 and the polarity is determined.

The polarity determination circuit 16 outputs a control signal to the subsequent voltage controlled oscillator 8 when the output of the adder 15 has a positive value, and does not output a control signal when the output of the adder 15 has a negative value.

In this way, when the value of -1 is given to the adder 15, since the output is obtained from the polarity judgment circuit 16 only when the input signal is +1 or more, the threshold circuit is configured by the adder 15 and the polarity judgment circuit 16. There is.

Next, the output of the polarity determination circuit 16 is input to the voltage controlled oscillator 8 and the memory of the tap 14 is reset. FIG. 3 shows this state. When the synchronization deviation is integrated and reaches +1, it is reset to 0, at the same time a control signal for the voltage controlled oscillator 8 is output, and the next integration is started again. Of course, when a large signal such as +2 level is input to the input of the adder 13, the polarity determination circuit 16 outputs a control signal because only the signal exceeds the threshold value.

As described above, the input of the adder 13 is set so that a positive level of +2 to 0 is always input irrespective of the synchronization deviation direction, so that the integrated output of the adder 13 continues to increase. However, resetting this to 0 enables repeated polarity determination.

Next, since the voltage controlled oscillator 8 is set to oscillate in the phase of the delay state from the original synchronization state in the uncontrolled state, appropriate advance control is always required to maintain the synchronization state.

The advance of the oscillation phase is performed by advancing the frequency division ratio (n) of the frequency division circuit in the voltage controlled oscillator 8 by one step to the frequency division ratio (n-1).

Therefore, when the synchronization deviation is largely deviated in the delay direction, the integrated output of the adder 13 reaches +1 in a short period of time, and the polarity determination circuit 16 frequently outputs a control signal, and the frequency division ratio is output for each output. (N-1) and control the oscillation phase in the direction of synchronous advance.

On the contrary, when the synchronization shift occurs in the advance direction, the integrated output of the adder 13 gradually increases, so that the number of times the control signal is output from the polarity determination circuit 16 decreases and the oscillator is controlled in the original delay phase direction. .

In the present invention, by providing the integrating circuit, the leading jitter and the lagging jitter cancel each other out during the integration period, so that the oscillation phase of the voltage controlled oscillator 8 does not have timing fluctuation due to the jitter, and stable timing synchronization can be obtained. .

〔The invention's effect〕

As described in detail above, according to the present invention, the phase of the sampling pulse of the A / D converter can be continuously controlled without fluctuation due to jitter, so that it is possible to suppress jitter.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a timing synchronization system according to the present invention. FIG. 2 is an explanatory diagram of an embodiment of the APC circuit according to the present invention. FIG. 3 is an operation explanatory diagram of the APC circuit according to the present invention. FIG. 4 is a diagram showing an example of a conventional timing synchronization method. FIG. 5 is a diagram showing an example of the timing extraction circuit and the vector conversion circuit. In the figure, 1 is an A / D converter, 2 is a timing extraction circuit, 3 is a vector conversion circuit, 4 is a low pass filter, 5 is a polarity determination circuit, 6 is a voltage controlled oscillator, 7 is an APC circuit, and 8 is voltage controlled oscillation. Circuits, 10 and 11 are multipliers, 12, 13 and 15 are adders, 14 is a tap, and 16 is a polarity determiner.

Claims (1)

[Claims] 1. A received signal is sampled and A / D converted, a timing signal is extracted from the sampled value, vectorized, and a voltage controlled oscillator (8) is based on the vector.
APC circuit (7) in the modem that adopts the timing synchronization method that controls the phase of the sampling clock by controlling
After adjusting the level diagram of the vector in the APC circuit (7), limiter processing is performed, and the phase of the voltage controlled oscillator (8) is set to 1 when the integrated value of the vector reaches a certain constant value. A timing synchronizer characterized by resetting the integral value to 0 as the step advances and continuing the integration without controlling the voltage controlled oscillator (8) when the constant value is not reached.