JPH0683399B2 - Solid-state imaging device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a solid-state imaging device.

Configuration of Conventional Example and Problems Thereof The solid-state image pickup element has many advantages as compared with the image pickup tube, and thus is being actively developed.

In the early stages of solid-state image sensor development, the blooming phenomenon (a phenomenon in which excess charge generated by excessive light injection flows into other photoelectric conversion elements or transfer channels, causing loss of image information in that area) has become a problem. By some methods, it has become a state where it is not a big problem under normal use. However, it is still in an insufficient state especially when the amount of incident light is large.

A conventional blooming suppression method will be described below with reference to the drawings.

FIG. 1 is an overall configuration diagram of a solid-state image pickup of a system called an interline transfer system CCD.

In the figure, 1 is a photodiode (hereinafter abbreviated as PD) used as a photoelectric conversion element, and the signal charge accumulated in PD1 is transferred to a vertical transfer CCD2 and then horizontally transferred CCD3 for each row.
Are sequentially transferred to the charge detector 4 and output.
The blooming phenomenon is a phenomenon in which excess charge generated in PD1 that receives excessive incident light overflows from the PD1 to the adjacent vertical CCD2 or other PD1. As one method for suppressing such a blooming phenomenon, so-called P
There is a well structure. This will be described with reference to FIG. 2 which is a sectional view of the element taken along the line AA ′ of FIG. As shown in the figure, this device has a P well 6 formed on an n substrate 5.
And a photodiode portion 7, a vertical CCD channel 8 and an electrode 9 which also functions as an electrode for controlling the transfer of signal charge from the vertical CCD transfer electrode and the photodiode portion on the vertical CCD channel 8 are formed therein. Has become. The device of this structure is driven by a ternary pulse as described later, and when the highest voltage is applied, the signal charge is transferred from the photodiode part 7 to the vertical CCD channel 8. The potential distribution at this time is shown along the line BB 'in FIG.
Indicates. In the figure, 7-1 is a photodiode part, 8-1 is a vertical CC.
The electric potential of the D area is shown.

In this device, as described above, P is used to suppress blooming.
It has a well structure and its operation will be described with reference to FIG. 3b showing the potential distribution along the line CC ′ in FIG.
In the figure, 7-1 is a photodiode part, 6-1 is a P well, 5-1
Indicates each region of the n substrate 5. In the conventional drive, a DC voltage Vsub is applied to the n substrate 5-1 as shown in FIG.
The potential 7-9 of the photodiode section 7-1 immediately after the signal charge is transferred from the photodiode section 7-1 shown in FIG.
7-9 in FIG. 7B shows the potential of the photodiode part 7-1 at the same time and is the same. The transfer period of the signal charge from the photodiode section 7-1 ends, and the signal charge accumulation period starts. When the signal charge is accumulated and the potential of the photodiode section 7-1 is lowered, for example, to 7-8, the excess charge 15 passes through the P well region 6-1 and is discharged to the n substrate region 5-1. It

This is the conventional driving method. However, this driving method has the following drawbacks.

This will be explained with reference to FIG. 4 showing the potential along the B′-DC ′ line in FIG. 3a. This figure is a diagram in which FIG. 3a and FIG. 3b are combined, and the signal charge is being transferred from the photodiode section 7-1. The charges generated in the photodiode portion during this period are accumulated in the vertical CCD channel region 8-1, the transfer gate region 11-1, and the photodiode portion region 7-2 until the charge becomes 7-8. (Shaded area in the same figure) Actually, when the depth becomes shallower (lower), excess charge overflows to the adjacent region in the vertical CCD channel before it falls to the threshold potential 7-8 that the substrate 5-1 overflows. That is, there is a big drawback that the blooming suppressing capability is effectively ineffective during the transfer of the signal charges from the photodiode section.

SUMMARY OF THE INVENTION In view of the above drawbacks, the present invention provides a solid-state imaging device capable of exhibiting a blooming suppressing effect even during a signal charge transfer period from the photodiode section.

In order to achieve this object, a solid-state image pickup device of the present invention includes a plurality of photoelectric conversion elements, a unit for reading out signal charges accumulated in the photoelectric conversion elements, and an excess charge discharged from the photoelectric conversion elements. Excessive charge discharging means, and means for applying different potentials to the excess charge discharging means during the charge accumulation period to the photoelectric conversion element and the charge transfer period to the reading means, so as to facilitate discharge. By doing so, the blooming suppressing ability can be kept effective during the signal charge transfer period.

Description of Embodiments An embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 shows an example of drive pulses in the first embodiment of the present invention. Reference numeral 20 is a clock pulse applied to the vertical CCD transfer electrode and the electrode 9 which also functions as an electrode for controlling the transfer of the signal charge from the photodiode portion, and the period in which the voltage of 20-1 is applied is the transfer period. , 20-2, 20-3 are applied alternately during transfer in the vertical CCD. This is the same as the conventional one. The present invention is to apply a clock pulse 21 to the n substrate 5. 2 in the figure
The E periods of 0 and 21 are expanded to 22 and 23 of FIG. 6, respectively. As shown in the figure, a pulse (21-1) having an overlap with the period 20-1 of the clock pulse 22 is applied to the n substrate 9. That is, most of the signal charge accumulation period is applied with the low level voltage 21-2, which is the same as the conventional one, and the high level voltage 21-1 is applied during the transfer period, so that excess potential is discharged (threshold value). ) Charges shallower than 26 (lower) are discharged to the substrate 5-1 without being accumulated in the photodiode section 7-1.
Enable the blooming suppression effect. FIG. 4 shows a potential distribution for explaining the blooming suppressing effect at this time. At this time, during the transfer period, charges between the broken line indicated by reference numeral 26 and the potential 7-8 are discharged to the n substrate region 5-1 so that blooming is suppressed. At this time, the barrier with the adjacent area of the vertical CCD needs to be lower than the potential 26,
Actually, it can be easily realized.

The rising phase of the voltage pulse applied to the n-substrate 5-1 is 6th
The same phase as the beginning of the transfer period is desired, as shown at 22 and 23 in the figure. However, although the incident light intensity at which blooming does not occur is slightly lowered, it may be slightly delayed as indicated by 25.

However, as shown in 24, if a high level 24-1 is applied to the n-substrate 5-1 before the transfer period, the signal charges accumulated in the photodiode portion are discharged to the potential 26 in FIG. The dynamic range of the diode is reduced. The phase of the trailing edge of the pulse applied to the n-type substrate 5-1 may be the same as the end of the transfer period, but it is better to delay it slightly as shown at 23 for ease of synchronization.

In the present embodiment, the blooming suppressing means having the P well structure has been described, but the blooming suppressing means is not limited to this, and any means having a function of discharging excess charges from the photodiode portion may be used. For example, a so-called “overflow drain structure” having an overflow control gate and an overflow drain adjacent to the photodiode section can also obtain the same effect by applying a clock pulse to the overflow control gate. Also, the interline transfer CCD has been described as an example, but the same applies to other types of devices and one-dimensional solid-state imaging devices.

EFFECTS OF THE INVENTION As described above, according to the present invention, during the period during which the signal charges accumulated in the photoelectric conversion unit are transferred to the reading means, the excess charge discharge control is set to a state in which the discharge is facilitated, so that By eliminating the period during which the blooming suppression ability becomes ineffective, the blooming suppression ability can be improved.
Its practical effect is enormous.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an interline transfer type CCD, FIG. 2 is a sectional structure diagram of a main part, FIGS. 3A and 3B are diagrams showing a potential distribution in a conventional drive, and FIG. 4 is a conventional drive and the present invention. FIG. 5 is a comparison diagram of driving, FIG. 5 is a diagram showing one embodiment of the driving of the present invention, and FIG. 6 is a diagram showing clock pulses of one embodiment of the driving of the present invention and another embodiment. 1 ... Photodiode, 2 ... Vertical CCD, 3 ... Horizontal C
CD, 4 ... Charge detection unit, 5 ... N substrate, 6 ... P well, 7 ... Photodiode, 8 ... Vertical CCD channel, 9 ... Electrode, 10 ... Oxide film, 7-8, 7 -9 ... potential, 20,
21,22,23,24,25 ... Driving clock pulse.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hiroyuki Mizuno 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electronics Industrial Co., Ltd. (56) References JP-A-56-168475 (JP, A)

Claims (1)

[Claims] 1. A plurality of photoelectric conversion elements, reading means for reading out signal charges accumulated in the photoelectric conversion elements, excess charge discharging means for discharging excess charges from the photoelectric conversion elements, and the photoelectric conversion elements. A solid-state image pickup device, comprising: a control unit that applies different potentials to the excess charge discharging unit during a charge accumulation period to the read unit and a charge transfer period to the reading unit.