JPH0683415B2 - LCD drive circuit - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a liquid crystal drive circuit for driving a liquid crystal display panel having a dot matrix configuration.

[Prior Art and its Problems] Conventionally, a liquid crystal display panel is generally used for a display unit of a small portable television receiver, a small electronic computer, or the like. Therefore, the liquid crystal drive circuit for driving the liquid crystal display panel is conventionally constructed as shown in FIG. FIG. 5 shows one of the scan electrode driving circuits. In the figure, 1 is a shift register, which reads the common data In in synchronization with the timing φ _4H . Then, the data held in the shift register 1 is used as common data In1 in the level shifter 3 in the display drive circuit 2.
To the scan electrode drive circuit of the next stage. The common data In1 has an amplitude of the drive voltage GND-VDD (0-5V) of the display drive circuit 2, but the level shifter 3 causes the liquid crystal drive bias voltage V5 level (V0-V5:- It is a signal that oscillates between about 14V and 1/64 duty) and V0 level (usually GND). The output signal of the level shifter 3 controls the multiplexer circuit 7 including the inverter 4 and the gate circuits 5 and 6 to switch between the liquid crystal selection voltage Vs and the non-selection voltage Vn and output the scan electrode drive signal Out1.

FIG. 6 shows a detailed circuit configuration of the level shifter 3. This level shifter 3 is a P channel MO
S-transistors 11 and 12, N-channel MOS transistor 1
3 and 14 are used as the source electrodes of the MOS transistors 11 and 12.
The GND potential is applied, and the V5 voltage is applied to the source electrodes of the MOS transistors 13 and 14. Also, the MOS transistors 11, 1
The drain electrodes of the MOS transistor 12 and the drains of the MOS transistors 12 and 14 are collectively connected to each other.
The collective connection point of 1 and 13 is connected to the gate of the MOS transistor 14, and the collective connection point of MOS transistors 12 and 14 is M.
Connected to the gate of the OS transistor 13. Then, the common data In1 held in the shift register 1 is input to the gate of the MOS transistor 11 and the inverter
It is input to the gate of the MOS transistor 12 via 15.
The inverter 15 is supplied with VDD-GND as an operating power supply. Then, the signal generated at the drain electrodes of the MOS transistors 12 and 14 is taken out as the output signal of the level shifter 3.

In the above configuration, the shift register 1 always outputs a high level signal, and in this state, the MOS transistors 11 and 14 of the level shifter 3 are turned off and the MOS transistor 1 is turned off.
2, 13 are turned on, and the GND level signal is level shifter 3
Output signal. This turns on the gate circuit 5,
The non-selection voltage Vn is output via the gate circuit 5. Then, after that, when the common data In (low level) is read into the shift register 1, the output of the shift register 1 becomes low level, and the level shifter 3 turns on the MOS transistor 1
The transistors 2 and 13 are turned off, the MOS transistors 11 and 14 are turned on, and the V5 level signal becomes the output signal of the level shifter 3. As a result, the gate circuit 6 is turned on, the selection voltage Vs is output as the scan electrode drive signal Out1 via the gate circuit 6, and the scan electrodes of the liquid crystal display panel are driven.

As described above, the conventional scan electrode driving circuit has the multiplexer 7 in each stage, which causes a problem that the chip area of the LSI becomes large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and an object of the present invention is to provide a liquid crystal drive circuit that simplifies a liquid crystal scan electrode drive circuit and can reduce an LSI chip area.

According to the present invention, the multiplexer circuit can be eliminated by inverting the signal level of the common data according to the field switching signal and generating the scan electrode drive signal by the level shifter according to the common data. It is the one.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. First
The figure shows the first stage portion of the scan electrode drive circuit for the liquid crystal display panel. The shift register 23 reads the input signal In in synchronization with the timing signal φ _4H, and the output signal of the register 23 is input to the exclusive OR circuit (hereinafter abbreviated as EX OR circuit) 21 and
It is input to the shift register of the next stage (here omitted). It is assumed that the EX OR circuit 21 is provided ahead of the shift register of each stage. The EX OR circuit 21 receives the output signal of the shift register 23 and receives the field switching signal f.
Is input via the inverter 22. This EX OR circuit 21
The output of is input to the display drive circuit 24 as common data In1. The display driving circuit 24 is provided with a level shifter 25, the details of which will be described later.
Is output as the scan electrode drive signal Out1.

FIG. 2 shows the details of the level shifter 25.
This level shifter 25 is a P-channel MOS transistor 3
1, 32, N-channel MOS transistors 33, 34,
Va source is applied to the source electrodes of the MOS transistors 31 and 32, and Vb source is applied to the source electrodes of the MOS transistors 33 and 34. Further, the drain electrodes of the MOS transistors 31 and 33 and the drains of the MOS transistors 32 and 34 are collectively connected, and the collective connection point of the MOS transistors 31 and 33 is connected to the gate of the MOS transistor 34, and the MOS transistor The collective connection point of 32 and 34 is connected to the gate of the MOS transistor 33. Then, the output signal of the EX OR circuit 21, that is, the common data In1 is the MOS transistor.
It is input to the gate of 31 and via the inverter 35
It is input to the gate of the MOS transistor 32. VDD-GND is supplied to the inverter 35 as an operating power supply. Thus, the signal generated at the drain electrodes of the MOS transistors 32 and 34 is taken out as the scan electrode drive signal Out1.

Next, the level shifter power supply circuit 40 for generating the Va power supply and the Vb power supply will be described with reference to FIG. 41 ~
Reference numeral 44 is a gate circuit, and bias voltages V0, V1, V4, and V5 are input to these gate circuits 41 to 44, respectively. In this case, the bias voltages V0 and V5 are the liquid crystal selection voltage and the bias voltage.
V1 and V4 are liquid crystal non-selection voltages. Then, the field switching signal f is input to the NOR circuit 47 via the inverter 45 and the buffer 46, and the zero bias selection signal {circle over ()} is input to the NOR circuit 47 via the inverter 48 and the buffer 49. The output of the buffer 46 is input to the NOR circuit 51 via the inverter 50, and the output signal of the buffer 49 is directly input to the NOR circuit 51. Then, the output signal of the NOR circuit 47 is input to the gate terminal of the gate circuit 42, and is also input to the gate terminal of the gate circuit 41 via the inverter 52. Further, the output signal of the NOR circuit 51 is input to the gate terminal of the gate circuit 43, and is also input to the gate terminal of the gate circuit 44 via the inverter 53. The bias voltage V0 or V1 output from the gate circuits 41 and 42 is
It is supplied to the level shifter 25 as Va power supply, and the gate circuit 4
Bias voltage V4 or V5 output from 3, 44 is Vb
It is supplied to the level shifter 25 as a power source.

Next, the operation of the above embodiment will be described with reference to the timing chart of FIG. The timing chart in Fig. 4 is 1 /
It shows a signal waveform when a 64-duty drive is performed. The level shifter power supply circuit 40 shown in FIG.
As shown in the timing chart of FIG. 4, only when both the field switching signal f and the zero bias selection signal ▲ ▼ are at the high level, the output of the NOR circuit 47 becomes "1", the gate circuit 42 is turned on, and the bias voltage is changed. When V1 is output as the Va power source and either the field switching signal f or the zero bias selection signal ▲ ▼ becomes low level, the output of the NOR circuit 47 becomes "0" and the gate circuit 41 is turned on, and the bias voltage V0 Is output as Va power supply. Further, when the field switching signal f is low level, the zero bias selection signal ▲
Only when ▼ is high level, NOR circuit 51
Output signal of "1" turns on the gate circuit 43, the bias voltage V4 is output as Vb power supply, and in other cases, the output of the NOR circuit 51 turns "0" and the gate circuit 44 turns on. , Bias voltage V5 is output as Vb power supply.

Then, common data In (low level) is given to the first stage scan electrode driving circuit shown in FIG. 3 when the field switching signal f is switched to high level and the output of the inverter 22 is at low level. Then, a low level signal is read into the shift register 23 in synchronization with the timing signal φ _4H , and thereafter, this low level signal is sequentially transferred to the scan electrode drive circuit of the next stage. When the field switching signal f is at a high level, the output signal of the EX OR circuit, that is, the common data In1, In2, ... Becomes a low level signal. Then, the above shift register
The signal output from 23 is input to the level shifter 25 of the display driving circuit 24 through the EX OR circuit 21. In the level shifter 25, when the common data In1 is low level, the MOS transistors 31 and 34 in FIG. 2 are turned on, and the Vb power source is output as the scan electrode drive signal Out1 via the MOS transistor 34. At this time, in the level shifter power supply circuit 40 shown in FIG. 4, since the zero bias selection signal ▲ ▼ is at the high level, the gate circuits 42 and 44 are turned on, the bias voltage V1 is the Va power supply, and the bias voltage V5 is the Vb. It is output as a power supply. Therefore, the bias voltage V5 is
Is output as Out1 and the scan electrodes are driven for display. Thereafter, similarly, the corresponding scanning electrodes are sequentially driven for display by the respective driving circuits.

When the field switching signal f is switched to the low level in the next field, the output of the inverter 22 becomes the high level and is input to the EX OR circuit 21. When the output (low level) of the shift register 23 is given to the EX OR circuit 21 in this state, the output of the EX OR circuit 21 becomes high level. That is, when the field switching signal f is low level, the common data In1, In2, ... Are high level signals. When the common data In1 is at the high level, the level shifter 25 turns on the MOS transistors 32 and 33 shown in FIG.
Is output as the scan electrode drive signal Out1. At this time, in the level shifter power supply circuit 40 shown in FIG. 4, since the zero bias selection signal ▲ ▼ is at the high level, the gate circuits 41 and 43 are turned on, the bias voltage V0 is the Va power supply, and the bias voltage V4 is the Vb power supply. It is output as a power supply. Therefore, the bias voltage V0 is output from the level shifter 25 as Out1, and the scan electrodes are driven for display. Thereafter, similarly, the corresponding scanning electrodes are sequentially driven for display by the respective driving circuits.

As described above in detail, according to the present invention, the signal levels of the common data In1, In2, ... Are inverted according to the field switching signal f, and the common data In1, In2 ,. Since the scan electrode drive signal is generated by the level shifter, the multiplexer circuit which is conventionally required can be omitted. Therefore, the circuit configuration can be simplified and the chip area of the LSI can be considerably reduced.

[Brief description of drawings]

1 to 4 show an embodiment of the present invention.
FIG. 1 is a circuit configuration diagram showing a first stage portion of a scan electrode drive circuit, FIG. 2 is a circuit configuration diagram showing details of the level shifter in FIG. 1, FIG. 3 is a diagram showing a configuration of a level shifter power supply circuit, and FIG. Is a timing chart for explaining the operation, FIG. 5 is a diagram showing a configuration of one stage of a conventional scan electrode driving circuit, and FIG. 6 is a circuit configuration diagram showing details of the level shifter in FIG. 21 …… Exclusive OR circuit, 23 …… Shift register, 24 …… Display drive circuit, 25 …… Level shifter, 31〜
34 …… MOS transistor, 40 …… Level shifter power supply circuit, 41 to 44 …… Gate circuit.

Claims (1)

[Claims] 1. A liquid crystal drive circuit for driving a liquid crystal display panel having a plurality of scan electrodes, and means for inverting common data applied to the scan electrode drive circuit in response to a field switching signal, and the means for inverting the input. A shift register that sequentially shifts common data according to a timing signal, a level shifter that shifts the level of common data that is shifted by this shift register, and an operating voltage of this level shifter are selected according to the field switching signal and the zero bias selection signal. And a level shifter power supply circuit for supplying the liquid crystal, and driving the scan electrode by the output signal of the level shifter.