JPH0683467B2 - Luminance signal / color difference signal data separation device for dual-screen television receiver - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a luminance signal / color difference signal data separation device in a dual-screen display television receiver, and more particularly to a luminance signal using one A / D conversion system. And a device for time-division processing each data of the color difference signal and transferring these to each display memory.

(Prior Art) In recent years, along with the digitalization of television receivers, dual-screen display television receivers that simultaneously display a small image for monitoring (sub screen) in a standard image (main screen) have been implemented. The configuration of such a two-screen display television receiver,
In particular, the outline of the configuration of the data separation device for separating each data of the luminance signal and the color difference signal of the sub-screen and transferring them to each display memory will be described with reference to FIG.

The television signal received by the antenna not shown is
It is demultiplexed into a video signal for the main screen and a video signal for the sub screen (hereinafter referred to as the sub screen video signal). The sub-screen video signal is supplied to the sub-screen video signal processing circuit 50 and separated into a luminance signal (-Y) and color difference signals (RY) and (BY). The luminance signal (-Y) is given to the luminance signal A / D converter 51, appropriately sampled according to the size of the sub-screen, and then converted into digital data. The luminance signal data is once stored in the luminance signal buffer memory (line memory) 52 and then written in the luminance signal display memory 53.

On the other hand, the color difference signals (RY) and (BY) are time-divided and taken out by the multiplexer 54, and then converted into digital data by the A / D converter 55 for color difference signals in the same manner as the luminance signal described above. To be done. The color difference signal data is temporarily stored in the color difference signal buffer memory 56 and then written in the color difference signal display memory 57.

Then, the luminance signal data and the color difference signal data written in the respective display memories 53 and 57 are converted into analog signals by the D / A converters 58 to 60, and the luminance signal (-Y) and the color difference signal (R- Y) and (BY) are taken out. These sub-screen signals are supplied to a switching circuit (not shown), switched to a main-screen luminance signal / color difference signal at a predetermined timing, and supplied to the CRT display.

However, the above-described conventional apparatus has two methods for obtaining the luminance signal data and the color difference signal data from the sub-screen video signal.
Since the A / D conversion system is required, there is a problem that the circuit scale becomes large.

(Object of the Invention) The present invention has been made in view of the above circumstances, and has two screens capable of separating luminance signal data and color difference signal data from a sub-screen video signal by one A / D conversion system. An object of the present invention is to provide a data separation device for a luminance signal / color difference signal in a display television receiver.

(Structure of the Invention) In order to achieve such an object, the present invention has the following structure.

FIG. 1 is a block diagram showing the outline of the configuration of the device of the present invention.

A data separation device for a luminance signal / color difference signal in a two-screen display television receiver according to the present invention comprises: a sub-screen video signal processing circuit 1 for separating a sub-screen video signal into a luminance signal, a color difference signal and a synchronization signal, A multiplexer 2 for time-divisionally outputting a luminance signal and a color difference signal alternately and converting the time-divided luminance signal and color difference signal into digital luminance data and color difference signal data.
A / D converter 3, buffer memory 4 in which the luminance signal data and color difference signal data are written, luminance signal display memory 5 in which the luminance signal data transferred from the buffer memory is written, and transfer from the buffer memory The color difference signal display memory 6 in which the generated color difference signal data is written, an oscillator 7 that generates a clock pulse for writing data in the buffer memory and transferring data from the buffer memory, and divides the clock pulse in half. By providing a synchronizing signal from the frequency divider 8 and the sub-screen video signal processing circuit 8, sampling control of the video signal of the sub-screen is performed, and the clock pulse from the oscillator 7 or the frequency divider 8 is controlled. When given, it controls the timing of writing and transferring each data of the sub-screen. The control means 9 counts the clock pulses output from the frequency divider 7 in the case of writing data to the buffer memory 4, and the control means 9 counts the clock pulse output from the frequency divider 7 according to the count value. When the write address is designated and the data is transferred from the buffer memory 4, the clock pulse of the oscillator 7 is counted, and the minimum digit of the counted value is divided into the first half and the second half of the data transfer period. A luminance signal in a two-screen display television receiver characterized in that the read address of the buffer memory 4 is designated by fixing it to "0" or "1".
Data separation device for color difference signals.

Next, the operation of the invention described above will be described.

The multiplexer 2 alternately outputs the luminance signal and the color difference signal of the sub-screen video signal. These signals are sequentially converted into digital data by the A / D converter 3.

When writing the brightness signal data and the color difference signal data for one horizontal scan of the sub-screen converted into digital data into the buffer memory 4, the control means 9 counts the clock pulses of the frequency divider 8. Then, the address of the buffer memory 4 is designated by the counted value, and the luminance signal data and the color difference signal data are sequentially written to each designated address. Since the luminance signal data and the color difference signal data are alternately input to the buffer memory 4, the luminance signal data is stored at the even address (or the odd address) and the color difference signal is stored at the odd address (or the even address). The data is written respectively.

When the writing of the luminance signal data and the color difference signal data is completed, the data written in the buffer memory 4 is transferred in the first half and the second half of the next data transfer period. That is, in the first half of the data transfer period, the control means 9 sets the minimum digit of the count value of the clock pulse to "0" (or "1").
Fixed to, and in the latter half, the minimum digit is "1" (or,
Fixed to "0"). Then, the clock pulse which is not divided is counted by the control means 9, and the read address is designated by the counted value.

Therefore, in the first half of the data transfer period, even-numbered addresses (or odd-numbered addresses) of the buffer memory 4 are designated, and the luminance signal data (or color-difference signal data) is changed to the luminance signal display memory 5 (or the color-difference signal display memory 6). ) Is transferred to. In the latter half of the data transfer period, an odd numbered address (or even numbered address) of the buffer memory 4 is designated, and the color difference signal data (or luminance signal data) is transferred to the color difference signal display memory 6 (or the luminance signal display memory 5). ) Is transferred to.

(Example) Hereinafter, one example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an outline of a luminance signal / color difference signal data separation device in a dual-screen display television receiver according to an embodiment of the present invention.

The sub-screen video signal is given to the sub-screen video signal processing circuit 21, and the luminance signal (-Y), the color difference signal (RY), (B-
Y), a vertical synchronizing signal V, and a horizontal synchronizing signal H.
The luminance signal (-Y) and the color difference signals (RY) and (BY) are given to the multiplexer 22. Multiplexer 22
The time-series luminance and chrominance signals output from the
It is provided to the converter 23. The brightness signal data and color difference signal data obtained as digital data are stored in the buffer memory.
Written on 24. The buffer memory 24 is composed of a line memory having a data area at least twice the number of horizontal dots on the sub-screen. In the present embodiment, since the number of horizontal dots on the sub-screen is 128, a buffer memory 24 is used in which 256 data are written.

The luminance signal data read from the buffer memory 24 is
It is given to the luminance signal display memory 26 via the buffer 25. The luminance signal display memory 26 has a data area in which luminance signal data for one field of the sub screen can be stored. On the other hand, the color difference signal data read from the buffer memory 24 is given to the color difference signal display memory 28 via the buffer 27. The color difference signal display memory 28 has a data area capable of storing color difference signal data for one field of the sub screen.

On the other hand, the sync signal separated by the sub-screen video signal processing circuit 21
V and H are given to the counter unit 29. The counter unit 29 includes a ternary counter (not shown) that counts the horizontal synchronizing signal H,
The buffer memory 24 includes a first address counter (not shown) that counts control clock pulses, a second address counter that counts display clock pulses, and the like. The first and second address counters are configured to count up to a count value which is twice the number of horizontal dots on the sub-screen. The oscillator 30 is a buffer memory
Outputs 24 control clock pulses. This clock pulse is given to the first address counter of the counter unit 29 via the inverter G1, the AND gate G2 and the OR gate G3. Further, the clock pulse is frequency-divided by the frequency divider 31 into 1/2, and then applied to the first address counter via the AND gate G4 and the OR gate G3. The oscillator 32 generates a clock pulse for display,
This clock pulse is given to the second address counter.

The address bus of A _{0 to} A ₁₃ is output from the counter unit 29. The other ends of A ₀ and A ₁ are connected to the control terminal of the multiplexer 22. The other ends of the address buses A _{1 to} A ₇ are connected to the address terminals of the buffer memory 24. The A ₀ terminal of the counter unit 29 is connected to the A ₀ terminal of the buffer memory 24 via the AND gate G5 and the OR gate G6. The other ends of the address buses A _{1 to} A ₁₃ are connected to the display memories 26 and 28, respectively.

Further, the counter unit 29 outputs the sampling signal S based on the output of the ternary counter included therein and its inverted signal. The sampling signal S is given as a control signal for the AND gate G4 and also given as a drive control signal to the oscillator 30 via the OR gate G7. On the other hand, the inverted signal is given to the data transfer timing signal generation circuit 33 including D flip-flops FF1 to FF4.

In the data transfer timing signal generation circuit 33, the D input terminal of the D flip-flop FF1 and the preset terminals (active LOW) of the D flip-flops FF1 to FF4 are connected to the power supply line Vcc. The output 1Q of the D flip-flop FF1 is given as the D input of the D flip-flop FF2. The output 2Q of the D flip-flop FF2 is given as the D input of the D flip-flop FF3 and is also given as a drive control signal of the oscillator 30 via the OR gate G7. Also, the inverted output of D flip-flop FF2
▼ is given to the AND gate G5 and the transfer control circuit 34 as respective control signals. The output 3Q of the D flip-flop FF3 is given as the D input of the D flip-flop FF4, and also the buffer memory via the OR gate G6.
It is given to the A ₀ terminal of 24, and further given to the transfer control circuit 34 as a control signal. The transfer control circuit 34 transfers the luminance signal data and the color difference signal data read from the buffer memory 24 to predetermined display memories 26 and 27 based on the two control signals.

On the other hand, the clock pulse input terminals CK of the D flip-flops FF3 and FF4 are supplied from the counter unit 29 with the dot count signal 12
8C is given. The dot count signal 128C is output every time the first address counter included in the counter unit 29 counts 128 clock pulses. The inverted output ▲ ▼ of the D flip-flop FF4 is the D flip-flop F
It is given to the clear terminals (active LOW) of F1 to FF3.
The clock pulse input terminal CK of the D flip-flop FF2 and the clear terminal of the D flip-flop FF4 are
Sub-screen display timing signal corresponding to the sub-screen display position ▲
▼ is given. This sub-screen display timing signal ▲ ▼ is sent from the sub-screen display timing generation circuit 40 shown in FIG.
Is output as an inverted signal of.

The sub-screen display timing signal generation circuit 40, when displaying the sub-screen on the left side of the main screen, the one-shot multivibrator M1 for setting the position, and when displaying the sub-screen on the right side of the main screen, Includes a one-shot multivibrator M2 for setting its position. Input signals 1A and 2A of these one-shot multi-vibrators M1 and M2 have inverted signals of the horizontal flyback pulse MH of the main screen.
▼ is given. One-shot multivibrator M
The outputs of 1 and M2 are inverters G8, G9, AND gates G10, G1.
1, one of the outputs is given to the clock pulse input terminal CK of the D flip-flop FF5 via the selection circuit 41 constituted by the OR gate G12. Further, the selection circuit 41 is controlled by a display position designation signal PS that designates a sub-screen display position. The output 5Q of the D flip-flop FF5 is given to the oscillator 32 for generating the display clock. The display clock pulse output from the oscillator 32 is given to the second counter 29 a included in the counter unit 29.
The second counter 29a addresses the display memories 26 and 28, and outputs a dot count signal ▲ ▼ 'when counting 128 clock pulses. This dot count signal ▲ ▼ 'is the inverter G13
To the clear terminal CL of the D flip-flop FF5. Then, the inverted output of the D flip-flop FF5
▼ is given to the data transfer timing signal generation circuit 33 as a sub-screen display timing signal ▲ ▼.

In the present embodiment, the counter section 29, the data transfer timing signal generating circuit 33, the sub-screen display timing signal generating circuit 40, and the gates G1 to G7 correspond to the control means 9 described in FIG.

Next, the operation of the embodiment having the above-described structure will be described based on the operation waveform chart shown in FIG.

When the horizontal synchronizing signal H is applied from the sub-screen video signal processing circuit 21 to the ternary counter of the counter unit 29, the counter unit 29 outputs three horizontal scanning lines as shown in FIG. 4 (a). A sampling signal S for extracting one horizontal scanning line and an inversion signal shown in FIG. The "H" level period of the sampling signal corresponds to the sampling period Ts. During this sampling period Ts, the oscillator 30 is driven and the AND gate G4 becomes conductive. On the other hand, the AND gate G2 is in the cutoff state until the sampling period Ts ends. Therefore, during the sampling period, the oscillator 30
The clock pulse of is input to the counter unit 29. This clock pulse is counted by the first address counter of the counter unit 29. When the first address counter counts up to 256, the sampling signal S and its inverted signal are inverted.

On the other hand, during the period in which the sampling signal S is being output (sampling period Ts), the output of the lower 2 bits of the first address counter serves as a switching control signal.
It is given to the multiplexer 22 via A ₀ and A ₁ . Based on the switching control signal, the multiplexer 22 time-divisions the luminance signal (-Y) input and the color difference signals (RY), (BY) input, and outputs each signal from (RY) → ( -Y) →
Output in the order of (B−Y) → (−Y) → ... Here, the number of time-divided color difference signals (RY) and (BY) is half that of the luminance signal (-Y).
Since the bandwidth of the color difference signal is narrower than the bandwidth of the luminance signal, even if the number of each of the color difference signals (RY) and (BY) is smaller than that of the luminance signal (-Y), the image quality of the sub-screen is reduced. Does not deteriorate.

The frequency-divided luminance signal and color difference signal are output by the frequency divider 31.
It is converted into digital data by the A / D converter 23 in accordance with the timing of the clock pulse divided in half. Therefore, in the sampling period Ts, 128 pieces of luminance signal data and chrominance signal data are obtained, and these pieces of data are given to the buffer memory 24 via the data buses D _{0 to} D ₅ in the order of the above-mentioned signal data.

On the other hand, except during the data transfer period of the buffer memory 24 (including the sampling period), the inverted output ▲ ▼ of the D flip-flop FF2 is at the “H” level. Therefore, the AND gate G5 to which the inverted output) ▼ is given is open. As a result, the count value of the first address counter of the counter unit 29 is given to the address terminals A _{0 to} A ₇ of the buffer memory 24 via the AND gate G5, the OR gate G6 and the address buses A _{1 to} A ₇ .

In this way, the luminance signal data and the color difference signal data are sequentially written in the data area designated by the count value of the first address counter. Here, since the luminance signal data and the color difference signal data are transmitted alternately, for example, the color difference signal data is stored in an even address of the buffer memory 24.
The luminance signal data is written in each odd address.

Next, the sub-screen display timing signal generation circuit shown in FIG.
The operation of 40 will be described with reference to FIG.

Now, it is assumed that the sub-screen display position designation signal PS is set to "1" in order to display the sub-screen on the left side of the main screen. Then, the AND gate G10 of the selection circuit 41 is in the cut-off state because its one input becomes the "L" level.
On the other hand, the AND gate G11 is open because its one input becomes the "H" level. In this case, FIG. 5 (a)
When the main screen horizontal flyback pulse ▲ ▼ shown in is input to the one-shot multivibrator M1, the capacitor C1, the resistor R1, and the resistor C1, which are set appropriately according to the sub-screen position
The inverted output of the one-shot multivibrator M1 rises with a delay based on the time constant of R2 (see FIG. 7B). This inverted output is D through the selection circuit 41.
When applied to the flip-flop FF5, the output 5Q (DISP) of the D flip-flop FF5 rises (see (d) in the same figure).

When the output 5Q of the D flip-flop FF5 becomes the “H” level, the oscillator 32 is driven and the display clock pulse becomes the second level.
It is given to the counter 29a. When 128 clock pulses are counted, the second counter 29a outputs a dot count signal ▲ ▼ '((c) in the figure).
reference). The dot count signal (5) 'is applied to the clear terminal of the D flip-flop FF5 via the inverter G13, so that the output 5Q is cleared (see (d) in the figure). Therefore, while the output 5Q is at the "H" level, the sub screen is displayed on the left side of the main screen (see (h) in the figure). In the figure (h), MP
Indicates the main screen, SPL indicates the sub-screen displayed on the left, and SPR indicates the sub-screen displayed on the right. Then, the inverted output ▲ ▼ of the D flip-flop FF5 is given to the data transfer timing signal generation circuit 33 as the sub-screen display timing signal ▲ ▼.

On the other hand, when the sub-screen display position designation signal PS is set to "0" to display the sub-screen on the right side of the main screen, the inverted output of the one-shot multivibrator M2 (see (e) in the figure) It is given to the D flip-flop FF5.
As a result, the output 5Q of the D flip-flop FF5 becomes "H".
At the level, the display clock pulses are counted in the same manner as described above, and the dot count signal ▲ ▼ 'is output (see (f) in the figure). As a result, the sub-screen display timing signal DISP corresponding to the right display position is output from the output 5Q of the D flip-flop FF5 (see (g) and (h) in the same figure).

Returning to FIG. 2, when the first address counter of the counter unit 29 counts up and the writing of data is completed, the sampling signal S is not output and the oscillation of the oscillator 30 is stopped. Further, as shown in FIG. 4 (d), the output 1Q of the D flip-flop FF1 becomes "H" level by being triggered by the rising edge of the inverted signal. D flip-flop which is given this output 1Q
FF2 is the sub-screen display pulse ▲ shown in FIG.
Trigger is applied at the rising edge of ▼, and the pressure is 1Q.
Is latched, and its output 2Q becomes "H" level. However, the sub-screen display timing signal ▲ shown in FIG.
▼ shows the time axis of the inverted signal of the sub-screen display timing signal DISP shown in FIG. 5 in a reduced scale.

The output 2Q is given to the oscillator 30 as a data transfer control signal to start oscillation and open the AND gate G2. As a result, the clock pulse output from the oscillator 30 is supplied to the counter unit 29 via the inverter G1, the AND gate G2, and the OR gate G3 without being divided.

On the other hand, when the data is transferred to the display memories 26 and 27, the inverted output ▲ ▼ of the D flip-flop FF2 is at the “L” level, so the AND gate G5 is cut off. Also, after the output 2Q rises, the D flip-flop FF
Until the first dot count signal 128C is input to 3 (the first half of the data transfer period), the output 3Q of the D flip-flop FF3 is at the "L" level. Therefore, in the first half of the data transfer, the address terminal A ₀ of the buffer memory 24 is fixed at "0". As a result, in the first half of the data transfer period, the data written in the address of the even address of the buffer memory 24, that is, the color difference signal data is read and placed on the data buses D _{0 to} D ₅ . Since the address terminal A ₀ is fixed to “0”, the first address counter addresses one clock pulse for every two clock pulses. Therefore, in order to make the read speed the same as the write speed, clock pulses that are not divided during data transfer are counted.

The transfer control circuit 34 detects that the color difference signal data has been read by being provided with the inverted output (1) of the D flip-flop FF2 and the output 3Q of the D flip-flop FF3. As a result, the buffer memory 27 and the color difference signal display memory 28 are set to the written state. In this way, the color difference signal data read from the buffer memory 24 is transferred to the color difference signal display memory via the buffer memory 27.
The data is transferred to 28 and written to the address designated by the second address counter of the counter unit 29.

By the way, the first address counter of the counter unit 29 is 12
Every time eight clock pulses are counted, the dot count signal 128C shown in FIG. 4 (f) is output. The first dot count signal is given to the clock pulse input terminal CK of the D flip-flop FF3, so that the D flip-flop FF3 outputs the output 2Q given from the D flip-flop FF2.
Is latched, and its output 3Q becomes "H" level (4th
(See FIG. (G)). When the subsequent dot count signal is output, the D flip-flop FF4 latches the "H" level output 3Q, and its inverted output ▲ ▼ becomes the "L" level. When the inverted output ▲ ▼ rises, D
Flip-flops FF1 to FF3 are cleared, each output 1Q, 2Q,
3Q is "L" as shown in Fig. 4 (d), (e), (g)
Become a level.

That is, in the second half of the data transfer period (from the output of the first dot count signal 128C to the output of the next dot count signal 128C), the D flip-flop FF
Output 3Q of 3 becomes "H" level, and this is OR gate G6
Is given to the A ₀ terminal of the buffer memory 24 via. Therefore, in the latter half of the data transfer period, the address terminal A ₀ of the buffer memory 24 is fixed to "1", and the luminance signal data written in the odd address is read during this period.

Then, the transfer control circuit 34 outputs the inverted output ▲ ▼ of the D flip-flop FF2 and the output 3Q of the D flip-flop FF3.
The fact that the luminance signal data has been read out is detected by giving and. As a result, the buffer memory 25 and the luminance signal display memory 26 are set to the written state.
In this way, the luminance signal data read from the buffer memory 24 is transferred to the luminance signal display memory 26 via the buffer memory 25.

As described above, when the next sub-screen display is started (the rising of the sub-screen display pulse ▲ ▼ by the data transfer being performed almost at the same time as the rising of the sub-screen display pulse ▲ ▼ (the end of the sub-screen display). ), Each data of the buffer memory 24 is a luminance signal display memory.
26 and the color difference signal display memory 28.

Then, when the D flip-flop FF4 is cleared by being triggered by the falling edge of the sub-screen display pulse ▲ ▼, its inverted output ▲ ▼ returns to the “H” level, and the D flip-flops FF1 to FF3 are cleared. Is released. After that, similarly, one scanning line is extracted from the three scanning lines, the luminance signal and the color difference signal of the sub-screen video signal are time-division processed, converted into digital data, and written in the buffer memory 24. . Then, almost simultaneously with the end of the sub-screen display, the video signal data of the sub-screen is transferred from the buffer memory 24 to the display memories 26 and 28.

The luminance signal data and the color difference signal data written in the display memories 26 and 28 are read and D / A converted during the period when the sub-screen display timing signal DISP is output, and then the main screen / sub-screen not shown. Is applied to the switching circuit of. Then, the sub-screen is displayed at a predetermined position on the main screen by switching the switching circuit according to the sub-screen display timing.

In the above embodiment, the video signal of the sub-screen is sampled for every three horizontal scanning lines, and the number of horizontal display dots on the sub-screen is 128. Needless to say, is not limited to these cases.

(Effects of the Invention) As is apparent from the above description, the data separation device for the luminance signal / color difference signal in the dual-screen display television receiver according to the present invention is obtained by performing time-division processing on the sub-screen video signal. When writing the luminance signal data and the color difference signal data to the buffer memory, the divided clock pulses are counted, the buffer memory is addressed by the count value, and the luminance signal data and the color difference signal data are even-numbered. Or write in each odd address. After the data writing to the buffer memory is completed, the minimum digit of the counter is fixed to "0" or "1" in the first half and the second half of the data transfer period, and the clock pulse is not divided. The read signal is designated by the counted value, the luminance signal data and the color difference signal data are individually read from the buffer memory and transferred to each display memory.

Therefore, according to the present invention, the luminance signal and the color difference signal of the sub-screen video signal can be separated and transferred to each display memory without using two A / D conversion systems as in the conventional device. Therefore, the circuit scale can be reduced as compared with the conventional device.

[Brief description of drawings]

FIG. 1 is a block diagram showing the outline of the configuration of a luminance signal / color difference signal data separation device in a dual-screen display television receiver according to the present invention, and FIG. 2 is an outline of the configuration of an embodiment of the present invention. The block diagram shown in FIG. 3 is a circuit diagram of the sub-screen display timing signal generating circuit in the embodiment, and FIG.
FIG. 5 is an operation waveform diagram of the above embodiment, FIG. 5 is an operation waveform diagram of the sub-screen display timing signal generating circuit shown in FIG. 3, and FIG.
FIG. 1 is a block diagram showing the outline of the configuration of a conventional example. 21 …… Sub screen video signal processing circuit, 22 …… Multiplexer, 23 …… A / D converter, 24 …… Buffer memory, 26 ……
Luminance signal display memory, 28 ... Color difference signal display memory, 29 ...
… Counter unit, 30… Oscillator for buffer memory control,
32 ... Oscillator for controlling display memory, 33 ... Data transfer timing signal generating circuit, 40 ... Sub screen display timing signal generating circuit, FF1 to FF5 ... D flip-flop, M1, M2
...... One-shot multi-vibrator.

Claims (1)

[Claims] 1. A sub-screen video signal processing circuit for separating a sub-screen video signal into a luminance signal, a color difference signal and a synchronization signal, a multiplexer for time-divisionally outputting the luminance signal and the color difference signal alternately, Converting the time-divided luminance signal and color difference signal into luminance signal data and color difference signal data which are digital data
A / D converter, a buffer memory in which the luminance signal data and the color difference signal data are written, a luminance signal display memory in which the luminance signal data transferred from the buffer memory is written, and a color difference transferred from the buffer memory A color difference signal display memory in which signal data is written, an oscillator that generates a clock pulse related to data writing to the buffer memory and data transfer from the buffer memory, and a frequency divider that divides the clock pulse into 1/2. The sub-picture video signal processing circuit provides a synchronization signal to control sampling of the sub-picture video signal, and a clock pulse from the oscillator or the frequency divider to provide the sub-picture. Control means for controlling the timing of writing and transferring each data, The control means counts the clock pulses output from the frequency divider when writing data to the buffer memory, specifies the write address of the data in the buffer memory by the count value, and In the case of data transfer from the memory, the clock pulse of the oscillator is counted, and the minimum digit of the count value is fixed to "0" or "1" in the first half and the second half of the data transfer period. A data separation device for a luminance signal / color difference signal in a dual-screen display television receiver, characterized in that a read address of a buffer memory is designated.