JPH0683513B2 - Time division exchange - Google Patents

Description

The present invention relates to a time-division exchange with time switch control.

[Conventional technology]

Conventionally, this type of time-division exchange has, for example, as shown in FIG. 3, a line control unit 11, 12, ..., 1n that time-division-multiplexes information from a local line (not shown) and outputs it as a serial signal. , And the signal is input via the upstream call highways 41, 42, ... 4n, and the time division multiplexing degree is further increased and serial / parallel conversion is performed. Information from the multiplexing unit 20 is transmitted to the upstream super highway. And a control circuit 30 for inputting control information for time slot conversion from the line control units 11, 12, ..., 1n via the control bus 70. A control memory 23 that temporarily holds the control information received by the control circuit 30 as conversion information for time slot conversion via the control line 71; and the information from the call memory 21 that has been time slot converted according to the exchange information. Via Super Highway 61 Input, parallel-to-serial conversion, demultiplexing, and demultiplexing, and the line control units 11, 12, ..., 1n transmit information via the downlink highways 51, 52 ,.
, And 1n for transmitting information to the line control units 11, 12, ..., 1n. Uplink call highways 41, 42, ..., 4n and downlink call highway 5 described above
Signals with 1,52, ..., 5n are serial and each has one channel 64
kb / s information is multiplexed on 128 channels in 125 μs units 8,19
It has a speed of 2M b / s, and the upstream super highway 60 and the downstream super highway 61 are 8-bit parallel configuration with 1024 channels multiplexed, and the time slot α on the upstream super highway 60 is on the downstream super highway 61. In order to convert into the time slot β of, the data α may be set to the address β of the control memory 23. The time slot j on the upstream call highway 4i (i = 1 to n) is
It is assumed that the time slot αij on the upstream super highway 60 is uniquely output, and similarly, the time slot βpq on the downstream super highway 61 is uniquely output to the time slot q on the downstream communication highway 5P.

Therefore, the control memory 23 has a capacity of 1024 words × 10 bits.

The line control is performed by control information transmitted and received between the control circuit 30 and the line control units 10 to 1n via the control bus 70.

[Problems to be solved by the invention]

In the conventional time switch control type time division switch, the control memory is centrally installed. Therefore, when the time division switch is configured by distributed control, that part remains as the central control, which lacks reliability. In particular, the failure of the control memory has the drawback of causing a total outage.

[Means for Solving Problems] A time division switch according to the present invention includes a first multiplexing unit that multiplexes call information on an upstream call highway, performs serial / parallel exchange, and outputs the upstream superhighway. The control information having a synchronous relationship with the time slot of the call information corresponding to the call information to be multiplexed by the multiplexer is multiplexed, and the second multiplexer for serial / parallel exchange is output to the upstream super highway. A call memory for temporarily holding the call information for time slot exchange and outputting it to the downlink super highway, and a control unit for time-slot converting the call information in the call memory based on the control information of the second multiplexing unit and outputting it. And the demultiplexer for the first demultiplexing unit, which parallel-serially exchanges the call information output to the downlink super highway, demultiplexes, and outputs to the downlink call highway. And a second demultiplexing unit for demultiplexing and outputting the multiplexed call information from the downlink highway and the call information from the second demultiplexing unit is sent to the line and transmitted from the line. A line interface that outputs call information and control information, a third multiplexing unit that time-division-multiplexes the call information of the line interface and sends it to the upstream call highway, and call information of the line that is sent to the upstream call highway. Control memory that outputs the control information of the line to the control information highway in synchronization with the time slot of the line, and when the line state change is received from the line corresponding part via the internal bus, the necessary information is controlled via the control bus. When it is necessary to control the communication path for a line that has been exchanged with a circuit and the line status has changed, the content of the control memory must be rewritten to change the correspondence of time slot conversion in the communication memory. And a line control unit including a line control circuit.

By disposing the control memory in each line control unit in this way, the failure of one control memory does not stop the whole function, and the time switch unit does not need the interface of the control circuit. Therefore, it is necessary to operate only by the information from the line control unit.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a time division exchange of the present invention.

The outputs of the line control units 11 to 1n are connected to the first multiplexing unit 20 by the upstream call highways 41 to 4n, and the first multiplexing unit 20
The output of the upward super highway 60 call memory
It is connected to 21 and the output of call memory 21 is a super highway
61 is connected to the first demultiplexing unit 22, and the output of the first demultiplexing unit 22 is connected to the line control units 11 to 1n by the downlink communication highways 51 to 5n. In addition, the line control unit 11
The outputs of 1n to 1n are connected to the second multiplexer 24 by the control information highways 81 to 8n, the second multiplexer 24 is connected to the controller 25, and the controller 25 is connected to the call memory 21. In addition, the line control units 11 to 1n use the control bus 70 to control the circuit 30.
Connected to.

FIG. 2 is a block diagram of the line controller 1i (i = 1 to n).

The line corresponding unit 111-11m is connected to the third multiplexing unit 103,
The output of the third multiplexing unit 103 is sent to the upstream call highway 4i. The output of the first demultiplexing unit 22 is connected to the second demultiplexing unit 104 via the downlink call highway 5i,
The second demultiplexing unit 104 is connected to the line corresponding units 111 to 1m. Line corresponding part 111-11m, control memory 101, line control circuit
100 is connected by the internal bus 102, and the control memory 101 is connected by the control information highway 8i to the second multiplexer 24,
The line control circuit 100 is connected to the control circuit 30 by a control bus 70.

Next, the operation of this embodiment will be described.

First, the flow of call information will be described. The call information is transmitted from the line corresponding units 111 to 11m to the third multiplexing unit 103 as in the conventional configuration.
And is multiplexed by the third multiplexer 103, output to the upstream call highway 4i, further multiplexed and serial-parallel converted by the first multiplexer 20, output to the upstream super highway 60, and the call memory 21 is input, is converted into a time slot, and is then output to the downlink super highway 61.
Demultiplexing and parallel-serial conversion in the demultiplexing unit 22 of
The outgoing call highways 51 to 5n are output, and the outgoing call highway 5i is input to the second demultiplexing unit 104,
Further, the signals are demultiplexed and output to the line corresponding units 111 to 11m.

On the other hand, when a line state change is detected by the line corresponding units 111 to 11m, it is transmitted to the line control circuit 100 via the internal bus 102, and necessary information is transmitted and received via the control bus 70 and the control circuit 30. When it is necessary to control the communication path for the line, the correspondence of the time slot conversion in the communication memory 21 is changed by rewriting the corresponding address in the control memory 101. The control memory 101 has the number of words corresponding to the number of lines accommodated in the line control unit 1i, and its information is synchronized with the time slot on the upstream call highway 4i and corresponds to the line of the time slot. Is output to the control information highway 8i. Since the control information highway 8i is multiplexed by the second multiplexing unit 24 like the upstream call highway 4i, its synchronous relationship is maintained, and the control unit 25 sequentially reads data from the call memory 21 according to the control information. , Output to the down super highway 61. With the control memory 101 thus distributed and installed, the call memory 2
1 can be controlled as in the case of the conventional central installation.
It is obvious that the control memory control line 71 shown in FIG. 3 is unnecessary.

〔The invention's effect〕

As described above, according to the present invention, by distributing the control memory in each line control unit, there is an effect that the decentralization can be further promoted and a highly reliable communication path can be configured. There is no need for an interface with a circuit, and it is sufficient to operate only by information from the line control unit, which has the effect of increasing the flexibility of the configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the time division exchange of the present invention, FIG. 2 is an internal block diagram of the line control unit 1i in FIG. 1, and FIG. 3 is a block diagram of a conventional example. 11 to 1n ... Line control unit, 20 ... First multiplexing unit, 21 ... Call memory, 22 ... First demultiplexing unit, 24 ... Second multiplexing unit, 25 ... Control Part, 30 ... control circuit, 41-4n ... upstream call highway, 51-5n ... downstream call highway, 60 ... upstream super highway, 61 ... downstream super highway, 70 ... control bus, 81-8n ... ... control information highway, 111 to 11m ... line interface, 100 ... line control circuit, 101 ... control memory, 102 ... internal bus, 103 ... third multiplexing unit, 104 ... second multiplexing Separation department.

Claims (1)

[Claims] 1. A first multiplexing unit for multiplexing call information on an upstream call highway, performing serial / parallel exchange, and outputting to an upstream superhighway, and corresponding to the call information multiplexed by the first multiplexer. Then, the control information having a synchronous relationship with the time slot of the call information is multiplexed, and the second multiplexer for serial / parallel exchange and the call information output to the upstream super highway are temporarily held for time slot exchange, The call memory output to the downlink super highway, the control unit for time-slot converting the call information in the call memory based on the control information of the second multiplexing unit, and outputting the call information output to the downlink super highway. A first demultiplexing unit that serially exchanges, demultiplexes, and outputs to a downlink highway, a control circuit, and a multiplexed communication from the downlink highway. A second demultiplexing unit for demultiplexing and outputting information, and a line corresponding unit for transmitting the call information from the second demultiplexing unit to the line and outputting the call information and control information from the line And a third multiplexing unit that time-division-multiplexes the call information of the line corresponding unit and sends it to the up-call highway, and the time slot of the call information of the line sent to the up-call highway in synchronization with the line. A control memory that outputs control information to the control information highway, and when the line status changes from the line interface via the internal bus, the necessary information is exchanged with the control circuit via the control bus. When there is a line control unit that includes a line control circuit that rewrites the contents of the control memory to change the correspondence of time slot conversion in the call memory when call line control is required Split exchange.