JPH0685123B2 - Programmable controller - Google Patents

Description

TECHNICAL FIELD The present invention relates to a programmable controller, and more particularly to a programmable controller suitable for controlling a plurality of control targets that require the same control.

[Conventional technology]

A conventional programmable controller is shown in FIG. The programmable controller is a logical operation unit 1 for reading and processing a program, a program memory 2 for storing the program, a data memory 3 for storing various data, and an input / output for connecting to the controlled objects 9 to 13. Device 4
-8.

Inside the logic operation unit 1, an oscillation circuit 20, a control circuit 21,
Multiplexer 23, 37, save register 23, program counter 24, a plurality of address modification registers (also called index registers) 36, switching switches 28, 29, arithmetic circuit 30, accumulator 31, address register 32, instruction register 33 Further, the instruction register 33 has an instruction code part (OP), a register designating part (IX), and an address part (ADDR).
It consists of.

In such a programmable controller, the address from the program memory 2 is normally executed by modifying the address. Address modification is the execution address (the logical operation unit (CPU) for the instruction) based on the contents of the address part in the instruction word.
Determine the address at which data is actually exchanged and access the execution address according to the contents of the instruction code part to perform processing, the execution address is changed to the contents of the address part and the register (index) in the logical operation part. TX Register)
It means to calculate by hardware with the contents of.

Such address modification is an essential technique for reducing the capacity of programs, not limited to programmable controllers. For example, when moving multiple data in one area to another area, if address modification is not used, Since all the move source addresses and move destination addresses must be specified one by one in the program, the program capacity increases, and the program capacity changes depending on the number of move data words.

However, if the address modification is used, the move source address is stored in the two destination registers, and the contents of those registers are incremented by one after one move process. All the data can be moved by repeating this process a required number of times. Therefore, in this case, only three programs, one movement processing program, register increment program, and program that ends at the required number of times,
The program capacity can be reduced. Moreover, the capacity of the program does not change depending on the number of moved data words.

The programmable controller shown in FIG. 2 has a plurality of index registers that can be used for address modification, and is capable of both word processing and bit processing. It was necessary to specify the address modification register in the program.

Note that Japanese Patent Application Laid-Open No. 52-122786 and the like can be cited as examples of the address modification register in the programmable controller.

[Problems to be solved by the invention]

In the above-mentioned prior art, in the processing including the word processing and the bit processing, and the processing including both the word processing and the bit processing, the creator of the processing program requires the processing program in each of the above-mentioned processing that requires address modification. When creating, it was necessary to always be aware of which address modification register was used to modify the address. In particular, in the processing including both word processing and bit processing, when the address modification amount in each of the above-mentioned processings is different, the address modification by the same register cannot be performed, so that it is difficult to create the processing program.

An object of the present invention is that the creator does not need to be aware of the address modification register in word processing or bit processing in creating a processing program, and includes both word processing and bit processing that require address modification. It is to provide a programmable controller that facilitates the creation of a processing program.

[Means for solving problems]

The above object is to provide two registers, an address modification register dedicated to word processing and an address modification register dedicated to bit processing, which are independent of each other, and an address modification register to each instruction code part of the word processing instruction and the bit processing instruction. A bit indicating whether to use it and a multiplexer for selecting whether to use the address modification register for word processing, the address modification register for bit processing, or neither of the above registers by the bit are newly added. By providing it, it becomes possible to automatically select the register for address modification.

[Action]

According to the present invention, before the word processing instruction or bit processing instruction requiring the address modification is executed in the newly provided word processing address modification register and bit processing address modification register, the address modification in each of the above processes is executed. Store the quantity. The multiplexer fetches an instruction from the program memory and uses the word processing address modification register from the bit in the instruction code section of the instruction indicating whether to use the address modification register.
When it is determined by selecting whether to use the bit processing address modification register or not to use both the above registers, the address part of the instruction fetched from the program memory and the selected address modification register are stored. If the address modification amount or the address modification is not performed, 0 is added to obtain the operant address when the word processing instruction or the bit processing instruction is executed.

As a result, since the address modification register can be automatically selected, it is not necessary to specify the address modification register in the word processing and the bit processing, which is conventionally performed by the program creator at the time of creation, and the address modification described above is required. It becomes easy to create a processing program for each processing.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. The programmable controller is a logical operation unit 1 that reads and processes a program, a program memory 2 that stores the program, a data memory 3 that stores various data, and an input / output device that is connected to the control targets 9 to 13. It is composed of 4-8.

Inside the logic operation unit 1, an oscillation circuit 20, a control circuit 21,
Multiplexers 22, 27, save register 23, program counter 24, address modification register 25 for word processing, address modification register 26 for bit processing, switching switches 28, 2
9, arithmetic circuit 30, accumulator 32, address register 3
2. It consists of instruction register 33, and further instruction register 3
3 comprises an instruction code section 34 and an address section 35.

FIG. 3 is an example of instructions of the programmable controller according to the present invention. Among the instructions, AND, OR, and EOR are instructions for obtaining a logical product, a logical sum, and an exclusive logical sum without address modification in the bit processing, and ANDA, ORA, and EORA are the above-mentioned AN.
This is an instruction when the D, OR, and EOR instructions are used after address modification. INB and OUTB are input / output instructions without address modification in bit processing, and INBA and OUTBA are input / output instructions with address modification. ADD, SUB, MUL, DIV are four arithmetic operations without address modification in word processing, and ADDA, SUBA, MULA, DIV
A is an arithmetic operation instruction for address modification. INW, OUTW
Is an input / output instruction without address modification in word processing, and INWA and OUTWA are input / output instructions with address modification.
The COM instruction is an instruction for obtaining the complement of the contents of the accumulator 31 and storing it in the accumulator 31. JMP (Unconditional JUM
P) and JTC (conditional JUMP) are commands that change the contents of the program counter 24. In the unconditional JUMP command, the address part of the command is stored in the program counter 24, and in the conditional JUMP command, The address portion of the conditional JUMP instruction is stored in the program counter 24 only when the condition set in the conditional JUMP instruction is satisfied. When the condition is not satisfied, the content of the program counter 24 is incremented by one. Unconditional and conditional CALL
The instruction is an instruction to change the contents of the program counter 24 like the above two JUMP instructions.
The contents of the program counter 24 are saved in the save register 23. The RET instruction is an instruction to restore the contents of the program counter 24 saved in the save register 23, and is used in combination with the CALL instruction to use a subroutine. The WAS instruction is the word processing address modification register 25.
Is an instruction for storing an address modification amount in word processing, and the address is modified by the word processing address modification register when the word processing instruction requiring the address modification after the WAS instruction is executed. The BAS instruction is an instruction for storing the address modification amount in the bit processing in the bit processing address modification register 26, and at the time of execution of the bit processing instruction requiring the address modification after the execution of the BAS instruction,
The address is modified by the bit processing address modification register.

Next, the operation of the embodiment according to the present invention will be described. Control target 9
The states of to 13 are controlled by the logical operation unit 1. The control differs depending on the control target, but is roughly classified into the following two. One is the control by word processing for controlling the inflow amount, the pressure, the number of revolutions, etc. The other is the control by bit processing for turning on / off the contacts, opening / closing the valve, starting / stopping the equipment and the like. If there are multiple states of controlled objects 9 to 13,
Different input / output addresses are assigned to each. For example, it is assumed that the input / output addresses are assigned to the control targets 9 to 13 as follows.

Controlled 9 word processing input 200 to 203 word processing output 232 to 233 bit processing input 0 to 15 bit processing output 128 to 135 Controlled 10 word processing input 204 to 207 bit processing output 234 to 235 word processing input 16 to 31 bit processing Output 136 to 143 Controlled 11 word processing input 208 to 211 Word processing output 236 to 237 Bit processing input 32 to 47 Bit processing output 144 to 151 Controlled 12 word processing input 212 to 215 Word processing output 238 to 239 Bit processing input 48 〜63 Bit processing output 152〜159 Controlled object 13 Word processing input 216〜219 Word processing output 240〜241 Bit processing input 64〜79 Bit processing output 160〜167 The logical operation part 1 is requested from the control object 9〜13. From the program memory 2 which stores the combination of the instruction and the input / output address as a program according to the processing content, the instructions are sequentially read according to the content of the program counter 24,
The controlled objects 9 to 13 are controlled by accessing the input / output addresses assigned to the input / output devices 4 to 8.

FIG. 4 shows an example of the program of the programmable controller according to the present invention, and shows an example of the program used in the embodiment shown in FIG. The program of FIG. 4 is the program 100 to 104 for the controlled objects 9 to 13.
The common subroutine 200 having the same processing contents for the controlled object 10 and the controlled object 12 is used.

When the program starts from program address 0, first, the program 100 for the controlled object 9 is executed. Next, the program 101 for the controlled object 10 is executed,
The processing of the program 101 uses the WAS and BAS instructions to modify each address in word processing and bit processing.
4 and 16 are the address modification registers for word processing 2
5 and bit processing address modification register 26
The L instruction sets the contents of the program counter 24 to the address 300, saves the leading address of the program 102 in the save register 23, and calls the subroutine 200. 300 in subroutine 200 CALLed from program 101
In the INWA instruction of the address, the address 0 of the instruction is modified by the address modification amount 204 in the word processing set in the program 101, and the state of address 204 of the input / output device 5 is acquired by the accumulator 31 by 0 + 204 = 204. Get caught.
Further, in the INBA instruction at the address 310, the address 0 of the address portion of the instruction is modified by the address modification amount 16 in the bit processing set by the program 101, and the state of the address 16 of the input / output device 5 is changed by 0 + 16 = 16. Taken in 31. The subroutine 200 ends with a RET instruction, and by executing the RET instruction, the start address of the program 102 is returned from the save register 23 to the program counter 24, and the program 102 for the controlled object 11 is executed. When the program 102 ends, the program 103 for the control target 12 is entered. Like the program 101, the program 103 sets the address modification amounts 212 and 48 in word processing and bit processing in the word processing address modification register 25 and the bit processing address modification register 26, respectively, and saves the start address of the program 104. Save to register 23 and call subroutine 200
To do. In the INWA instruction at the address 300 in the subroutine 200 that is CALLed by the program 103, the address 0 of the address portion of the instruction is modified by the address modification amount 212 in the word processing set by the program 103, and 0 + 212 = 212 is used as the input / output unit 7. The state of address 212 is taken in by Aki Umrator 31. Further, in the INBA instruction at the address 310, the address 0 of the address portion of the instruction is modified by the address modification amount 48 in the bit processing set by the program 103, and 0 + 48 = 48.
The status of address 48 of I / O device 7 is
Be taken into. In this way, the processing of the controlled object 12 is performed by the execution of the subroutine 200. When this subroutine 200 ends, the start address of the program 104 is returned to the program counter 24 from the save register 23 and the program 104 is executed. The last JMP instruction of the program 104 returns to the program 100 again.
~ 104 is repeatedly executed.

As described above, according to the embodiment of the present invention, the creator of the processing program can create the processing program without being aware of the address modification register. In addition, there is no problem even if the address modification amount in the word processing and the address modification amount in the bit processing are different. In particular, the same control is required, and it is easy to make a subroutine of the process requiring the address modification in those controls. Therefore, the capacity of the program memory can be reduced.

Further, although the address modification for the input / output device has been described in the present embodiment, the present invention can be applied to the address modification for the data memory 3 in which each constant and the like are stored.

〔The invention's effect〕

According to the present invention, the creator of a processing program need not be aware of the address modification register in word processing or bit processing, and the efficiency of creating a program can be improved.

In addition, since the address modification to the input / output device can be easily performed, it is easy to make a program into a subroutine for a plurality of control targets that require the same control, and it is possible to reduce the program creation time and the capacity of the program memory. Can be planned.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a programmable controller according to the present invention, FIG. 2 is a block diagram showing the configuration of a conventional programmable controller, and FIG. 3 is an example of instructions of the programmable controller according to the present invention. FIG. 4 is a diagram showing an example of a program of the programmable controller according to the present invention. 1 ... Logical operation part, 2 ... Program memory, 3 ... Data memory, 4-8 ... Input / output device, 9-13 ... Control object, 23 ... Save register, 24 ... Program counter,
25 ... Address modification register for word processing, 26 ... Address modification register for bit processing, 27 ... Multiplexer, 33 ... Instruction register.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hiromasa Yamaoka 5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi Ltd. Omika Factory (72) Inventor Mitsuro Takakura 5-chome, Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 Incorporated company Hitachi Ltd. Omika factory (56) References JP-A-60-79431 (JP, A) JP-A-56-57111 (JP, A)

Claims (1)

[Claims] 1. A programmable controller for storing an address modification amount and a bit in a programmable controller for sequentially reading instructions from a memory and performing word processing for handling data in word units and bit processing for handling data in bit units according to the instructions. An address modification register for processing, a means for distinguishing a word processing or bit processing instruction, and designation of whether or not the word processing or bit processing register is selected by the output of the means. Means for adding the address part of the instruction fetched from the memory and the address modification amount of the specified address modification register or 0 when the address modification is not performed, to obtain the operand address at the time of execution Programmable controller.