JPH0685442B2 - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device (hereinafter referred to as EPROM) having a read-only memory function capable of rewriting information by ultraviolet rays. ) Is applied to effective technology.

BACKGROUND ART EPROM using a field effect transistor having a floating gate as a memory cell is a technical technology in which it is important to improve the information writing efficiency and shorten the writing time, and to improve the reading efficiency and shorten the reading time. It is one of the challenges.

The writing efficiency can be improved by increasing the electric field strength near the drain region of the memory cell and increasing the injection amount of hot carriers into the floating gate.

Further, the read efficiency can be improved by reducing the channel resistance value of the memory cell and increasing the amount of current flowing between the source and drain regions.

Therefore, in order to increase the electric field strength near the drain region and reduce the channel resistance value, it is conceivable to shorten the memory cell, that is, the field effect transistor.

However, when a highly integrated EPROM having a channel length of about 1.5 [μm] or less is formed, a phenomenon in which the threshold voltage of the memory cell fluctuates significantly due to the short channel effect occurs.

Therefore, in the peripheral circuit of the EPROM, there is a tendency to adopt the LDD structure in order to improve the breakdown withstand voltage of the field effect transistor, and it can be considered to apply this to the memory cell.
Regarding the LDD structure, for example, "IEEE Transactio
n on Erectoron Devices, Vol.ED-No.4 Ap.1982, pp590〜
See 596.

However, as a result of experiments and studies in such a technique, it was found by the present inventor that when the field effect transistor of the EPROM peripheral circuit adopting the LDD structure is applied to the field effect transistor of the memory cell, the following problems occur. It was

(1) The LDD portion provided between the region where the channel of the field effect transistor of the memory cell is formed and the substantial drain region is formed with a low impurity concentration of about 1 × 10 ¹³ [atoms / cm ² ]. It For this reason, the semiconductor substrate and the LDD portion are formed by a pn junction having a low impurity concentration, and the electric field strength near the drain region is reduced, so that the writing efficiency is reduced.

(2) The LDD portion having a low impurity concentration has a resistance value of about 1 [KΩ / □] which is 20 to 30 times larger than that of the substantial drain region. For this reason, the amount of current flowing between the source and drain regions of the field effect transistor is reduced, and the reading efficiency is reduced.

(3) Because of the above (1) and (2), the field effect transistor of the memory cell cannot be shortened and the memory cell size cannot be reduced, so that the integration degree of the EPROM cannot be improved.

(4) Due to the above (1) to (3), high integration, high write efficiency and high read efficiency cannot be achieved in the EPROM.

[Object of the Invention] An object of the present invention is to provide a technical means capable of improving the integration degree of an EPROM.

Another object of the present invention is to provide a technical means capable of improving the writing efficiency of EPROM.

Another object of the present invention is to provide a technical means capable of improving the EPROM read efficiency.

Another object of the present invention is to provide a technical means capable of achieving high integration of EPROM, high write efficiency, and high read efficiency.

Another object of the present invention is to provide a technical means capable of achieving high integration of EPROM, high write efficiency, high read efficiency, and improvement of breakdown voltage of peripheral circuit elements.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Outline of the Invention] The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, the first field-effect transistor forming the memory cell of the ERROM and the second field-effect transistor of the peripheral circuit have an LDD structure, and the LDD portion of the first field-effect transistor has a semiconductor region (fifth semiconductor region). ) LDD of the field effect transistor of the peripheral circuit for the impurity concentration of
By making the impurity concentrations of the partial semiconductor regions (sixth semiconductor regions) different, and particularly by forming the fifth semiconductor region with an impurity concentration higher than that of the sixth semiconductor region, the drain of the field effect transistor of the memory cell is formed. Since the electric field strength in the vicinity of the region can be improved and the resistance value of the drain region can be reduced, the writing efficiency and reading efficiency of the EPROM can be improved.

Further, compared to the case where the LDD structure of the field effect transistor of the peripheral circuit is adopted, the extension of the depletion region formed inside the semiconductor substrate from the source / drain region can be reduced, and the field effect transistor can have a short channel. Therefore, the integration degree of EPROM can be improved.

Hereinafter, the configuration of the present invention will be described together with examples.

[Example I] FIG. 1 is an EP for explaining the outline of Example I of the present invention.
It is an equivalent circuit diagram which shows the memory cell array of ROM.

In all the drawings of the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

In FIG. 1, reference numeral 1 is an X decoder for selecting a predetermined word line, which will be described later, and for turning on a predetermined memory cell connected to the word line.

Reference numeral 2 is a Y decoder for selecting a predetermined data line described later and applying a voltage serving as information to the data line.

Reference numerals 3 and 3'denotes write circuits for selecting a predetermined word line and a data line described later and writing information to a predetermined memory cell connected to the word line and the data line.

Reference numeral 4 is a sense amplifier for reading information from a predetermined memory cell connected to the data line.

The X decoder 1, the Y decoder 2, the write circuits 3, 3'and the sense amplifier 4 constitute a peripheral circuit of the EPROM.

WL _1, WL _2, ..., WLm are word lines, and the other end is connected at one end thereof to the X-decoder 1 is connected to the write circuit 3 are provided a plurality of the Y-direction extending in the X direction . Word line
The WL is for turning on and writing information to the memory cells connected to it.

DL ₁ , DL ₂ , ..., DLn are data lines, one end of which is connected to the Y decoder 2 and the other end of which is connected to the write circuit 3 ′ and the sense amplifier 4 and which extend in the Y direction and extend in the X direction. This is provided for transmitting information of the memory cell connected to the book.

, Mnm are memory cells, and a plurality of M ₁₁ , M ₁₂ , ..., Mnm are arranged at predetermined intersections between the word lines WL and the data lines DL. The memory cell M has a floating gate and a control gate connected to a predetermined word line WL, and is constituted by a field effect transistor Q _M having one end connected to a predetermined data line DL and the other end grounded. Cage, EPRO
It is for configuring the information of M.

A plurality of memory cells M are arranged in a matrix to form a memory cell array.

Next, a specific structure of this embodiment will be described.

2 is a plan view of a main part of a memory cell array of an EPROM for explaining an embodiment I of the present invention, and FIG. 3 is a memory cell (left side) and a peripheral circuit taken along the line III-III in FIG. FIG. 4 is a cross-sectional view of a main part showing CMIS (on the right side) that configures FIG.

In FIGS. 2 and 3, 5 is ap ⁻ type semiconductor substrate made of single crystal silicon, and 5A is an n ⁻ type well region provided on a predetermined main surface portion of the semiconductor substrate 5, which constitutes an EPROM. belongs to.

A field insulating film 6 is provided mainly on the semiconductor substrate 5 between the regions where semiconductor elements are to be formed or on the upper surface of the well region 5A, and serves to electrically isolate the semiconductor elements.

Reference numeral 7 denotes a p-type channel stopper region provided in the main surface portion of the semiconductor substrate 5 below the field insulating film 6 for more electrically separating the semiconductor elements.

8A is an insulating film provided on the upper part of the main surface of the semiconductor substrate 5, and 8B is an insulating film provided on the upper part of the main surface of the semiconductor substrate 1 or the well region 5A, and is mainly used to form a gate insulating film of a field effect transistor. It is a thing.

Reference numeral 9 is a conductive layer provided on a predetermined upper portion of the insulating film 8A.
This is for forming the floating gate of the M memory cell.

Reference numeral 10 is an insulating film provided so as to cover the conductive layer 9, and is mainly for electrically separating the conductive layer 9 and the conductive layer provided above the conductive layer 9.

Reference numeral 11 denotes a conductive layer provided on the plurality of conductive layers 9 arranged in the X direction via the insulating film 10 and provided in the Y direction.
The upper part constitutes the control gate of the EPROM memory cell, and the other parts constitute the EPROM word line WL.

Reference numeral 11A is a conductive layer provided on a predetermined upper portion of the insulating film 8B and is for forming a gate electrode of the field effect transistor of the peripheral circuit.

Reference numeral 12 is the semiconductor substrate 5 on both sides of the conductive layers 9 and 11 with the insulating film 8A interposed therebetween.
It is an n-type semiconductor region (fifth semiconductor region) provided in the main surface portion (first semiconductor region main surface portion), and is for forming the LDD structure of the field effect transistor of the memory cell.

Reference numeral 13 denotes the semiconductor substrate 5 on both sides of the conductive layer 11A via the insulating film 8B.
It is an n ⁻ type semiconductor region (sixth semiconductor region) provided in the main surface portion (third semiconductor region main surface portion) and constitutes the LDD structure of the field effect transistor of the peripheral circuit.

14A is an insulating film provided on both sides of the conductive layers 9 and 11, and 14B is an insulating film provided on both sides of the conductive layer 11A, which are used to configure the source and drain regions of the field effect transistor in the LDD structure. is there.

15A is an insulating film provided so as to cover the upper part of the conductive layer 11, 15B
Is an insulating film provided so as to cover the upper part of the conductive layer 11A.

Reference numeral 16 denotes an n ⁺ type semiconductor region (second semiconductor region) provided on the main surface portion (first semiconductor region main surface portion) of the semiconductor substrate 5 with the insulating film 8A on both sides of the insulating film 14A in the region where the semiconductor element is to be formed. Semiconductor region), which is used as a substantial source region, a drain region or as a ground line (GL), and is mainly for constituting a first field effect transistor which becomes a memory cell of an EPROM.

Reference numeral 17 denotes an n ⁺ type semiconductor region (fourth semiconductor region) provided on the main surface portion (third semiconductor region main surface portion) of the semiconductor substrate 5 with the insulating films 8B on both sides of the insulating film 14B in the region where the semiconductor element is to be formed interposed. Semiconductor region), which is used as a substantial source region and a drain region and constitutes an n-channel type second field effect transistor of the peripheral circuit.

18 is provided on the main surface portion of the well region 5A through the insulating film 8B on both sides of the insulating film 14B in the region where the semiconductor element is to be formed.
It is a p ⁺ type semiconductor region, is used as a source region and a drain region, and is for forming a p channel type field effect transistor of a peripheral circuit.

The memory cell M of the EPROM, that is, the field effect transistor Q _M is mainly composed of the semiconductor substrate 5 and the insulating film 8A on the upper part thereof.
Conductive layer 9 provided via the insulating layer, and an insulating film on the conductive layer 9
The semiconductor layer 16 includes a conductive layer 11 provided via the semiconductor layer 16, a pair of semiconductor regions 16 and a semiconductor region 12 (LDD portion) provided between the channel formation region and the semiconductor region 16.

The n-channel field effect transistor Q _{n in} the peripheral circuit of the EPROM is mainly composed of the semiconductor substrate 5 and the insulating film 8B on the upper part thereof.
It is composed of a conductive layer 11A provided via the semiconductor layer 17, a pair of semiconductor regions 17 and a semiconductor region 13 (LDD portion) provided between the channel formation region and the semiconductor region 17.

The p-channel field effect transistor Q _n of the peripheral circuit of the EPROM is mainly composed of the well region 5A and the insulating film 8B on the well region 5A.
It is composed of a conductive layer 11A provided via the semiconductor layer 18 and a pair of semiconductor regions 18.

The field effect transistor Q _n and the field effect transistor Q _p constitute CMIS.

Semiconductor region 12 which will be the LDD part of field effect transistor Q _M
Has a lower impurity concentration than the field-effect transistor Q _M of the semiconductor region 16 and the field effect transistor Q _n of the semiconductor region 17, higher than the semiconductor region 13 serving as the LDD portion of the field effect transistor Q _n It is configured to have an impurity concentration.

That is, the electric field strength generated in the vicinity of the drain region (semiconductor region 12) of the field effect transistor Q _M is increased as compared with the case where the LDD structure similar to that of the field effect transistor Q _n is adopted (when it is formed with the same impurity concentration). , And sauce,
The resistance value of the drain region (semiconductor region 12) can be reduced.

Further, as compared with the case where the LDD structure similar to that of the field effect transistor Q _n is adopted, it is formed inside the semiconductor substrate 5 from the pn junction between the channel forming region of the semiconductor substrate 5 and the source / drain regions (semiconductor region 12). The extension of the depletion region can be suppressed and the channel of the field effect transistor Q _M can be shortened.

An insulating film 19 is provided so as to cover semiconductor elements such as field effect transistors Q _M , Q _n , and Q _p , and is for electrically separating from a conductive layer provided above the insulating film.

Reference numeral 20 denotes a connection hole provided by selectively removing the insulating films 8A, 8B, 19 above the predetermined semiconductor regions 16, 17, 18 and
It is for electrically connecting 16, 17, 18 and the conductive layer provided on the insulating film 19.

Reference numeral 21A denotes a conductive layer which is electrically connected to a predetermined semiconductor region 16 through the connection hole 20 and extends in the Y direction so as to intersect with the conductive layer 11 on the insulating film 19 and is provided in plural in the X direction. Yes, EP
It is for configuring the data line DL of the ROM.

21B is a conductive layer which is electrically connected to predetermined semiconductor regions 17 and 18 through the connection hole 20 and is provided on the insulating film 19 and is formed by the CMIS.
Is for configuring an inverter circuit.

Next, regarding the specific manufacturing method of the present Example I, the control gate of the field effect transistor of the memory cell,
This will be described using an example of forming the gate electrode of the field effect transistor of the peripheral circuit in the same manufacturing process.

4 to 10 are cross-sectional views of the essential parts of the memory cell of the EPROM and the CMIS forming the peripheral circuit in each manufacturing process for explaining the manufacturing method of the embodiment I of the present invention.

First, a p ⁻ type semiconductor substrate 5 made of single crystal silicon is prepared. Then, an n ⁻ type well region 5A is formed in the main surface portion of the semiconductor substrate 5 which will be a p channel type field effect transistor forming region.

After that, a field insulating film 6 is formed on the semiconductor substrate 5 and the well region 5A main surface between semiconductor elements, and a p-type channel stopper is formed on the semiconductor substrate 5 main surface below the field insulating film 6 in substantially the same step. Region 7 is formed.

Then, as shown in FIG. 4, an insulating film 8A is mainly formed on the semiconductor substrate 5 and the well region 5A so as to serve as a gate insulating film of a field effect transistor serving as a memory cell.
To form. The insulating film 8A is, for example, a silicon oxide film formed by thermal oxidation of a semiconductor substrate and has a film thickness of 300 to 350.
It may be formed with a thickness of about [angstrom (hereinafter, referred to as [A])].

After the step shown in FIG. 4, impurities are mainly introduced into the semiconductor substrate 5 and the well region 5A main surface portion through the insulating film 8A in order to adjust the threshold voltage of the field effect transistor to be a memory cell. This impurity is introduced by an ion implantation technique using, for example, boron ions of about 1 × 10 ¹² [atoms / cm ² ].

After that, a first conductive layer in the manufacturing process is formed on the field insulating film 6 and the insulating film 8A. As the conductive layer, a polycrystalline silicon film formed by a chemical vapor deposition (hereinafter referred to as CVD) technique to which phosphorus is introduced may be used.

Then, in order to form the floating gate of the memory cell, the conductive layer is subjected to predetermined patterning to form the conductive layer 9A. By this step, the insulating film 8A in the field effect transistor formation region of the peripheral circuit is removed.

After that, the insulating film 10 that covers the conductive layer 9A is selectively formed.
As the insulating film 10, for example, a silicon oxide film formed by thermal oxidation of the conductive layer 9A may be used, and the film thickness may be formed to about 250 to 350 [A].

Then, as shown in FIG. 5, an insulating film 8B is formed above the main surface of the semiconductor substrate 5 and the well region 5A in the field effect transistor forming region of the peripheral circuit so as to become the gate insulating film thereof. The insulating film 8B is, for example, a silicon oxide film formed by thermal oxidation of the semiconductor substrate 5 and has a film thickness of 200 to 300.
It may be formed to about [A]. The insulating film 8B can be formed in the same step as the insulating film 10.

After the step shown in FIG. 5, mainly in order to adjust the threshold voltage of the field effect transistor which becomes the peripheral circuit,
Impurities are introduced into the semiconductor substrate 5 and the main surface of the well region 5A through the insulating film 8B. The introduction of this impurity is, for example,
Boron ions of about 1 × 10 ¹² [atoms / cm ² ] are used and the ion implantation technique is used.

Then, the second conductive layer 11B in the manufacturing process is formed on the field insulating film 6 and the insulating film 8B so as to cover the conductive layer 9A with the insulating film 10 interposed therebetween. This conductive layer 11B is a CVD
A polycrystalline silicon film obtained by introducing phosphorus may be used.

Then, the conductive layer 11B in the field effect transistor formation region of the peripheral circuit is selectively patterned to form a conductive layer 11A to be a gate electrode as shown in FIG.

After the step shown in FIG. 6, an etching mask 22 made of a resist is formed in order to form a floating gate and a control gate of the memory cell. Then, the conductive layers 11B and 9A and the insulating film 10 are etched using the etching mask 22 to form the conductive layers 9 and 11.

Then, using the etching mask 22 as a mask for introducing impurities, the field effect transistor to be a memory cell is LD
In order to obtain the D structure, as shown in FIG. 7, n-type semiconductor regions 12A are formed in the main surface portion of the semiconductor substrate 5 on both sides of the conductive layers 9 and 11 with the insulating film 8A interposed therebetween. This semiconductor region 12A is 1 ×
It may be formed by using an arsenic ion of about 10 ¹³ to 1 × 10 ¹⁵ [atoms / cm ² ] and an ion implantation technique with energy of about 80 [KeV]. By using arsenic as the ion-implanted impurity, a shallow junction can be formed, so that the surface concentration can be made relatively high even if the ion-implanted amount is reduced.

After the step shown in FIG. 7, the etching mask 22 is removed.

Then, an insulating film (silicon oxide film) 23A that covers the conductive layers 9 and 11 and an insulating film (silicon oxide film) 23B that covers the conductive layer 11A are formed by oxidation. This may be formed so as to cover at least the conductive layer 9 to be the floating gate,
It is possible to prevent unnecessary emission of electrons, which become information stored in the conductive layer 9, and improve the information retention characteristics.

After that, in order to make the field-effect transistor of the memory cell and the n-channel field-effect transistor of the peripheral circuit have an LDD structure, an impurity introduction mask 24 made of a resist for covering other p-channel field-effect transistors and the like.
To form.

Then, using the impurity introducing mask 24, as shown in FIG. 8, n on the semiconductor substrate 5 main surface portion (the portion where the semiconductor region 12A is formed) on both sides of the conductive layers 9 and 11 with the insulating film 8A interposed therebetween, -Type semiconductor region 12 is formed, and conductive layer 11A is formed through insulating film 8B.
N ⁻ type semiconductor regions 13 are formed on the main surface portions of the semiconductor substrate 5 on both sides. The semiconductor regions 12 and 13 are 1 × 10 ¹³ [atoms / c
It may be formed by an ion implantation technique with an energy of about 50 [KeV] using phosphorus ions of about [m ² ].

The impurity introducing mask 24 may also be used in the field effect transistor portion of the memory cell so that the semiconductor region 12 is not implanted with phosphorus ions.

That is, the LD of the field effect transistor that becomes
The impurity concentration of the D portion, that is, the impurity concentration of the semiconductor region 12 may be controlled in the step of forming the semiconductor region 12A. In addition, the LDD of the field effect transistor that becomes the peripheral circuit
The impurity concentration of the portion, that is, the semiconductor region 13 may be controlled in the step of forming the same.

After the step shown in FIG. 8, an insulating film is formed so as to cover the entire surface. As the insulating film, for example, a silicon oxide film formed by a CVD technique formed at a high temperature of about 600 to 800 [° C.] and a low pressure of about 1.0 [torr] may be used.

Then, the insulating film is anisotropically etched to form a conductive layer.
Insulating films 14A and 14B on both sides of 9, 11 and conductive layer 11A, respectively.
(Sidewall) is formed.

After that, the conductive layers 9, 11, 11A, the field insulating film 6, the resist mask 26 and the insulating films 14A, 14B are used as a mask for introducing impurities, and ion implantation of n-type impurities is performed. The semiconductor substrate 5 main surface portion (the portion where the semiconductor region 12 is formed) via the insulating film 8A in the field effect transistor forming region to be a memory cell, and the insulating film 8B in the n channel type field effect transistor forming region to be a peripheral circuit are formed. As shown in FIG. 9, n ⁺ type semiconductor regions 16 and 17 are selectively formed on the main surface of the semiconductor substrate 5 (the part where the semiconductor region 13 is formed). The semiconductor regions 16 and 17 are, for example, 1 × 10 ¹⁶ [atoms / cm ² ]
It may be formed by an ion implantation technique with an energy of about 80 [KeV] using arsenic ions of about the same.

The impurity concentration of the semiconductor regions 16 and 17 may be controlled in this forming process.

Therefore, in the field effect transistor that becomes the memory cell, the semiconductor region 12 that controls the writing efficiency and the reading efficiency is used.
Since the impurity concentration of the semiconductor region 16 can be increased irrespective of the impurity concentration of, the resistance value thereof can be significantly reduced. Therefore, the ground line GL (semiconductor region 16) extending through the memory cell array can be downsized, and the read efficiency can be improved.

In addition, in the present embodiment, arsenic ions are used to form the semiconductor regions 16 and 17 in order to reduce the junction depth and further shorten the channel, but phosphorus ions are used to form the semiconductor regions 13. Since it is used, the impurity concentration gradient does not become steep, and in particular, the breakdown withstand voltage in the LDD portion (semiconductor region 13) can be sufficiently secured.

After the step shown in FIG. 9, the insulating film 15A covering the upper part of the conductive layer 11 and the insulating film 15B covering the upper part of the conductive layer 11A are thermally oxidized.
To form.

Then, as shown in FIG. 10, the insulating film through the insulating film 8B is used.
14B Both sides of the well region 5A have p ⁺ type semiconductor regions 1 on the main surface.
Forming eight. This semiconductor region 18 is 1 × 10 ¹⁵ [atoms / c
It may be formed by an ion implantation technique with an energy of about 80 [KeV] using boron ions of about [m ² ]. In general, p-type impurities have a high diffusion rate, so that they can sufficiently wrap around under the insulating film 14B.

After the step shown in FIG. 10, the insulating film 19 is formed and the connection hole 20 is formed.
To form. Then, as shown in FIGS. 2 and 3, by forming the conductive layers 21A and 21B so as to be electrically connected to the predetermined semiconductor regions 16, 17 and 18 through the connection holes 20, The EPROM of this embodiment is completed.

After this, a treatment such as a protective film may be performed.

As described above, according to the present embodiment, the LDD portion of the field effect transistor which becomes the memory cell is formed with an impurity concentration lower than that of the source and drain regions, and is formed more than the LDD portion of the field effect transistor which becomes the peripheral circuit. By forming with a high impurity concentration, the electric field strength generated in the vicinity of the LDD part (drain region) of the field effect transistor which becomes the memory cell is increased as compared with the case where the same LDD structure as the field effect transistor which becomes the peripheral circuit is adopted. be able to.
Therefore, the field effect transistor serving as a memory cell can improve the writing efficiency.

Further, by forming the field-effect transistor serving as a memory cell with an LDD structure, it is possible to suppress the extension of the depletion region formed inside the semiconductor substrate from the pn junction between the channel formation region and the LDD portion (source and drain regions). You can
Therefore, it is possible to shorten the channel of the field effect transistor which becomes the memory cell, so that the writing efficiency and the reading characteristic are improved, and the memory cell area is reduced.
The degree of integration of M can be improved.

Further, since the LDD portion of the field effect transistor which becomes the memory cell can be formed by the mask for forming the floating gate and the control gate, the number of manufacturing steps is not increased.

In addition, the LDD of the field effect transistor that becomes
By separately forming the LDD portion of the field effect transistor that serves as the peripheral portion and the peripheral circuit and the substantial source and drain regions thereof, the impurity concentration of each can be optimally set. Therefore, in particular, since the substantial source and drain regions of the field effect transistor to be the memory cell can be formed with a high impurity concentration and the resistance value thereof can be reduced, the read efficiency can be improved. Furthermore, since the area occupied by the ground line extending through the memory cell array can be reduced, EPROM
The degree of integration can be improved.

Further, by forming arsenic ions in the substantial source and drain regions, it is possible to reduce the amount of impurities flowing into the channel formation region, which makes it possible to shorten the channel and improve the integration degree of EPROM. can do.

Example II This example II is another specific manufacturing method of the example I, in which the floating gate of the field effect transistor of the memory cell and the gate electrode of the field effect transistor of the peripheral circuit are the same. This will be described using an example of forming in the manufacturing process.

11 and 12 are cross-sectional views of the essential parts of the memory cell of the EPROM and the CMIS forming the peripheral circuit in each manufacturing process for explaining the manufacturing method of the embodiment II of the present invention.

After the process shown in FIG. 4 of the embodiment I, the first conductive layer in the manufacturing process is formed on the field insulating film 6 and the insulating film 8A.

Then, in order to form the floating gate of the memory cell and the gate electrode of the peripheral circuit, the conductive layer is subjected to predetermined patterning to form the conductive layers 9A and 9B.

Then, as shown in FIG. 11, insulating films 10 and 10A are formed to cover the conductive layers 9A and 9B.

After the step shown in FIG. 11, a conductive layer is formed through the insulating films 10 and 10A.
Field insulating film 6 and insulating film 8A so as to cover 9A and 9B
A second conductive layer 11B in the manufacturing process is formed on the top.

Then, as shown in FIG. 12, the conductive layer 11B other than the memory cell array is removed.

After the step shown in FIG. 12 is performed, the steps after the step shown in FIG.
Is completed.

As described above, according to this embodiment,
It is possible to obtain substantially the same effect as.

[Example III] Example III is an example of reducing the resistance values of the control gate of the memory cell and the gate electrode of the peripheral circuit to increase the operating speed of the EPROM.

FIG. 13 is a cross-sectional view of essential parts of a memory cell of an EPROM and a CMIS forming a peripheral circuit for explaining a third embodiment of the present invention.

In FIG. 13, reference numerals 25A and 25B denote conductive layers provided on the conductive layers 11 and 11A and have a resistance value lower than that of the conductive layers 11 and 11A, thereby increasing the operating speed of the EPROM. It is for doing.

Next, regarding the specific manufacturing method of the present Example III, by using an example of forming the control gate of the field effect transistor of the memory cell and the gate electrode of the field effect transistor of the peripheral circuit in the same manufacturing process, Explain.

FIG. 14 is a cross-sectional view of essential parts of a memory cell of an EPROM and a CMIS forming a peripheral circuit in a predetermined manufacturing process for explaining the manufacturing method of the embodiment III of the present invention.

After the step shown in FIG. 5 of Example I, conductive layers 11 and 25 are formed on the entire surface of the substrate. A conductive layer 11 in the memory cell array for forming a field effect transistor of the memory cell.
And 25 are patterned to form the conductive layer 11B, and the conductive layer 25C is formed on the conductive layer 11B. The conductive layer 25 may be formed of, for example, a refractory metal such as molybdenum, tungsten, tantalum, or a silicide that is a compound of the refractory metal and silicon by a sputter deposition technique.

After that, the conductive layers 11 and 25 in the field effect transistor formation region of the peripheral circuit are selectively patterned to form conductive layers 11A and 25B to be gate electrodes, as shown in FIG.

After the step shown in FIG. 14, the step shown in FIG. 7 of Example I is performed to form the conductive layer 9 to be the floating gate and the conductive layers 11C and 25A to be the control gate.
Then, after forming the semiconductor region 12A, the conductive layer 25A, 25B
Is subjected to heat treatment to reduce its resistance value.

Thereafter, the steps shown in FIG. 8 of the embodiment I are applied to complete the EPROM of the embodiment III.

As described above, according to this embodiment,
It is possible to obtain substantially the same effect as.

Further, by forming the control gate of the field effect transistor of the memory cell, the word line, and the gate electrode of the field effect transistor of the peripheral circuit with refractory metal or silicide, the resistance values thereof can be reduced, so that the EPROM The operating speed can be increased.

[Effects] As described above, according to the novel technical means disclosed in the present application, the effects described below can be obtained.

(1) By forming the LDD portion of the field effect transistor, which becomes the memory cell, with an impurity concentration lower than that of the source and drain regions and with the impurity concentration higher than that of the LDD portion of the field effect transistor, which becomes the peripheral circuit, Compared to the case of adopting the same LDD structure as the field effect transistor that becomes the circuit,
Since the electric field strength generated in the LDD portion (drain region) can be increased, the writing efficiency of EPROM can be improved.

(2) The field-effect transistor serving as a memory cell has an LDD structure to suppress the extension of the depletion region formed inside the semiconductor substrate from the pn junction between the channel formation region and the LDD portion (source / drain region). Therefore, it is possible to shorten the channel of the field effect transistor which becomes the memory cell.

(3) Since the area of the memory cell can be reduced by the above (2), the integration degree of the EPROM can be improved.

(4) Since the LDD portion of the field effect transistor which becomes the memory cell can be formed by the mask forming the floating gate and the control gate, the number of manufacturing steps is not increased.

(5) LDD of field effect transistor that becomes a memory cell
By separately forming the LDD portion of the field effect transistor that serves as the peripheral portion and the peripheral circuit and the substantial source and drain regions thereof, the impurity concentration of each can be optimally set.

(6) According to the above (5), the substantial source and drain regions of the field effect transistor to be a memory cell can be formed with a high impurity concentration and the resistance value thereof can be reduced, so that the reading efficiency can be improved. it can.

(7) Because of the above (5) and (6), the occupied area of the ground line extending through the memory cell array can be reduced, so that the integration degree of the EPROM can be improved.

(8) By forming the substantial source and drain regions with arsenic ions, it is possible to reduce the amount of impurities flowing into the channel forming region, so that the channel can be shortened.

(9) Since the area of the memory cell can be reduced by the above (8), the integration degree of the EPROM can be improved.

(10) The above (1), (2) to (3), (6) to (1
With 0), higher integration of EPROM, higher write efficiency, and higher read efficiency can be achieved.

(11) Due to the above (1) to (10), there is a synergistic effect that the EPROM can be highly integrated, the writing efficiency and the reading efficiency can be improved, and the breakdown voltage of the peripheral circuit element can be improved. be able to.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Of course, you can do that.

[Brief description of drawings]

FIG. 1 is an EP for explaining the outline of Example I of the present invention.
FIG. 2 is an equivalent circuit diagram showing the memory cell array of the ROM, FIG. 2 is a plan view of a main portion of the memory cell array of the EPROM for explaining the embodiment I of the present invention, and FIG. 3 is a sectional view taken along line III-III of FIG. FIG. 4 to FIG. 10 are cross-sectional views of a main part showing a memory cell and a CMIS forming a peripheral circuit in a line, and FIGS. And FIG. 11 and FIG. 12 are cross-sectional views of a main part of the CMIS forming the peripheral circuit, and FIG. 11 and FIG. FIG. 13 is a cross-sectional view of an essential part of a CMIS forming a peripheral circuit and a memory cell of an EPROM for explaining a third embodiment of the present invention, and FIG. 14 is a cross-sectional view of the present invention. EPROM memory cells and peripherals in a predetermined manufacturing process for explaining the manufacturing method of Example III of It is a fragmentary cross-sectional view of the CMIS constituting the circuit. In the figure, 1 ... X decoder, 2 ... Y decoder, 3,3 '...
Write circuit, 4 sense amplifier, 5 semiconductor substrate, 5A well region, 6 field insulating film, 7
... Channel stopper area, 8A, 8B, 10,14A, 14B, 15A, 15B, 1
9,23A, 23B ... Insulating film, 9,9A, 9B, 11,11A, 11B, 21A, 21B, 25
A, 25B, 25C ... conductive layer, 12,12A, 13,16,17,18 ... semiconductor region, 20 ... connection hole, 22,24 ... mask.

 ─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-60-136374 (JP, A) JP-A-59-126674 (JP, A) JP-A-60-110167 (JP, A) JP-A-60- 110168 (JP, A) Actual opening 60-110169 (JP, U) Actual opening 60-110170 (JP, U)

Claims (3)

[Claims] 1. A conductive layer provided on a first semiconductor region main surface portion of one semiconductor substrate with a first gate insulating film interposed therebetween,
A first field effect transistor formed by second semiconductor regions of the second conductivity type provided on the main surface portion of the first semiconductor region on both sides of the conductive layer, and a third semiconductor region of the semiconductor substrate. A conductive layer provided on the main surface portion via a gate insulating film, and a third layer on both sides of the conductive layer.
A second field-effect transistor formed by a fourth semiconductor region of the second conductivity type provided in the semiconductor region main surface part of the first field-effect transistor. A second semiconductor region having a lower impurity concentration than the second semiconductor region in the first semiconductor region main surface portion between the region where the channel of the field effect transistor is formed and the second semiconductor region, A fifth semiconductor region having a self-alignment formation is provided on both sides of the conductive layer, and the second field effect transistor is formed between a region where a channel of the field effect transistor is formed and a fourth semiconductor region. A self-aligned sixth side surface of the third semiconductor region main surface portion with respect to both side portions of the conductive layer which is of the second conductivity type and has a concentration lower than that of the fifth semiconductor region. A semiconductor region is provided, the first field effect transistor is applied to a memory cell capable of writing and reading information, and the second field effect transistor is applied to a peripheral circuit of the memory cell. A semiconductor integrated circuit device. 2. The impurity concentration of the pair of second semiconductor regions of the first field effect transistor is equal to the impurity concentration of the pair of fourth semiconductor regions of the second field effect transistor, and the fifth, The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is higher than the sixth semiconductor region. 3. A conductive layer provided on the main surface of one semiconductor substrate with a gate insulating film interposed therebetween, and a second semiconductor layer provided on both sides of the conductive layer on the first semiconductor region main surface portion of the semiconductor substrate. A method of manufacturing a semiconductor integrated circuit device having a plurality of field-effect transistors constituted by a conductive second semiconductor region, the first field-effect being applied to a memory cell capable of writing and reading information. A step of selectively introducing a first impurity into the first semiconductor region main surface portion of the conductive layer side portion of the transistor formation region so that the semiconductor region is self-aligned with the conductive layer side portion; A semiconductor region is self-aligned with the conductive layer side portion on the first semiconductor region main surface portion of the conductive layer side portion of the second field effect transistor formation region applied in the peripheral circuit of the cell, and The step of selectively introducing the second impurity so that the semiconductor region has a lower concentration than the semiconductor region formed by the first impurity introduction, and the conductivity of the first and second field effect transistor forming regions. A step of selectively forming a thick insulating film on a layer side portion, and a step of forming a thick insulating film on the first semiconductor region main surface portion of the insulating film side portion of the first and second field effect transistor forming regions, And a step of selectively introducing a third impurity so that the semiconductor region is self-aligned with the semiconductor region, the method for manufacturing a semiconductor integrated circuit device.