JPH0685553B2 - Image processing device - Google Patents

Description

The present invention relates to an image processing device that processes image information as an electric signal.

2. Description of the Related Art As an image information processing device, a copying device that duplicates a document image is widely used. This type of device exposes a document with a light source such as a fluorescent light, makes reflected light from the document incident on a photoconductor, forms a latent image on the photoconductor, and develops the latent image by a well-known developing means. A general electrophotographic apparatus as described above is used. However, for example, in the case of extracting only a part of an original and making a copy, in a conventional apparatus, it is necessary to mask an unnecessary part of the original to make a copy, or to cut out a necessary part from a copy. Therefore, it has been necessary to perform inefficient work to obtain a copy of a necessary portion.

Further, by reading the original image as an electric signal and electrically processing the image information converted into the electric signal,
In addition to the functions described above, an image processing apparatus has been proposed which can perform image processing such as extracting a part of a document for reproduction, combining a plurality of images, or changing the image density of only a part of the document. ing.

For example, it has been considered that image information of an original is converted into an electric signal by a solid-state image sensor such as a CCD and the electric signal is electrically processed to extract a part of the image.

Further, as this type of image processing apparatus has many functions, the apparatus becomes complicated and the users are limited to those who are accustomed to the apparatus. In addition, the image processing time is too long, which is inconvenient for the user.

The present invention provides an image processing system that solves the conventional drawbacks.

Further, in view of the above points, it is another object of the present invention to provide an image processing system capable of performing image processing at high speed with a simple operation.

That is, an object of the present invention is to perform image processing for recording an image of a desired area of an original on a recording material with a simple operation and surely. Specifically, the original image is read and the original image is displayed. A reading unit that outputs image information, a memory that stores the image information output by the reading unit, and a coordinate input surface corresponding to the original document, and a desired original document based on an instruction to the coordinate input surface by a pen. A digitizer for outputting coordinate information representing an area; display means for graphically displaying a desired area of the original according to the coordinate information output from the digitizer; and a display means for displaying the desired area of the original graphically displayed on the display means. The image processing program displayed on the display means includes coordinate information and processing data for recording an image of a desired area of the document, which is graphically displayed on the display means, on a recording material. Storage means for storing a plurality of sets of grams, designating means for designating one of the plurality of sets of image processing programs stored in the storage means, and the image processing program designated by the designating means. Reading means for selectively reading from the storage means, and image information stored in the memory according to the image processing program read from the storage means by the reading means, and the coordinates included in the image processing program. An image processing apparatus is provided, which has a recording unit for recording an image of a desired area of the original defined by information on a recording material according to the processing data included in the image processing program.

Hereinafter, the present invention will be described in more detail with reference to the drawings.

FIG. 1-1 shows the configuration of an embodiment of the image processing apparatus according to the present invention. Reference numeral 1 is a reader unit having a line sensor such as a CCD for photoelectrically reading a document image, and 2 is a document of a predetermined size, which is serially output from the reader unit 1 and is converted into an electric signal image information of the document. A page memory 3 composed of a semiconductor dynamic memory for storing the minute as a unit, and a printer section 3 composed of a laser beam printer for forming an image on a recording material such as paper by image information stored in the page memory 2 and serially output. Reference numeral 4 denotes a disk memory which stores all or a part of the image information stored in the page memory 2, and the image information is also transferred from the disk memory 4 to the page memory 2. The disk memory 4 also stores image processing information. Reference numeral 5 is an image processing unit for performing image processing on the image information output from the reader unit 1, the image information stored in the page memory 2 and the image information stored in the disk memory 4, and 6 is an image processed by the user to the image processing unit 5. A digitizer for inputting processing information for processing, 7 displays the processing information input by the digitizer 6, and a CR for allowing the user to easily input or modify the processing information in an interactive manner.
T and 9 are DMA controllers that control the DMA transfer of image information. Further, the page memory 2, the disk memory 4, and the image processing unit 5 are collectively referred to as an image processing control unit 12. A perspective view of the apparatus of the embodiment is shown in FIG. 1-2. 10 is page memory
2, an image processing unit composed of an image processing control unit 12 having a disk memory 4 and an image processing unit 5, a reader unit 1 and a printer unit 3, and 11 an image processing unit composed of a digitizer 6 and a CRT 7. It is an information forming unit. Alternatively, the reader unit 1 and the printer unit 3 may be provided independently and connected to the image processing unit 5 by a transmission line such as an optical fiber cable or a metal cable.

FIG. 2 shows a perspective view of the digitizer 6.

Reference numeral 6 is a digitizer body, and 8 is a stylus pen. When the stylus pen 8 points on the digitizer 6, the coordinate information of the point pointed on the digitizer 6 is sent to the image processing unit 5, and the image processing unit 5 uses the coordinates. The image processing information corresponding to the information is recognized. An area 6-1 of the digitizer 6 is an input section provided for inputting an alphanumeric character, a number and a character string command group, and a shaded area 6-2 is a paper placing position on which an original or a recording material is placed. .

Fig. 3-1 shows a detailed view of the surface of the digitizer 6. In this embodiment, for simplicity of explanation, a case of using an A-size original and a recording material will be described. The paper loading position 6-2 indicated by diagonal lines corresponds to the A4 size, and the paper is the loading reference 6
Place according to -3. As a result, the sheet mounting position 6-2 on the digitizer 6 and the image information stored in the buffer memory 2 have a one-to-one correspondence. For example, when it is desired to extract a part of the document image stored in the buffer memory 2, the extraction position is specified by placing the document on the digitizer 6 and actually pointing the position on the document with the stylus pen 8. it can. Input unit 6-1
As described above, a group of numbers, alphanumeric characters and character string commands are divided into areas as shown in the figure. For example, when "D" is desired to be input, the stylus pen 8 is used to indicate a portion surrounded by "D".

An embodiment of a method for specifying an image area by the digitizer 6 will be described with reference to FIG. 3-2. Further, FIG. 3-3 shows an operation control flow chart of the image processing section 5 based on the designation from the digitizer 6. Reference numeral 15-1 is a manuscript on which image processing is based, and reference numeral 15-7 is a copy output as a hard copy after image processing. That is, this is an example of image processing in which the character portion of the original 15-2 is extracted and the extracted image information is copied at a position such as the copy 15-7. When the power of the device is turned on, the device is operated by a start switch. Ready to operate. Operator is manuscript 15
-1 is placed on the reader unit 1 and the start switch is operated at step S1. Leader unit 1 in step S2
The image information of the original 15-1 is read by the scanning of the line sensor inside and is stored in the page memory 2 as an electric signal (the image stored in the page memory 2 is shown at 15-2).
Next, the operator places the manuscript 15-1 on the manuscript mounting surface 6-2 on the digitizer 6, defines a rectangle surrounding the character part of the manuscript as shown in 15-3, and uses the stylus pen 8 to make four vertices. One of them (point a, for example) is designated. Step
At S3, the X coordinate and the y coordinate of the designated point on the digitizer 6 are sensed, and at step S4, the first address of the page memory 2 is set in the RAM according to the coordinate information (x ₁ , y ₁ ) sensed at step S3. . The operator again points on the digitizer 6 the vertex d touched by the stylus pen 8 toward the vertex a of the rectangle previously designated. That is, the extracted portion is defined as a rectangle, and its position and size are determined by designating the facing vertex of the rectangle on the digitizer 6. At step S5, the x and y coordinates of the designated point on the digitizer 6 are sensed, and the process proceeds to step S6. In step S6, the second address of the page memory 2 is set in the RAM according to the coordinate information (x ₂ , y ₂ ) sensed in step S5. In step S7, the first coordinate information (x ₁ , y ₁ )
And the second coordinate information (x ₂ , y ₂ ) are used to perform arithmetic processing to rearrange the x and y coordinates, and coordinate information corresponding to the other two vertices (points b and c) of the rectangle. (X ₂ ,, y ₁ ) and (x ₁ ,,
y ₂ ) is obtained, and the third address and the fourth address of the page memory 2 are set in the RAM according to these values. Step S8
Then, the page memory 2 is addressed at the first to fourth addresses corresponding to the respective vertices of the rectangle set in the RAM as described above, and the image information defined by the rectangle is transferred to the disk memory 4. As a result, the image information to be extracted from the page memory 2 is stored in the disk memory 4. (The information in the disk memory 4 is shown in 15-4.) In step S9, the contents of the page memory 2 where the transfer of the necessary image information is completed are cleared.

Next, the operator removes the original 15-1 on the digitizer 6 and indicates on the digitizer 6 with the stylus pen 8 the position at which the extracted image is output as a hard copy.
The input of this position information is performed by designating one vertex (for example, point e) of the reference rectangle on the digitizer 6 as shown in 15-5. In other words, the information in the disk memory 4 is read from the page memory 2, and when it is stored in the disk memory 4 by the first to fourth addresses set in the RAM, the size of the rectangular image is Since it has already been determined in the index part as an offset value, it is only necessary to specify one vertex of the rectangle in order to determine the output position at the time of output. Step S1
At 0, the designated x-coordinate and y-coordinate are sensed, and the process proceeds to step S11. In step S11, 4 on the digitizer 6 of the page memory 2 is read according to the coordinate information sensed in step S10.
Four addresses corresponding to points e to h (the size of the rectangle consisting of e to h is the same as the size of the image information 15-4 in the disk memory 4) are set in the RAM. Step S
In 12, the image information in the disk memory 4 is RAM in step S11.
Page memory 2 according to the four addresses set in
Store at specified location in.

15-6 shows the information in the page memory 2 to which the image information in the buffer memory 6 has been transferred. As described above, the image information obtained by extracting the character portion of the original 15-1 and moving it to an arbitrary position is stored in the page memory 2. If it is determined in step S13 that the copy button has been pressed, the process proceeds to step S14, the image information 15-6 in the page memory 2 is transferred to the printer device 3, and the printer device is driven to obtain a copy 15-7 as a hard copy. To be In step S15, if the copying is completed, the process proceeds to step S16 to perform the copy operation and prepare for the next image processing.

As described above, the addressing in the page memory 2 in which the image information of the document is stored is specified on the digitizer by specifying only the two vertices of the rectangle facing each other, so that the reading corresponding to the four vertices of the rectangle is performed. 4 addresses for RAM can be set in RAM. Furthermore, when transferring the image information whose size is already registered as an index to page memory 2, only one rectangular vertex is used as a reference point on digitizer 6. By specifying with, a rectangular 4
RAM for 4 addresses of page memory 2 corresponding to the vertex
Can be set to As a result, an image processing apparatus capable of efficiently addressing the page memory 2 is provided, and further, an image processing apparatus in which desired portions different from each other of the original are arranged and copied easily can be provided.

Figure 4 shows the screen configuration of CRT7.

In this embodiment, the CRT7 is a NEC 12-inch color TV (JC
-1202DH). An area 7-1 on the screen indicates an input image area corresponding to A4 size, a ground color is white, and an area 7-4 designated by the digitizer 6 is green. Area 7-
Reference numeral 2 denotes an output image area corresponding to the A4 size, the ground color is blue, and the area 7-5 designated by the digitizer 6 is red. Area 7-3 is an application buffer for displaying the processing information input from the digitizer 6, and area 7-6 is a text buffer for displaying the completed application.

The operation method of the image processing apparatus of this embodiment will be described below. The outline of the operation of the present apparatus is that the reader unit 1 performs desired image processing on the read image information and outputs it by the printer unit 3. Here, the processing information for image processing is stored in the disk memory 4 as a program in advance while interacting with the area 7-3 of the CRT 7 by the digitizer 6, and the image processing is performed according to the stored processing information. A program for this image processing is defined as an application file. Further, as described with reference to FIG. 3, it is possible to input processing information at the same time as image processing and perform image processing in real time.

Further, a plurality of application files can be stored in the image processing section 5, and each application file can be stored in a two-digit number or a six-character alphabet, or a combination of numbers and blanks. File name is given by.

On the other hand, image information transferred from the page memory 2 to the disk memory 4 and stored according to the processing information is defined as an image file. Since the disk memory 4 stores a plurality of image files, each image file is also given a file name in two ways such as a two-digit number or a six-character alphabet, and a combination of numbers and blanks. Incidentally, it is possible to instruct whether these two types of files can be erased or not at the time of storage. That is, it means that the file is not erasable when "W" is input and is erasable when "" is input.

Next, the definition of the command for image processing input from the digitizer 6 will be shown. The command type is shown in FIG.
a is a command character and b is a parameter. The command is fixed by a parameter consisting of one command character (alphabet), a number in parentheses, a alphabet and a blank as shown in the figure. However, parameter b
May not be necessary depending on the command.

The types of parameters will be described below.

[Parameters related to image quality]

Regarding the image quality, halftone designation and edge enhancement image processing can be performed. When halftone is specified, dither processing is performed at the time of reading the original, but eight types of this dither pattern are provided and the numbers "1", "2" ... "8" must be input with the input section 6-1 of the digitizer 6. Defines halftone intensity. If you do not specify halftone, enter. For edge enhancement, digitizer 6
Input "E" in the input unit 6-1 of the above, otherwise enter "".

[Parameters for coordinates]

There are two parameters of the position and the size for the coordinates indicating the extraction position and the movement position of the image. Input of these parameters is carried out at the paper loading position 6-2 of the digitizer 6.
The desired position of the CRT7 is input by indicating it with the stylus pen 8, and as described above, the area is displayed in a color different from the ground color on the CRT7, and at the same time, a specific three-digit number is displayed in the area 7-3 of the CRT7. Is displayed in mm (unit: mm). The position parameter indicates the reference coordinate (X coordinate Y coordinate) of the desired position, and the size parameter indicates the length in the X and Y directions from the reference coordinate.

[Parameters Related to Transfer to Buffer Memory 2] As described above, the page memory 2 receives the image information of the document from the reader unit and the image information from the disk memory 4. When combining these image information, the digitizer 6
Enter "" above, otherwise define "".

The types of one-character commands will be described below. These are input by pointing each character of the input section of the area 6-1 of the digitizer 6 with the stylus pen 8.

M ... Clear page memory 2 F ... Clear image file R ... Read original P ... Printer output L ... Load image file into page memory 2 S ... Image information in page memory 2
Stored in E ... Executing the application file W ... Temporarily suspending the application file that is being executed Q ... Stopping the application file that is being executed A ... Specifying the write protect of the image file B ... Specifying the write protect of the application file Change T ... Transferred from the image processing unit of the application file and displayed on the text buffer. Next, the types of character string commands will be described.

"APC transfer" ... Transfers the processing information of the application buffer in the area 7-3 of the CRT 7 to the image processing unit 5 and stores it.

"TEX transfer" ... Image processing unit 5 displays the contents of the text buffer.
Transfer to.

"EDIT" ... Move the cursor on CRT7 to the application buffer in area 7-3.

"EXIT" ... "EDIT", "TRACE", "POSITINO", "SIZ"
Release of "E".

“TRACE”… Displays the contents of the application file on the CRT7.

“ENTER”… Transfers the contents of the text buffer to the application buffer.

“DELETE”… Deletes the character on the cursor.

“CLR LINE”… Clear area 7-3 of CRT7.

"←" ... Move the cursor one position to the left.

"→" ... Move the cursor one position to the right.

"Clear screen" ... Clear areas 7-1 and 7-2 of CRT7.

"POSITION" ... Position input specification.

“SIZE”… Specify the size input.

"CR" ... Carriage return.

An example of image processing using the above parameters, the one-character command and the character string command will be described with reference to FIG. This image processing extracts the image information of the area n1 of the first original document shown by 9 and the area n2 of the second original document shown by b,
The list is created by rearranging as shown by C.
(The file name of the application file programmed with this image processing is 01.) The procedure for creating the application file will be described below.

The first document a is placed on the sheet placement position 6-2 of the digitizer 6.
Place on.

Instruct "0" and "1". ... The application file name is 01.

Instruct "R". The original is read and stored in the page memory 2.

“S” “(” “0” “1” is designated .... The image information of the n1 area extracted from the original a is stored in the disk memory 4 as the image file of the file name 01.

")" ... Parameter input for image file 01 completed.

The original a is removed from the paper placing position 6-2 of the digitizer 6 and the original b is placed.

“R” ... The original is read and stored in the page memory 2.

“S” “(” “0” “2” ... Image information of the n2 area extracted from the document b is stored in the disk memory 4 as an image file of the file name 02.

")" ... Parameter input for image file 02 is complete.

The document b is removed from the paper loading position 6-2 of the digitizer 6 and the recording material C is loaded.

“L” “(” “0” “3” ... Image file of file name 03 (content is 0) is stored in page memory 2.

“” “)” ... Stores the image information of the file name 03 in place of the image information already stored in the page memory 2.

"L""(""0""1" ... Load the image file with file name 01 into page memory 2.

“” ... Overlaid on the image information already stored in the page memory 2.

")" ... Parameter input completed.

"L""(""0""2" ... Load the image file of file name 02 into page memory 2.

“0” ... Overlaid on the image information already stored in the page memory 2.

")" ... Parameter input completed.

"P""(""5"")" ... Set the number of prints to 5.

"APC transfer" ... Transfers the application file formed as described above to the image processing unit 5. Stored in disk memory 4.

The above processing information is formed by pointing the digitizer 6 with the stylus pen 8. That is, it is possible to input on the same digitizer 6 the instruction for extracting a desired image and the position for image composition and the command information for reading the image and performing the image processing. Therefore, the image processing information can be easily formed by the same means. Further, the application file formed as above, that is, the image processing information is displayed on the application buffer 7-3 of the CRT 7. This is shown in FIG. At the position indicated by the rectangle in FIG. 7, the coordinate information input by indicating the sheet placement position 6-2 on the digitizer 6 with the stylus pen 8 is a three-digit number in each of the X and Y directions. It is displayed in (unit mm). For example, the point A of the document a in FIG. 6 is at the position of X coordinate 98 mm and Y coordinate 63 mm, and the point B is
If the distance from the coordinates is 23 mm in the X direction and 54 mm in the Y direction, then 1 in FIG.
The line becomes 01 RS (01098063023054) RS ....

Here, the operation of the apparatus by the application file with the file name 01 is summarized as follows.

First, the first original shown in FIG. 6A is read by the reader unit 1 and stored in the page memory 2, and the image information n1 from the stored image information has a file name 01 in the disk memory 4. To store. Next, the second document shown in FIG. 6B is read by the reader unit 1 and stored in the page memory 2, and the image information n2 is stored in the page memory 2 and the file name 02 is stored in the disk memory 4. To store. After that, the image file with the file name 03 is transferred from the disk memory 4 to the page memory 2 (the image file with the file name 03 is a self-portrait in the image processing example described above,
By transferring this image file to the page memory 2, the page memory 2 is completely cleared. ),
The image file of file name 01 is displayed in m1 of page memory 2.
The image file with the file name 02 is transferred to the area and stored in the m2 area of the page memory 2. As a result, one page of image information in which the image information n1 and n2 are arranged as shown in FIG. 6C is formed in the page memory 2. Then, all the contents in the page memory 2 are output to the printer unit 3,
The printer unit 3 records on five recording materials. Also, the application file for the above image processing is stored and registered in the disk memory 4 with the file name 01 by the "APC transfer" finally instructed by the digitizer 6.

When the image processing apparatus is actually driven by using the processing information (application file) stored in the disk memory 4 as described above, the drive start command is provided in the image processing unit 10 shown in FIG. 1-2. It is input from the operating unit 13 that is operating. FIG. 8 shows a detailed view of the operation unit 13. 13-1 is a two-digit display for displaying the application file number, 13-2 is a display for displaying the desired number of sheets to be printed by the printer unit 3, 13-3 is a keyboard for setting numerical values, and the file name is shown. And used to set the desired number of prints. 13-4 is an enter key for inputting a numerical value set on the keyboard 13-3, 13-5 is an exit key for starting the image processing, and 13-6 is a stop key for interrupting the image processing being executed. When the stop key 13-6 is pressed, the work in progress at that time is completed, and then the apparatus is put into the standby state. 13-7 to 13-12 are a group of lamps for displaying the device status of the image processing unit 10.
A lamp 7 indicates that the application file having the file name input from the keyboard 13-3 and displayed on the display 13-1 is not registered in the disk memory 4.
A lamp 13-8 indicates a paper jam in the recording material supply system of the printer unit 3. Reference numeral 13-9 is a lamp that indicates the occurrence of a paper jam of the document in the automatic document feeder that automatically conveys the document to the reader unit 1 and discharges it after reading, 13-10 is a printer A lamp indicating that the recording material in the section 3 is exhausted, a reference numeral 13-11 is a lamp indicating a supply time of the phenomenon agent in the printer section 3, a reference numeral 13-12 is a lamp indicating that the apparatus is not in the standby state, Out of which lamp 13
If five or more lamps other than -11 are lit,
The reader unit 1 and the printer unit 3 do not operate. If one or more of the above five lamps are lit during the operation of the device, the device is stopped after completing the operation at that time.

Next, an operation example of performing image processing based on the application file stored as described above and stored in the disk memory 4 will be described. Incidentally, as an example, there is a case where the image processing of the application file having the file name 23 is performed to obtain five prints. Since the processing information regarding the image processing is stored in the disk memory 4 as an application file, in this case, the application file with the file name 23 is called from the disk memory 4 and transferred to the CPU circuit block sequence RAM of the image processing unit. Further, it is only necessary to set the desired number of prints 5 and set the document on the reader unit 1. In addition, this device is designed to give a user a key input procedure from the device side. In other words, when inputting the file name of the application file, the application name display 13
When -1 blinks and the number of prints is input, the print number display 13-2 blinks, prompting the user to input. The situation will be described below.

1. The display 13-1 showing the application file name is blinking "00".

2. The user presses the file name “2” or “3” on the keyboard 13-3.

3. Display 13-1 blinks "23".

4. The user presses the “ENTER” key 13-4.

5. The display 13-1 stops blinking and displays "23", and at the same time, the print number display 13-2 blinks with "00" displayed.

6. The user presses the number of prints “5” on the keyboard 13-3.

7. Display 13-2 blinks "5".

8. The user presses the “ENTER” key 13-4.

9. Display 13-2 stops blinking and displays "05".

10. Press the “EXCUT” key 13-5.

11. The device starts operating.

When image processing is performed using the application file already stored in the disk memory 4 as described above,
The image processing can be performed without the need of the image processing information forming unit constituted by the digitizer 6 and the CRT 7.

FIG. 9 shows a block diagram of the circuit of this embodiment.

1 is a reader unit, 3 is a printer unit, 6 is a digitizer, and 7 is
The CRT 12 is an image processing controller having the page memory 2, the disk memory 4, the image processor 5, and the DMA controller 9 shown in FIG.

A multi-bus 12-10 is provided in the image processing controller 12. Multibus 12-10 is generally a standard bus. A circuit block that can obtain the right to use the multibus 12-10 and control other circuit blocks is called a master function block, and a circuit block that is not so called a slave function block. Therefore, four circuit blocks connected to the multi-bus 12-10, that is, a CPU circuit block 12-10, a DMA controller 9, a page memory circuit block 12-3 having a semiconductor buffer memory, a reader & printer sequence controller 12-4. Of these, the CPU 12-1 and the DMA controller 9 are master function blocks, and the page memory circuit block 12-3
The reader & printer sequence controller 12-4 is a slave function block. The four circuit blocks are connected to the multibus 12-10 by multibus lines 12-12, 12-13, 12-14, 12-15, respectively.

12-16 to 12-20 are DMA controller 9, reader & printer sequence controller 12-4, dither controller 12
-9, shift memory 12-5, page memory circuit block
This is an interrupt line input from 12-3 to the CPU circuit block 12-1. Image signal lines 12-21 and 12-22 transfer image information photoelectrically converted by the two line sensors CCD1 and CCD2 of the reader unit 1. Reference numeral 12-13 is a line from which the information regarding the dither of the image quality processing is output from the dither controller 12-9. 12-24 and 12-25 are line sensor CC
The image information obtained from D1, 2 is A / D converted according to a predetermined threshold when edge emphasis is specified, and is A / D converted by the signal from dither controller 12-19 when halftone is specified. Transfer of image information that has undergone image quality processing,
This is a line for transferring control information relating to these image quality processes. Reference numeral 12-26 is a line for transferring the image signal of one scanning line obtained by the parallel image signals of the lines 12-24 and 12-25 to the page memory circuit block 12-3, and also includes the control information thereof. . Reference numeral 12-27 is a refresh trigger signal line for the dynamic memory, which is the page memory 2 in the page memory circuit block 12-3 by the CPU 12-1. 12-28 are the selection signal lines of the page memory 2 since the page memory 2 has two banks. 12-29
Is the shift memory 12-5 to the page memory circuit block 12
3 is a period signal line indicating a period during which image information is input to -3 and a period during which image information is output. Reference numeral 12-30 is a line for outputting one serial image information from the page memory circuit block 12-3 to the printer section 3. Reference numeral 12-31 designates a video blank signal for causing the laser of the printer unit 3 to emit light in the non-image area in the case of the background ground scan, and a signal line for forcing the laser to emit in order to obtain the horizontal synchronizing signal. Reference numeral 12-32 is a signal line for determining the coordinate information for designating the area to be halftoned on the original and the type of design by the dither controller 12-9. 12-23
Is a line for transferring the coordinate information on the digitizer 7 to the CPU 12-1, and the file information in the disk memory 4 is sent from the CPU 13-1 to the CRT & digitizer controller 12-8 via this line. 12-34 is a line to which the coordinate information from the digitizer 6 is input.

12-35 is a video signal line output from the CRT & digitizer controller 12-8. Reference numeral 12-36 is a line of an input signal to be processed and a processed signal by a processor in the reader & printer sequence controller 12-4. The interface 12-6 converts the output signals of various sensors provided in the reader unit 1 and the printer unit 3 into a form that can be input to the reader & printer sequence controller 12-4, and drives the motor, heater, laser, etc. To output a signal. Reference numeral 12-37 is a signal line for driving the optical system scanning motor of the reader unit 1, and 12-38 is a sensor signal line in the reader 1. Reference numeral 12-39 is a line for interacting with the user via the operation unit 13. 12-40 is a line for detecting the rotation of the scanner of the printer unit 3, 12-41 is a line for detecting the temperature of the laser for stabilizing the laser, 12-42 is a signal for driving the printer unit 3 and various sensors Signal line. The page memory circuit block 12-3 has two lines that are not connected to the multibus 12-10, that is, lines 12-26 for inputting serial image information from the reader unit 1.
Line 12 that outputs serial image information to printer unit 2
-30 and a line 12-14 connected to the multibus 12-10 are provided as image information transfer lines. As a result, even though the image information is being input from the reader unit 1 and being output to the printer unit 3, the CPU 2− connected to the multi-bus 12−10
1 is capable of performing operations related to image processing.

As described above, when performing image processing, prior to actual driving of the image processing apparatus, processing information relating to image processing, that is, designation of an image processing area of a document, instruction of image processing content, printout area Formed by pointing the digitizer 6 with the stylus pen 8 while interacting with the CRT 7 to specify the file name of the image information to be stored in the image processing unit, and to specify the file name of the set of image processing information. Will be done. Therefore, an image processing apparatus that can easily perform image processing in that simple operations do not require complicated operations and that information related to image extraction position designation and image processing can be formed by a common means. provide. Further, since a page memory including a semiconductor dynamic memory is provided for storing one page of image information which is read by the line sensor of the reader unit 1 and continuously output, the reader unit 1 outputs the page information. When inputting the image information to the storage means, it can be directly input without using a synchronizing means such as an intermediate buffer.

The same applies to the case of outputting to the printer unit 3, and the image information can be read into and read from the memory means at high speed.

The details of the CRT & digitizer controller circuit block 12-8 shown in FIG. 9 are shown in FIG. For this block, APPLE II from Apple is used, and Fig. 10 shows APLL I.
The circuit diagram of I is shown. Therefore APPLE for details
See II Manual.

Details of the CPU circuit block 12-1 shown in FIG.
Shown in the figure. This block uses Intel's single board computer SBC86 / 12, and Fig. 11 shows SBC8.
6/12 circuit diagram is shown. Therefore SB for details
See the C86 / 12 manual. The control of this circuit is CP
It is performed mainly on U8086, and this program is stored in advance ROM. Further, as described above, the interrupt signal from each block of the image processing control unit 12 is input to the interrupt controller through the interrupt lines 12-16 to 12-20. By determining these interrupt signals, central control of blocks of each part is performed.

The details of the reader & printer sequence controller circuit block 12-4 shown in FIG. 9 are shown in FIG. This block has Intel's single board computer SB
It uses C569, and Fig. 12 shows the circuit diagram of SBC569. Therefore, see the SBC569 Manual for more information. As mentioned above, this circuit is a CPU circuit block 12-
Interrupt 1 to interrupt line 12-17. Also CP
The interrupt from the U circuit block 12-1 to this circuit is caused by the addressing of the CPU circuit block 12-1.

Details of the DMA controller circuit block 9 shown in FIG. 9 are shown in FIG. 9-1 is an Intel processor with built-in DMA function, Intel 8089, which is the main function of this circuit block. See the 8089 manual for details on the device itself. 9-2 is a bus arbiter 8289 and multibus 12 according to the status information from the IO processor 9-1.
It has a function of acquiring the right to use the multibus 12-13 by connecting it with -13 and releasing the multibus 12-13 after use. See the Intel 8289 manual for detailed features. 9-3 is a bus controller 8288 which outputs or inputs address and data signals to the multi-bus 12-13 after acquiring the right to use the multi-bus 12-13 by the bus arbiter 9-2, and a memory line command MWTC and a memory read. Output the command. In other words, multibus 12-13
The master function for the block is the bus arbiter 9-
By having 2 and the bus controller 9-3, it is possible to access the multi-bus 12-13. Therefore, the slave function block does not have these two devices and is unilaterally accessed by the multibus 12-13. For details of the bus controller 9-3 itself, refer to the Intel 8288 manual. Reference numeral 9-4 is a clock generator 8284 which uses an external oscillator as an input means and supplies a clock signal of a predetermined frequency to the IO processor 9-1, the bus arbiter 9-2 and the bus controller 9-3, and
For the IO processor 9-1, the peripheral circuit performs a memory OR as the judgment information of whether the bus cycle enters the wait state and the judgment information of the release of the wait state.
It has a function of receiving an I / O acknowledge (response to write or read from memory or I / O) signal and outputting a ready signal in accordance therewith. See Intel 8284 for details
See the manual. 9-5 is an internal bus in this circuit block, which is a local bus for the multi-bus 12-13. As for the bus structure, the address bus is 16 bits and has an address space of 64 KBYTE, and the data bus is 8 bits. 9-6 is the address / data buffer,
This block consists of two address / data buffers, one for the multibus 12-13 and the other for the internal bus 9-5. This buffer 9-
As the basic function of 6, the address and data information output from the IO processor 9-1 is multiplexed and time-divided and output on the same line, that is, the address information and then the data information are output first. First, the address information is latched in the address buffer,
Then, depending on whether the next data information is a read command or a write command, this data is switched between transfer and read. Therefore, regarding the former buffer, since the address information is already output from the IO processor 9-1 to the address / data line at the timing when the address latch enable ALE signal is output from the bus controller 9-3, The address information is latched in the address buffer by the signal.

After that, the bus arbiter 9-
If already acquired by 2, the bus arbiter 9-2 outputs an address enable AEN signal, and this signal causes the address buffer to output the latched address information to the multibus.
Output to 12-13. If this is for a write command, the IO processor 9-1 outputs the address information on the address / data line, and then outputs the data information if the multibus 12-13 has been acquired at that time. Along with this, the bus controller 9-3 outputs the data enable DEN signal, and outputs the data information together with the address information to the multi-bus 12-13 via the data buffer. The transmission or read switching signal at this time is output as a DT / R signal from the bus controller 9-3, and accordingly, the data information is transferred to the multi-bus 12-13. Bus controller 9 for read command
-3 does not output the DEN signal, and the data buffer puts the DT / R signal in the read mode to put the data information on the multi-bus 12-13 on the address / data line of the IO processor 9-1. Reading this data by the IO processor 9-1
Transfer acknowledge XACK from accessed memory
It is designed to be performed after checking the signal. For the address / data buffer for the internal bus 9-5,
The timing of address latching is the same as in the above case. That is, both the address buffer for the multi-bus 12-13 and the address buffer for the internal bus 9-5 are equally latched regardless of which bus is used to access the address information output from the IO processor 9-1. To do. However, the signal indicating whether or not to output only in the case of the multi-bus 12-13 is performed by the AEN signal from the bus arbiter 9-2. Next, whether or not to output the data buffer for the internal bus is determined by the peripheral data enable PDEN signal of the bus controller 9-3, and the direction switching between the transmit and the read is performed for the multibus 12-13. Bus controller 9-3 as well as data buffer
It is performed according to the mode of the DT / R signal of. Reference numeral 9-7 is a synchronizing signal generating circuit, which is used when the IO processor 9-1 accesses peripheral units (memory, I / O, etc.) in this block and confirms the response from these units.
Processor 9-1 is set to enter the next operation,
The clock generator 9-4 operates in such a manner that these response signals are synchronized with the bus cycle of the IO processor 9-1.
It is sent as a ready signal to the processor 9-1. 9-
Reference numeral 8 is a ROM, which has two 2716 devices. Therefore, it has a capacity of 4KBYTES and IO processor 9-1.
It is a memory for storing the micro program of 9-9
Is a normal I / O port and uses two 8212 devices. The purpose is to control peripheral devices, but in this embodiment, nothing is controlled and the device is open. An address decoder 9-10 decodes a part of the address information (upper number bits) of the internal bus 9-5 in order to generate a chip selection signal for the ROM 9-8 and the I / O board 9-9.
A disk memory 9-11 is a hard disk unit having a storage capacity of 10 MBYTE, a structure of 350 tracks, one track of 18 sectors, and one sector of 512 BYTE. It has a disk controller circuit inside and is designed to interface with an 8-bit data bus. The model name is WDS-10. For details, see the manual of WDS-10 of Sword Computer. Reference numeral 9-12 is a dedress / data line of the IO processor 9-1, which outputs address information and data information on the same line in a time division manner. In the output order, the address is first and the data is first. Line 9-13
Are signal lines for address information and data information to be output to the internal bus 9-5. Reference numeral 9-14 is a signal line for address information and data information output to the multi-bus 12-13. 9
-15 is a signal line for status information output from the IO processor 9-1 to the bus arbiter 9-2 and the bus controller 9-3. Reference numeral 9-16 is a channel attention CA signal which is a DMA request signal from the CPU 12-1, and a system interrupt SINTR signal for notifying the completion of DMA from the IO processor 9-1 to the CPU 12-1. This SINTR signal is CPU1
Input to the 2-1 interrupt terminal. Line 9-17 is an address latch enable ALE signal, a peripheral data enable PDEN signal, a data enable which the bus controller 9-3 outputs to the address / data buffer 9-6 based on the status information from the IO processor 9-1. Bull DEN signal and data transmit / read DT / R signal. The line 9-18 acquires the right to use the multibus 12-13 according to the status signal of the bus arbiter 9-2 or the IO processor 9-1, and then multiplies the address information already latched to the address / data buffer 9-6. It is an address enable AEN signal which is a signal output to the bus 12-13. The line 9-19 is a signal line for requesting and granting the right to use the multibus 12-13. That is, multibus
The priority of the bus use right is determined in advance for the master function circuit block connected to 12-13.
1 is the highest and the second is the DMA controller 9. First, the bus arbiter 9-2 is a multibus 12-
High priority when bus request BREQ signal is issued to 13
If the CPU 12-1 is not using the multi-bus 12-13, a reply indicating that it is available as the bus priority in BPRN signal comes. When the bus arbiter 9-2 confirms this, it outputs a busy signal to inform that the bus is in use. Line 9-20 is multibus 12-
When accessing external memory or I / O degree through 13,
Transfer acknowledgment XA which is the response signal from them.
This is the CK signal line. Line 9-21 is IO processor 9-
When accessing the memory from 1, when the byte information at the odd address is accessed by the byte high enable BHEN signal that is output together with the address information (data is output to the upper byte of the data bus), the even address is addressed. And 16-bit word information is accessed (byte data at an even address is in the lower byte of the data bus, byte data at an odd address is in the upper byte of the data bus) and an even bank by the signal output. This is to use as a switching signal which bank is to be accessed in a memory having a structure divided into odd-numbered banks. A line 9-22 is a clock signal, and a line 9-23 is a power-on reset and a manual reset. The line 9-24 is a ready signal synchronized with the bus cycle of the IO processor 9-1. Line 9-25 is an emory write command MW that outputs together with address information and data information when accessing multibus 12-13.
TC signal and memory read command MRDC signal. The line 9-26 is the ALE signal from the bus controller 9-3 and the signal of S2 which is one of the status information. As described above, the address information of the S2 signal is latched to the multi-bus address buffer and the internal bus address buffer at the same time regardless of which buffer is accessed. It is necessary to judge whether or not the content latched in the far is the address information for the internal bus. Therefore, the judgment is made in the address decoder 9-10 based on the S2 signal. That is, the S2 signal is this identification information, and when S2 = 1, the multi-bus 12-13, S2 =
0 indicates the internal bus 9-5, and this signal is latched and held by the ALE signal.

Line 9-27 is an I / O read command IORC signal output from the bus controller 9-3 and a microprogram from the ROM 9-8 when the IO processor 9-1 accesses data in the read mode on the internal bus 9-5. These are the interrupt acknowledge INTA signal and the ALE signal output from the bus controller 9-3 at the time of switching. In the synchronizing signal generating circuit 9-7, when the IO processor 9-1 accesses the internal bus 9-5 by the IORC signal and the INTA signal, a signal for identifying the read mode is produced. The ALE signal is used for the clock in the synchronizing signal generating circuit 9-7. The line 9-28 is a data bus, and the command information, the result information, and the data information of the information to be loaded on this are one address, and the other one address is the status information. The former three pieces of information are distinguished by the disk unit 9-11 by being input / output sequentially.

Lines 9-29 are the above two address information lines. A command busy CBUSY signal which is an identification signal for the above two addresses is provided on a line 9-30. It should be noted that the signal on line 9-30 and the signal on line 9-
The reason for inputting the signal of 27 is 1 of command information, result information and data information in the disk unit 9-11.
The read mode and the write mode for the information of the set have different timings of data ready, and the read mode and the write mode for status information also have the different timing of the ready, so that the wait time given to the IO processor 9-1 is changed. This is because it is necessary to create four types. Line 9-31 is the ready signal described above. Line 9-32 is a disk unit 9-
11 is a data request indicating the ready status DREQ signal and DMA
External terminated EXT signal indicating completion. Line 9-33 is the data bus line (8 bits) of I / O port 9-9. Line 9-34 is ROM9-8 and I / O
The upper bit of the address information for producing the chip selection signal of the above is carried, and the line 9-35 is the address information indicating the specific address in the ROM 9-8, and the lower bits other than the above are carried.
Line 9-36 is a data signal line of the instruction code fetched from ROM 9-8 and is output on the data bus.

Line 9-37 is the chip select signal for I / O port 9-9,
Line 9-38 is the ROM9-8 chip select signal.

Based on the above description, the flow of information during DMA in FIG. 13 will be described.

The CPU 12-1 passes the line 9-16 to the IO processor 9
Add the channel attendance to -1.

IO processor 9-1 is line 9-12, line 9-14
Through the dual port R in the CPU circuit block 12-1
Access AM to get mode and address information for DMA.

IO processor 9-11 is line 9-12, line 9-14
The page memory 2 is accessed via.

Multibus 12-13 read from page memory 2
The above 16-bit data is multi-bus 12-13, line 9-14,
It is taken into the IO processor 9-1 via the line 9-12.

The IO processor 9-1 outputs the upper 8 bits of the 16-bit data to the line 9-12, line 9-13, internal bus 9-5,
Take it into the disk unit 9-11 via line 9-28.

Next, the lower 8 bits are taken into the disk unit 9-11 by the same route as.

The above steps are repeated until the EXT signal appears on the line 9-32.

The SINR signal on line 9-16 interrupts the CPU 12-1 to terminate the DMA.

In this way, the image information is DMA-transferred between the page memory 2 and the disk memory 4 (disk unit 9-11). Further, the DMA controller 9 for controlling this DMA has a master function capable of controlling the multi-bus 12-10, and by this master function, the page memory 2 in the page memory circuit block 12-3 which is a slave function circuit block is controlled. Can be accessed. Therefore, the CPU 12-1 can execute other operations necessary for image processing during the transfer of the image information.

Furthermore, there are two circuit blocks with master function, namely
The CPU 12-1 and the DMA controller 9 are given priority to the CPU 12-1 with respect to the use of the multibus 12-10. As a result, the DMA controller 9 becomes a multibus 12-10.
If the CPU 12-1 does not complete the image processing and the preprocessing using the multi-bus 12-10 related to the operation of each unit even if the DMA transfer is requested using the DMA transfer, the DMA transfer is prohibited. Therefore, it is possible to prevent contention due to signals from a plurality of blocks on the multi-bus line 12-10.

Memory Space of Multibus A memory map in four circuit blocks related to the multibus 12-10 will be described below. CPU circuit block 12-
1 has a 32KB YTE dual-port RAM and an 8KBYTE ROM as a program memory for the CPU 8086. The page memory circuit block 2 has a memory capacity when reading an A4 size image at 12 pel / mm, that is, a capacity of 8,709,120 bits (12
It has a memory of 725.760words, where each bit is 1word.
Reader & Printer Sequence Controller Circuit Block
The 12-4 has dual port RAM with a capacity of 2KBYTE. These are all memory mapped memories and are accessed from the multi-bus 12-13 by a memory write command MWTC signal and a memory read command MRDD signal.
In addition, there is a ROM, which is a program memory for the 4KBYTE CPU8085, on the internal bus of the reader & printer sequence controller circuit block 12-4, and this is also a memory mapped memory that is accessed by the read RD signal of the CPU8085. Since -13 is a slave function, the address from this CPU8085 is never output.

Also, in the DAM controller circuit block 9, a 4KBYTE ROM which is a program memory of the IO processor 9-1 is provided on the internal bus 9-5. Since this memory is an I / O mapped memory, this ROM is IO processor 9-
Even if 1 accesses, the address is multibus 12-13
There is no going up and you cannot access this memory from the Multibus 12-13.

FIG. 14 shows a memory map related to the multibus 12-13.
The address space of the multi-bus 12-13 is a memory mapped memory space, one address per 1 BYTE of data, 000
There is 1MBYTE from 00 to FFFFF. F as the allocation of this space
8KBYTE from E000 to FFFFF in the CPU circuit block 12-1
Program memory space for 8086. Page memory 2
There is 725.760 WORDS as mentioned above, and if you convert it to BYTE unit, 1,
It is 451,520 BYTE, and the buffer memory space will exceed the memory space of 1MBYTE. Therefore, the buffer memory space is divided into two banks, and each address space is 72
As the 5.760 address, banks are switched by hardware with a signal from the CPU 12-1 (line 12-28 in FIG. 9).
The space of bank 0 is 0A000 to BB2FF, and the space of bank 1 is 0B300 to BC5FF. 2KBYTE's dual port RAM in the reader & printer sequence controller circuit block 12-4 is mainly used as the CPU8085 in the block.
In the communication with the CPU 8086 in the CPU block 12-1, 08000 to 087FF is allocated as its address space. CPU808
As the address space where 5 accesses the dual port RAM, since this RAM has only 64KBYTE space, the same address 08000 to 087FF is given.

Next, 8KBYTE of the 32KBYTE dual port RAM in the CPU circuit block 12-1 is connected to the CPU8086 and DM in this block.
Used for communication with the CPU 8089 in the A controller circuit block 9, and assigns 06000 to 07FFF as its address space. On the other hand, the address when the CPU 8089 accesses this space, that is, this address viewed from the CPU 8089 is different, and is FF800 to FFFFF. That is 0600
0 corresponds to FF800 and 07FFF corresponds to FFFFF. Therefore, FF800 to FFFF in the CPU circuit block 12-1.
When the address of F is entered, this address code is converted by hardware so that it will be 06000 to 07FFF via ROM. 00000 to 05FFF is allocated as the address space of the 24KB YTE dual port RAM other than the above.

The above is the memory space related to the multibus 12-10. However, the reader & printer sequence controller circuit block 12
The address space of the 4KBYTE ROM in -4 is 00000 to 00FFF as the memory mapped memory, and the address space of the 4KBYTE ROM in the DMA controller circuit block 9 is 00000 to 00FFF as the I / O mapped memory.

[Structure of page memory]

FIG. 15-1 shows an address map of the page memory 2 in the page memory circuit 12-3. This page memory 2 has the ability to store information obtained by resolving A4 size (288 mm x 210 mm) into 12 pixels per 1 mm. The direction of main scanning of this original by the reader unit 1 is 288 mm in the lengthwise direction, which is decomposed into 12 pixels per 1 mm and comes in from the CCD, so that 3,456-bit pixels are inputted in one scanning. The width of the sub-scan is 210 mm.
Therefore, since 12 lines are scanned per 1 mm, the scanning of A5 is 2520 lines in total. Therefore, the memory size is 8,709,120.
I have a bit. 3456 bit pixels are serially input 2520 times for each A4 size original.

How the image information input in this way is assigned and stored will be described. First, the manuscript is divided into 1 mm × 1 mm square unit blocks, and this unit block is used as one memory block, and an A4 original is composed of 60,480 blocks. In other words, this memory block has 12 bits of 12 lines, that is, 144 bits of image information. 1 word for 12 bits
If one address is given as, the memory block is composed of pixel groups having 12 addresses. Therefore, the total memory space has 725,760 addresses and addresses 0 to 725,759, HE
The XA code makes the address space from 00000 to B12FF. Therefore, 3456-bit serial image information for one line is divided into 12-bit pixel groups each corresponding to a length of 1 mm and extracted. The first pixel group is stored at address 00000, and the next 12-pixel group is stored.
Bit pixel group to 0000C, then 00018,00024 ...
The last 12-bit image group of the first line is stored at address 00D74. That is, the image information obtained by scanning one line is divided into pixel groups of 12 bits each and sequentially stored in jump addresses of 12 addresses. Next, when serial image information of 3456 bits for the second line is input, it is divided into 12 bits in the same manner as the first line, and each pixel group is stored from address 00001 to 12 every 00D75. Width 1mm
Addresses where the image information for a length of 288 mm is continuous, that is, 00000 to 00
It is stored at address D7F.

Then, the image information of 3456 bits on the 13th line is similarly divided and stored every 12th address from 00D80. The data is stored in this way, and the last 12 bits of the 2520th line are stored at the address B12FF.

1m when using the method of storing with the above address
The entire A4 area will be stored in consecutive addresses in units of m × 1 mm squares. This allows the digitizer 4 to specify the image processing area in mm, so when transferring the specified area to the disk memory 4, DMA transfer is used.
Just by setting the start address and the end address, you can transfer at high speed without going through the CPU.

That is, by designating one set of the start address and the end address, the image information for 12 main scanning lines is DMA-transferred. That is, image information of 1 mm width is extracted by designating the start address and the end address once. Therefore, the address setting at the time of DMA transfer is small, and the transfer speed can be increased. This is more effective when extracting image information. To extract an image, addresses are continuous from the right side to the left side of the extracted image. For example, when extracting the image information with a vertical length of 20 mm, the address setting by the CPU is 20 times. .

Further, since the address corresponds to the image in mm unit, the address can be set in mm unit, which is convenient for the user. In addition, this embodiment has 12
Since a line sensor with bit reading capability was used, 12
Although one address corresponds to one bit, the number of bits may be another value depending on the capability of the line sensor, and the same effect can be obtained by setting the address in units other than mm, such as inch. The initial address of each line to the page memory 2 is obtained by the CPU setting the initial value in the address counter. Also, when the image information is output from the page memory 2 to the laser beam printer 3, it is read out every 12th address from the initial address as in the case of inputting.

An example of extracting information of a desired area from the page memory 2 and performing DMA transfer to the disk memory 4 will be described with reference to FIG. 15-2.

As described above, the image information is transferred between the page memory 2 and the disk memory 4 by the DMA transfer. The image processing unit 5 uses the DAM controller 9 when the need for DMA transfer arises.
Send a DMA request signal to. The DMA controller 9 receives this and issues a hold command to the image processing unit 5. The hold command causes the control unit 5 to be in a state in which it is apparently disconnected from the multibus.

Based on the processing information formed by the digitizer 6, the DMA controller 9 uses the image processing unit 5 to perform image processing according to the set start address and end address on the page memory without using the image processing unit 5. Initiate the transfer of information. In other words, for image information having continuous addresses, the image processing unit 5 specifies the start address and the final address only once before the DMA transfer, so that the information between the addresses can be transferred at high speed without passing through the image processing unit 5. Transferred to. Here, page memory 2
When the necessary image information is transferred from the disk to the disk memory 4, if the storage method according to the memory map as shown in FIG. 15-1 according to the present invention is used, the start address and the end address are transferred for the DMA transfer. 12 lines in the main scanning direction of the line sensor, that is, 1 mm
An image signal corresponding to the width image information is DMA-transferred from the page memory 2 to the disk memory 4. That is, the structure of the address map in the page memory 2 is composed of 12 consecutive addresses for each unit block of a 1 mm × 1 mm square of the document (for example, 00000 to 0000B), and the first address of the adjacent block in the main scanning direction is Last address of previous block (eg 0000
Since the address is next to that of B) (for example, 0000C), reading from the page memory 2 is sequentially performed for each pixel group in block units.

That is, the image information for 12 lines has the first address and the last address as 1
It will be output by instructing once.

FIG. 15-2 is a part of the address map of the page memory of FIG. 15-1. An example of DMA transfer of the image information stored at the address in the shaded area in FIG. 15-2 will be described. When the _first address is X ₁ , X ₂ , X ₃ , X ₄ and the last address is Y ₁ , Y ₂ , Y ₃ , Y ₄ , the image processing unit 5 sets X ₁ and
When Y ₁ is set, the unit block starting from address X ₁ is read out, and then the next unit block is read out. At the address Y ₁ , the first DMA transfer ends, and the control unit 5 returns to the second address. When X ₂ and Y ₂ are set in the setting, the unit block starting from the X ₂ address is read out, then the next unit block is read out, the second DMA transfer ends at the Y ₂ address, and so on. 15th by setting X ₃ , Y ₃ for the 4th time and setting X ₄ , Y _{4 for} the 4th time
The image information stored at the address in the shaded area in FIG. 2 is DMA transferred. In this way, the image information for 12 lines is read by setting the address once.

Therefore, according to the storage method by the address map of the present invention, the DMA transfer can be performed at a high speed, and thus the image processing time can be shortened.

Next, the DMA transfer from the disk memory 4 to the page memory 2 will be described. In this case as well, similar to the case of the DMA transfer described above, 12 lines are performed by one address instruction, but the extracted image information is When outputting to the same position as the original, the address given when input from the reader unit 1 to the page memory 2 may be used, but when moving the extracted image information to a different position, it corresponds to the moving position. The page memory 2 must be converted into an address on the address map. For this address conversion, an address converter is provided in the page memory 2.
The image signal output from the disk memory 4 is converted into a necessary address on the memory map by this address converter, and is stored in the page memory 2 in units of 1 mm × 1 mm square blocks as described above.

In this way, the image information extracted from the original is stored in the page memory 2, and then this image information is transferred to the printer unit 3. In this case, the operation opposite to the address assignment when the image information is sent from the reader unit 1 to the page memory 2 is performed. That is, the image signal for each 12th address is read from the page memory 2 by the address counter and serially output through the 12-bit parallel-in serial-out shift register. As a result, a serial one-line image signal is input to the printer, and a copy is obtained based on this image information.

Further, since the original is stored in the page memory 2 as a square block of 1 mm × 1 mm, the image information of the extracted portion can be specified in mm units on the original.

In this embodiment, the number of pixels read by the licensor is set to 1 per 1 mm.
Although it is set to 2 bits, it is natural that this is not limited to this value. Also, even if the number of pixels per 1 mm increases, DMA transfer of 1 mm wide image information can be performed by setting a single address by giving a predetermined number of addresses for each 1 mm x 1 mm unit, as described above. Can be done. Further, in the present embodiment, the address map of the image memory is constituted by a square block of 1 mm × 1 mm, but the same effect can be obtained by using a unit block constitution other than this size.

FIG. 16 shows an address map when the page memory 2 is viewed from the multibus 12-10. The address space of 00000 to 5897F in FIG. 15 is bank 0, the address space of 58980 to B12FF is bank 1, and this space is OA000 to BB2FE, respectively.
And OB300 to BC5FE address space. Multibus 12-10 has a 16-bit data bus and a 20-bit address bus, but the area accessible by this bus is 1MBYTE.
It is said that. In other words, 1M pieces of 8-bit data can be accessed, and when accessing 16-bit data, since it reaches address 2, 16-bit data is input / output only when accessing even addresses in WORD mode. It For this reason, as is clear from FIG. 16, every other consecutive address is assigned. The real address in the page memory circuit block 12-3 is the address shown in FIG.
The page memory circuit block 2 has a circuit for converting this address into the address shown in FIG. By having this address conversion circuit, the address area of the page memory 2 can be set in an arbitrary address space.

The contents of page memory circuit block 12-3 in FIG.
Shown in the figure. As shown in the figure, this block is divided into five circuit units, a memory controller 2-1, a memory A2-2, a memory B2-3, a memory C2-4, and a terminator 2-5, all of which units are internal bus 26. Are connected with. The memory controller 2-1 is also connected to the multibus 12-14, and is accessed as a slave function from the multibus 12-14 as a whole of the page memory circuit block 12-3. Further, a bank switching signal is supplied from the CPU circuit block 12-1 via a line 12-28. Serial image information is input from the shift memory 12-5 via the line 12-26, and an image signal is output from the line 12-30 to the laser driver of the printer unit 3. Memories A, B, and C are 16K dynamic RAM, and their capacity is 256K with 12 bits as 1 word.
There are words. This memory has an IM1 made by NISSAN ELECTRONICS
Since it uses 440IMG, please refer to the IM1440IMG manual for details. An address signal line, a data signal line, a read signal line, a write signal line, a refresh signal line, a memory status signal line (MEMORYBUSY), and an acknowledge signal line are input to the internal bus 2-6. Multibus 1 for each of memories A, B, C in Table 1
2-14 represents an address accessed from 2-14 and an address on the internal bus converted in the memory controller 4-1.

FIG. 18 shows a circuit diagram of the memory controller 2-1 in the page memory circuit block 12-3. 2-1-1 and 2-
1-2 is a serial-in parallel-out 1.2-bit shift register. Reference numeral 2-1-3 is a 12-bit write data line, and image information of 3456 bits is transmitted per serial scanning line from the CCD on the line 2-1-4. 2-1-5 is a clock signal for serially inputting the selection signal of the register 2-1-1 and the image information of the line 2-1-4 by 12 bits, and the input 12 bits of information on the line 2-1-5. 3 is an output enable signal for parallel out to 3. 2-1-6 is a control signal for the register 2-1-2 having the same function as that of 2-1-5. 2-1-7 is a write timing generator, CCD
The register 2-1-1 is selected by using the write synchronizing signal (appearing at the head of the serial signal of each line) and the write clock accompanying the image information from the register, and the clock is given to it. As a result, the first 12 pages of image information input continuously for one page
The bit is input to the register 2-1-1. Then next
For the 12-bit image information, the register 2-1-2 is selected, the clock is also given, and this register is input. Further, at the time when this image information is input to the register 2-1-2, the image information already stored by applying the output enable signal to the register 2-1-1 is used to input the image information already stored in the memory input line 2-1. -3 to output.

That is, the write timing generator 2-1-7 parallel-mutes the contents of the register 2-1-2 while the data is serially in the register 2-1-1 and, conversely, the register 2-1-2. The timing signals 2-1-5 and 2-1-6 are generated so as to parallel-out the contents of the register 2-1-1 while the data is serially in.
As a result, one page of serial image information from the reader unit 1 can be parallel-out to the memory without interruption. Further, the address of the memory for storing the data must be output to the address bus line of the internal bus 2-6 at the timing of paralleling out the data from the register to the memory input data line 2-1-3. Therefore, the write timing generator 2-1
7 generates a clock pulse on the line 2-1-8 for counting up so that the value of the address counter 2-1-9 becomes the address value at the timing of parallel out. That is, as mentioned above, this address is 00000,0000C, 00
Since it will be a value every 12 counts like 018 ...
This clock pulse has two shift registers 2-1-1.
And 2-1-2 are alternately output while outputting 12 counts. Further, the write timing generator 2-1-7 is a memory input data line 2-1.
Internal bus at the timing when data is output on -3
Since it is necessary to output the memory write signal on the 26 control bus lines, the signal is output to the line 2-1-.
Raise to 10.

12-bit shift register for read data 2-1-11 and 2
Numeral -1-12 is a parallel-in / serial-out 12-bit shift register for parallel-in of 12-bit parallel image information read from the memory and serially outputting it to the line 2-1-14. Read timing generator 2-1-15
Is a memory output data line 2-1 while serially outputting the information stored in the register 2-1-12 based on the read horizontal synchronizing signal (beam detect signal in the laser beam printer) and the read clock. 12 bit shift register for reading the data on -13 2-1-11
Signal for parallel loading to register 2 and register 2
Waiting for the completion of the serial output of -1-12, the clock signal for shifting the loaded data and serially outputting it on the line 2-1-14 is output on the signal line 2-1-16.
Give to. Further, while the register 2-1-11 serially outputs the contents, the memory output data line 2-
Following the code signal for parallel loading the data on 1-13 into register 2-1-12 and the completion of serial out of register 2-1-11, this loaded data is shifted to line 2- Generate a clock signal on line 2-1-17 for serial out on 1-14.

In this case, in order to read data on the memory output data line 2-1-13, the address must be output on the address line of the internal bus 2-6. Therefore, a clock pulse is generated on the line 2-1-18 to count up so that the value of the address counter 2-1-9 and the value thereof before the data is outputted to the memory output data line 2-1-13. That is, as described above, 0000
0,0000C, 00018, ... The address to store the data is 12
This clock pulse has two shift registers 2-1-11 and 2-1 because it must be a value for each count.
It outputs so as to count up by 12 while inputting data alternately with -12. Further, the read timing generator 2-1-15 has to output the memory read signal on the control bus line of the internal bus 2-6 at the timing when the address is output, so that the signal is output on the line 2-1. Generate on -19. The address converter 2-1-20 is provided for converting a multi-bus address into an internal bus address as shown in Table 1, and is composed of a ROM. When the buffer memory 2 is accessed by the DMA controller 9 via the multi-bus 12-14 by the DMA controller 9, the address information thereof is given to the line 2-1-21 together with the bank switching signal. -1-
The reference numeral 20 outputs a selection signal to the line 2-1-22 which one of the memories A, B and C is to be selected by these signals, and the concretely converted address information in the line 2-1-22.
Output to 23. In addition, when accessing from the multi-bus 12-14, a memory write or read signal is given to the control bus line along with the address. Therefore, this signal is sent to the control bus line of the internal bus only when the buffer memory 2 is accessed. A signal for enabling to ride is output to the line 2-1-24. In this case, the data information of the multi-bus 12-14 is output through the line 2-1-25 at the same timing as the address information. That is, during memory write, the data information is put on the line 2-1-3 and output to the data bus line of the internal bus 2-6, and during memory read, the data on the data bus line of the internal bus 2-6 is transferred to the line 2-1. -13, and is input to the data bus line of multibus 12-14 via line 2-1-25.

As described above, when inputting serial image information from the CCD, 00000,00001,00002, ..., 0 for each line
An initial address such as 000B is preset by the CPU 12-1 to the address counter 2-1-9 via the multi-bus 12-14. The preset value is the data line 2-1-27
The signal which appears above via line 2-1-25 and whose address appears as line I / O mapped I / O appears on line 2-1-21 and which decodes it through the decoder 2-1-27. It is input to the line 2-1 to 26 as a chip selection signal of the address counter 2-1-9.

And IO that appears on the control bus of multibus 12-14
The write command is led to the line 2-1-28 and gated by the chip selection signal. When the chip selection occurs, the command signal causes the data on the line 2-1-3 to be parallel loaded to the address counter 2-1-9. To do. After the initial value is loaded, it counts up with a clock pulse on either line 2-1-8 or line 2-1-18.
The output of this address counter is the address converter 2-1.
Similar to 20, the memory selection signal is divided into the line 2-1-22 and the specific address in each memory is divided into the line 2-1-23. Signal of line 2-1-30 is CPU12-1
Alternatively, it is a memory write command and a memory read command signal output when the DMA controller 9 accesses the memory. By gated by the signal on the line 2-1-24, the command signal is output only when the buffer memory 2 is accessed on the line 2-1-31. A line 2-1-32 is a memory write / read signal based on any of the signals of the line 2-1-10, the line 2-1-19 and the line 2-1-31.

2-1-33 is a memory busy MB signal (indicating that the memory is in a read or write operation) output from each of the memories A, B and C to the control bus line of the internal bus 2-6 and a memory cycle enable. It is the MCE signal (indicating that the memory is in the read, write or refresh operation). The refresh control circuit 2-1-35 is CPU12
When the refresh trigger signal from -1 comes,
Confirm that it is neither an MCE nor MB signal, and apply a refresh pulse on the line 2-1-34 at a cycle of about 500 nsec for 128 times, which is a sufficient number to refresh the 16K dynamic RAM. Output. If the MB or MCE signal is output during the output of this refresh pulse, the output of the refresh pulse is temporarily interrupted and another refresh pulse is output after waiting for the memory access by these signals to end. To do.

Therefore, it is possible to prevent contention between the refresh pulse and the memory access pulse in the dynamic memory.

As described above, according to the present invention, it is possible to provide an image processing apparatus that can easily perform image processing for a user and can perform high-speed image processing.

19 and 20 are flow charts showing the operation of the image processing apparatus according to the present invention. FIG. 19 has the reader & printer sequence controller shown in FIG.
The operation of the CPU8085 is shown, which is set in the ROM of the reader & printer sequence controller, and FIG. 20 shows the CPU80 of the CPU circuit block shown in FIG.
The operation of 86 is shown, which is set in the ROM of the CPU circuit block.

When the device is powered on, the CPU 8086 proceeds to step S201 and waits for an interrupt from the CPU 8085 via interrupt lines 12-17.

On the other hand, in step S101, the CPU 8085 reads the application file name for desired image processing and the desired number of prints input as numerical information from the operation unit 13 shown in FIG. 8 through the interface 12-6. Write to RAM of reader & printer sequence controller. After that, the process proceeds to step S102, and the EQUUTE key 13 of the operation unit 13
Wait for -5 operation.

When the user operates the exit key 13-5, the CPU 8085 proceeds to step S103 and waits for an interrupt due to addressing from the CPU 8086.

The CPU 8085 becomes the CPU when the Exquito key 13-5 is operated.
Interrupt 8086. When the CPU 8086 determines this interrupt in step S201, the process proceeds to step S202. In step S202, the reader and printer sequence controller
Read the file name of the desired application file written in RAM and write it in RAM of the CPU circuit block. In step S203, the memory is stored in advance in the disk memory 4,
Enter the directory of the file name of the registered application file related to image processing to the R of the CPU circuit block.
Load into AM. Then, in step S204, it is checked whether or not the desired application file exists in the directory.

If not, the process proceeds to step S205, the error code is written in the RAM of the reader & printer sequence controller, and the process returns to step S201 to wait for a new interrupt. Also CPU8
The 086 interrupts the CPU 8085 simultaneously with writing the error code.

When the CPU 8085 receives this interrupt at step S103, it proceeds to step S104. In step S104, the code on the RAM of the reader & printer sequence controller is checked. In this case, the error code has been written, so step S1
At 05, proceed to step S106. Then, it indicates that the application file having the input file name is not registered. Turn on the APC display 13-7 of the operation unit 13. Then, the process returns to step S101 to wait for a new key input.

On the other hand, if the desired application name is found in the directory, the CPU 8086 advances to step S206. Step S
At 206, the application file stored in the disk corresponding to the input file name is loaded into the RAM of the CPU circuit block. Then go to step S207,
Sequentially read the character string of the application file. In steps S208 to S212, the one-character command and the carriage return signal of the application file sequentially read are discriminated and the corresponding processing is performed.

In step S208, the carriage return signal is discriminated.
The carriage return signal is a line feed command signal when displaying the application file on the application buffer 7-3 of the CRT 7. However, in the determination operation in step S208, the carriage return signal in the portion where the command continues after the line feed becomes invalid, and only the carriage return signal in the last portion of the application file becomes valid. That is, in step S208, it is determined whether or not the reading of the application file has been completed.

If the carriage return signal is discriminated in step S208, the process proceeds to step S213, and the end code for reading the application file is written in the RAM of the reader / printer sequence controller. Then, the process returns to step S201 to wait for a new interrupt.

In addition, the CPU8086 will
Interrupt 8085.

When the CPU 8085 determines this interrupt, it proceeds to step S104 and checks the code in the RAM of the reader & printer sequence controller. In this case, there is no error code, reader drive code, printer drive code, so step S1
After passing through 05, 107 and 108, the process returns to step S101 to wait for a new key input.

If the next read one-character command is "R" indicating document reading, the CPU 8086 advances from step S209 to step S214. In step S214, the reader driving code is written in the RAM of the reader & printer sequence controller.

In addition, when the reader drive code is written, the CPU8086
Interrupt 85.

If the CPU8085 judges an interrupt, the process proceeds to step S104, where R
Look up the AM code. Since the reader drive code is written in the RAM, the process proceeds from step S107 to step S118, and an instruction to start the advance of the reader drive motor is issued to the optical system scanning motor driver of the printer unit 1 to start reading the original. Then, when it is confirmed in step S119 that the document scanning of the reader is completed and the inversion position is reached, in step S120, the forward movement of the reader driving motor is turned off, and a backward movement start command is issued. In addition, the reader drive end flag is set in the RAM of the reader & printer sequence controller. At the same time, it interrupts the CPU 8086. And step S121
When it is confirmed that the reader has returned to the home position with, the reader drive motor is turned off in step S122, and step S1
Return to 03 and wait for a new interrupt.

When the CPU 8086 judges the interruption and confirms the set of the leader drive end flag of the RAM of the reader & printer sequence controller in step S215, the process returns to step S207 and the subsequent character string is read.

If the read one-character command is "P" indicating the output of the printer section, the CPU 8086 proceeds from step S210 to step S216 and writes the printer drive code in the RAM of the reader & printer sequence controller.

The CPU 8086 interrupts the CPU 8085 when writing the printer drive code.

When the CPU 8085 judges the interrupt, the process proceeds to step S104, and the RAM code is examined. Since the printer drive code is written in the RAM, step S108 to step S109
Proceed to. Steps S109 to S117 are known printing operations. That is, in step S109, pre-rotation for print preparation is performed, and when it is determined that the pre-rotation is completed in step S110, the recording material is fed in step S111. After that, in step S112, after a lapse of a predetermined time, the process proceeds to step S113 to instruct to output the image information for one page stored in the page memory 1. The printer unit 3 performs a printing operation based on this image information.

When it is determined in step S114 that the printing operation for one sheet is completed, the process proceeds to step S115. In step S115, it is checked whether or not the print operation of the desired number of prints written in the reader & printer sequence controller is completed. If not completed, the process returns to step S111 to repeat the printing operation. If the printing is completed, the flow advances to step S116 to set the print end flag in the RAM of the reader & printer sequence controller.

CPU8085 and CPU8086 together with the print end flag set
Interrupt. Then, the post-rotation cycle is performed in step S117, and the process returns to step S103 to wait for an interrupt from the CPU 8086.

When the CPU 8086 judges the interruption and confirms the set of the print end flag of the RAM of the reader & printer sequence controller in step S217, it returns to step S207 and reads the subsequent character string.

If the read one-character command is "S" for instructing the storage of the image information in the page memory 2 in the disk memory 4, the CPU 8086 advances to step S218. In step S218, the two characters following "(" in the character string are read as the file name of the image file, and the subsequent numerical values are read as the POSITION and SIZE information described above.
The address value of the page memory 2 is calculated from these numerical values. Then, in step S219, the image information of the page memory in the address area set in step S218 is DMA-transferred to the disk memory and stored. And step S207
Return to and read the subsequent character string.

If the read one-character command is "L" for instructing loading of the image file into the page memory 2, the process proceeds from step S212 to step S220. In step S220, the two characters following "(" in the character string are used as the file name of the image file, and the subsequent numerical values are described above.
Read as POSITION information. In step S221, the index part of the image file of the file name read in step S220 is transferred from the disk memory to the CPU circuit block RAM.
To load. Then, in step S222, the address value to which the image file of the page memory is to be transferred is calculated from the SIZE information of the index loaded in the RAM and the POSITION information read in step S220. In step S223, the image file having the file name read in step S220 is loaded into the address area calculated in step S222. Then, returning to step S207, the subsequent character strings are read.

As described above, according to the present invention, when performing image processing for recording an image of a desired area of a document on a recording material,
Not only is it possible to easily specify the desired area of the document by specifying the coordinates using a digitizer and pen instead of inputting numerical values using a keyboard, but also the desired area of the document that is specified by the coordinates on the digitizer is recognized graphically. Therefore, it is possible to easily determine whether or not the area specified by the coordinate instruction using the digitizer and the pen matches the desired area, and the desired area of the original can be specified with certainty.
Storing a plurality of sets of image processing programs including coordinate information representing a desired area of a document, which is graphically displayed according to coordinate instructions using a digitizer and a pen, and processing data for recording an image of the desired area of the document on a recording material. The image of the desired area of the original defined by the coordinate information included in the selectively read image processing program is recorded on the recording material according to the processing data included in the image processing program. The image processing for recording the image of the area on the recording material can be easily and surely executed a plurality of times without performing a complicated operation each time.

[Brief description of drawings]

FIG. 1-1 is a diagram showing the configuration of an embodiment of the image processing apparatus according to the present invention, FIG. 1-2 is a perspective view of the apparatus of this embodiment, FIG. 2 is a perspective view of the digitizer 6, and FIG. FIG. 1 is a detailed view of the surface of the digitizer of FIG. 2, FIG. 3-2 is a view showing an area designating method by the digitizer 6, and FIG. 3-3 is a flow chart showing an embodiment of control of the area designating method. , Fig. 4 is CR
FIG. 5 is a diagram showing the screen configuration of T7, FIG. 5 is a diagram showing command types, FIG. 6 is a diagram showing an image processing example, FIG. 7 is a diagram showing an application buffer, and FIG. Detail view,
FIG. 9 is a circuit block diagram of the apparatus of this embodiment, and FIG. 10 is a CR.
Circuit block diagram of T & digitizer controller 12-8,
FIG. 11 is a circuit block diagram of the CPU 12-1, FIG. 12 is a circuit block diagram of the reader & printer sequence controller 12-4, FIG. 13 is a circuit block diagram of the DMA controller 12-2, and FIG. 14 is a multi-bus. Memory map diagram, No. 15-
Figure 1 shows the address map of the buffer memory 12-3, 15th
-2 is a diagram showing a part of the address map of Fig. 15-1;
FIG. 16 is an address map diagram of the buffer memory 12-3 related to the multibus, FIG. 17 is a circuit block diagram of the buffer memory 12-3, and FIG. 18 is a circuit block diagram of the memory controller 2-1. The figure is an operation flow chart of the image processing apparatus according to the present invention.

Front page continuation (72) Inventor Yoshikazu Yokomizo 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Akira Suzuki 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Koichi Murakami 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Tadashi Yoshida 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Invention Person Masaharu Tsukada 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Nao Nagashima 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Ken Miyagi Tokyo 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (56) Reference JP-A-51-138332 (JP, A) JP-A-55-150662 (JP, A)

Claims (1)

[Claims] 1. A reading means for reading an original image and outputting image information representing the original image, a memory for storing the image information output by the reading means, a coordinate input surface corresponding to the original, and a pen A digitizer that outputs coordinate information that represents a desired area of the document based on an instruction to the coordinate input surface, a display unit that graphically displays the desired area of the document according to the coordinate information that is output from the digitizer, and the display unit. The coordinate information representing the desired area of the document displayed graphically on the display means, and the processing data for recording the image of the desired area of the document displayed graphically on the display means on the recording material. Storage means for storing a plurality of displayed image processing programs, and one of the plurality of sets of image processing programs stored in the storage means is designated. Specifying means, reading means for selectively reading the image processing program specified by the specifying means from the storage means, and storing in the memory according to the image processing program read from the storage means by the reading means. Recording for processing the image information stored in the image processing program, and recording an image of a desired area of the document defined by the coordinate information included in the image processing program on a recording material according to the processing data included in the image processing program. And an image processing apparatus.