JPH0686095A - Dc level stabilizing circuit - Google Patents

Abstract

PURPOSE:To prevent a noise produced in a line cycle by supplying a clamp pulse to a comparator constructing a digital clamping circuit in each vertical scanning period. CONSTITUTION:A sawtooth wave signal (a) is inputted through an input terminal In1 of a digital clamping circuit 1 which constructs a DC level stabilizing circuit. Thus the reference data is supplied to a comparator 16b through an input terminal In3 and at the same time a clamp pulse (d) is supplied to the comparator 16b through an input terminal In2. The pulse (d) is supplied once or several times at each vertical flyback time and at the start of a scanning period. The comparator 16b compares the pulse (d) with the reference data and then supplies the comparison output as a correction signal (b) to an adder/subtractor 16c via an averaging circuit 16d. The adder/ subtractor 16c performs the addition and the subtraction when the level to be clamped is low and high respectively to obtain the clamp output (c). Thus it is possible to prevent the noise which are produced in a line cycle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC level stabilizing circuit suitable for use in a color video camera or the like, and more particularly to a DC level capable of performing digital signal processing and reducing line period noise significantly. Regarding the stabilizing circuit.

[0002]

2. Description of the Related Art In recent years, with the progress of digital signal processing,
In the signal processing circuit technology used in a DC level stabilizing circuit of a camera-integrated recording / reproducing apparatus or the like, many parts are replacing conventional analog processing with digital processing. In particular, in this type of device, part or all of the signal processing of the camera unit is being digitized. By digitizing this camera unit, the number of parts is reduced, the adjustment process is reduced, and the stability is improved. The advantages such as high image quality and multi-functionality can be expected.

The clamp circuit included in the DC level stabilizing circuit adopting such digital technology sets the input level to the DC level within the operating range of the analog / digital conversion circuit (hereinafter also referred to as "A / D conversion circuit"). Is generally provided for the purpose of setting the optical black level of the solid-state image sensor.

FIG. 2 is a block diagram showing an example in which the DC level stabilizing circuit 2 is formed by using such a clamp circuit in a color video camera. In the figure, the imaging light irradiated to a solid-state imaging device (hereinafter also referred to as “CCD”) 11 via a lens system (not shown) is photoelectrically converted here, and a correlated double sampling circuit of the next stage is provided. (CDS)
12 are supplied. In the correlated double sampling circuit 12, the intermittent signal from the CCD 11 is converted into a continuous signal by sampling or the like, and the AGC (automatic gain control) circuit 1 of the next stage is provided.
Gain control is automatically performed at 3. The output signal of this AGC circuit 13 is an analog clamp circuit (CP) 14,
V so that it falls within the operating point of the A / D conversion circuit 15 in the next stage
After being clamped to the DC potential of _ref , A / D conversion circuit 1
It is converted into a digital signal by 5. Then, it is supplied to the digital process circuit 6 where predetermined signal processing is performed. In addition, digital clamp circuit 1
There is also a configuration in which 6 is provided at the first stage of the digital process circuit 6 as shown in FIG.

Further, various digitally constructed clamp circuits have been recently proposed.

By the way, in the analog clamp circuit (14), the accuracy of the clamp potential is generally poor due to the influence of the clamp error, the temperature characteristic, etc., and it may be insufficient to stabilize the optical black level. It was Also,
Although the digital clamp circuit 16 is sufficiently accurate, the analog clamp
There is a drawback that the pull-in range of the clamp circuit 14 becomes narrow. Therefore, when the gain of the AGC circuit (13) provided on the preceding stage side of the analog clamp circuit 14 greatly changes, there is a problem that the clamp operation becomes defective.

In order to solve such a problem, a microprocessor (hereinafter also referred to as "CPU") 17 is used as a clamp potential generating circuit for generating a clamp potential instead of the DC power supply V _ref in FIG. The applicant has developed a direct current level stabilizing circuit connected as shown in FIG. 2 and applied for a patent application No. 3-137284. In such a configuration, the analog signal clamped by the analog clamp circuit 14 so as to be within the operating range of the A / D conversion circuit 15 is converted into a 10-bit digital signal by the A / D conversion circuit 15, and further, It is supplied to the digital clamp circuit 16 of the next stage and also to the CPU 17.

Here, regarding the clamp reference of the analog clamp circuit 14 and the digital clamp circuit 16, there is a difference in the DC level correction range between the analog clamp circuit 14 and the digital clamp circuit 16.
That is, the analog clamp circuit 14 has a larger pull-in range and the digital clamp circuit 16 has a smaller pull-in range so that high-precision clamping can be performed.

For example, if the clamp reference of the digital clamp circuit 16 is set to 5% of the full scale data, the optical black level at the output point (c) of the digital clamp circuit 16 is 040H in hexadecimal display. (Ten
When quantizing with bits). In consideration of the circuit scale of the digital clamp circuit 16, a correction range of about 0 to 25% (000H to 0FFH) of full scale (3FFH) is considered appropriate. That is, when the data at the input point (b) is in the range of 000H to 0FFH, it converges to 040H, but in the case of more fluctuation, it cannot be converged on the digital clamp circuit 16 side and an error occurs. turn into. Therefore, in the analog clamp circuit 14, A /
The signal at the input point (a) of the D conversion circuit 15 is clamped so as to be in the range of 0 to 25% of full scale.

Here, the analog clamp circuit 14 and the digital clamp circuit 16 will be described with reference to FIGS. 3 and 4, which are more specific circuit block configurations. 3 and 4 are a block diagram of the digital clamp circuit 16 and a circuit diagram of the analog clamp circuit 14, respectively.

From the A / D conversion circuit 15 of FIG. 2 to the CPU 17
The data input to is compared here with the reference potential data. By this comparison, a correction potential that falls within the correction range (0 to 25%) is supplied to the input terminal 14b of the analog clamp circuit 14. A clamp pulse is supplied to the transistor Tr2 every horizontal blanking period, and at the time of this supply, the transistor Tr2 is supplied from the input terminal 14a in accordance with the correction potential.
1, clamp the incoming signal through capacitor C1 at point P. Here, the CPU 17 controls the correction potential to be increased when the output potential is low and conversely decreased when the output potential is high.

In this case, the time constant determined by the resistance value of the resistor R3 and the capacitance of the capacitor C2 is, for example, several times of the horizontal scanning period to the rate of the vertical scanning period. Therefore, the analog clamp circuit 14 has a large pull-in range. Further, the clamped signal is output from the output terminal 14c via the transistor Tr3. Then, this output signal is input to the digital clamp circuit 16 via the A / D conversion circuit 15 at the next stage as an input terminal 16
supplied from a.

The signal a from the input terminal 16a (FIG. 5A)
Reference} is supplied to the comparator 16b and the adder / subtractor 16c. A clamp pulse d as shown in FIG. 5 (B) is supplied to the comparator 16b from the input terminal In2 at every horizontal blanking period, and it is compared with the reference data to be clamped at the time of supply, and the correction signal b {Refer to FIG. 5 (C)} is supplied to the adder / subtractor 16c. In the adder / subtractor 16c, addition is performed when the signal level to be clamped by the correction signal b is low, and subtraction is performed when the signal level is high, and a clamp output c as shown in FIG. 5D is obtained. . This digital clamp circuit 1
The time constant of comparison and addition / subtraction of 6 is one horizontal scanning period rate, which is smaller than the time constant of the analog clamp circuit 14. And finally, the input signal is full scale
Clamped to 5% of data.

[0014]

In the DC level stabilizing circuit adopting the conventional DC level stabilizing circuit described above, the digital clamp is operated at one horizontal scanning period rate (hereinafter also referred to as "H rate"). Therefore, the OB period of the input signal {the period in which the clamp pulse is generated;
(B) noise component is output from the comparator 16b and the input signal is added / subtracted at the H rate, so that noise is returned to the low frequency band, that is, within the high frequency band such as the video signal band. When the noise component is sampled with a pulse of H period, aliasing noise is generated, so that there is a drawback that noise of line period (horizontal noise) is generated as shown in FIG. 5 (A).

[0015]

A DC level stabilizing circuit of the present invention is an analog clamp circuit for clamping an output signal from an image pickup device and an A / D for digitizing an output signal of the analog clamp circuit. Conversion circuit and this A
A digital clamp circuit that clamps the output signal of the A / D conversion circuit, and a clamp potential generation circuit that compares the output signal of the A / D conversion circuit with the reference potential data to generate the clamp potential of the analog clamp circuit , While making the DC level correction range of the analog clamp circuit larger than the DC level correction range of the digital clamp circuit,
In order to perform the clamp operation of the digital clamp circuit only once in each vertical scanning period, the comparator constituting the digital clamp circuit is configured to supply the clamp pulse only once in each vertical scanning period. It is a solution to the problem.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a DC level stabilizing circuit of the present invention will be described with reference to the block diagram of FIG. 1 and the signal waveform diagram (timing chart) of FIG. FIG. 1 is a block diagram of a digital clamp circuit 1 which constitutes the DC level stabilizing circuit of the present invention together with the analog clamp circuit 14, A / D conversion circuit 15, and CPU 17.
In this figure, the same components as those of the conventional circuit shown in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted. In the figure,
Although 16d is an averaging circuit, it is not always necessary to provide this. Although the reference data is supplied to the comparator 16b from the outside, it may be provided as internal data in the comparator 16b as in the conventional example shown in FIG.

A sawtooth signal a as shown in FIG. 5A is supplied from the input terminal In1 to the comparator 16b and the adder / subtractor 16c. The reference data is supplied from the CPU 17 to the comparator 16b via the input terminal In3, and the clamp pulse d'is supplied from the input terminal In2. This clamp pulse d'is not shown in each horizontal blanking period, but in FIG.
As shown in (1), it is supplied once every vertical blanking period, for example, at the start of one vertical scanning period. Then, it is compared with the reference data to be clamped at the time of supply, and the comparison output held for one vertical scanning period is supplied to the adder / subtractor 16c as a correction signal b ', as shown in FIG. 5 (F). In the adder / subtractor 16c, addition is performed when the signal level to be clamped by the correction signal b is low, and subtraction is performed when the signal level is high, and a clamp output c'as shown in FIG. 5 (H) is obtained. To be The time constant of comparison and addition / subtraction of the digital clamp circuit 1 is one vertical scanning period rate, which is larger than the time constant of the analog clamp circuit 14. And finally, the input signal is clamped to 5% of full-scale data.

In the above description, the clamp pulse d'is supplied to the comparator 16b once every vertical blanking period. However, the averaging circuit 16d is replaced by the comparator 16b.
Clamp pulse d
Is supplied to the comparator 16b, for example, several tens of times for each vertical scanning period (see FIG. 5 (C)), and the results are averaged by the averaging circuit 16d, as shown in FIG. 5 (G). The smoothed averaging output e may be obtained and supplied to the adder / subtractor 16c to perform addition / subtraction processing at the H rate.

[0019]

Since the DC level stabilizing circuit of the present invention is configured as described above, the above-mentioned problems in the conventional circuit are solved, and noise of a line period (horizontal pulling noise) as shown in FIG. ) Can be prevented. Therefore, when the circuit of the present invention is applied to a color video camera, there is an excellent feature that the S / N and the image quality can be improved.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a digital clamp circuit that constitutes a DC level stabilizing circuit of the present invention.

FIG. 2 is a block diagram showing an example in which a conventional DC level stabilizing circuit is used in a color video camera.

FIG. 3 is a block configuration diagram of a digital clamp circuit.

FIG. 4 is a circuit configuration diagram of an analog clamp circuit.

FIG. 5 is a signal waveform diagram (timing chart) for explaining the operation of the conventional circuit and the circuit of the present invention.

[Explanation of symbols]

1, 16 Digital clamp circuit (DC level stabilizing circuit) 6 Digital process circuit 11 Solid-state image pickup device (CCD) 12 Correlated double sampling circuit (CDS) 13 AGC circuit 14 Analog clamp circuit (CP) 15 Analog / digital (A / D) conversion circuit 16b comparator 16c adder / subtractor 16d averaging circuit 17 microprocessor (CPU)

Claims (2)

[Claims] 1. An analog clamp circuit for clamping an output signal from an image pickup device, an analog / digital conversion circuit for digitizing the output signal of the analog clamp circuit, and an output signal of the analog / digital conversion circuit. The analog clamp circuit comprises: a digital clamp circuit for clamping; and a clamp potential generation circuit for generating a clamp potential of the analog clamp circuit by comparing an output signal of the analog / digital conversion circuit with reference potential data. A DC level stabilizing circuit for making the DC level correction range of the circuit larger than the DC level correction range of the digital clamp circuit, wherein the clamp operation of the digital clamp circuit is performed only once in each vertical scanning period. , Clamp pulse to this digital clamp circuit every vertical scanning period DC level stabilizing circuit configured to supply only once. 2. An analog clamp circuit for clamping an output signal from an image pickup device, an analog / digital conversion circuit for digitizing an output signal of the analog clamp circuit, and an output signal of the analog / digital conversion circuit. A digital clamp circuit for clamping, and a clamp potential generation circuit for comparing the output signal of the analog / digital conversion circuit with reference potential data to generate a clamp potential of the analog clamp circuit are provided. A comparator for comparing the output signal from the analog / digital conversion circuit with predetermined reference data, an averaging circuit for averaging the output of the comparator for each vertical scanning period, and the averaging circuit. Addition and subtraction of addition and subtraction of the output of and the output from the analog / digital conversion circuit Level stabilizing circuit configured to supply a clamp pulse for causing the comparator to perform a comparison operation a plurality of times for each vertical scanning period.