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JPH0687478B2 - Wiring layer inspection method - Google Patents
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JPH0687478B2 - Wiring layer inspection method - Google Patents

Wiring layer inspection method

Info

Publication number
JPH0687478B2
JPH0687478B2 JP26711487A JP26711487A JPH0687478B2 JP H0687478 B2 JPH0687478 B2 JP H0687478B2 JP 26711487 A JP26711487 A JP 26711487A JP 26711487 A JP26711487 A JP 26711487A JP H0687478 B2 JPH0687478 B2 JP H0687478B2
Authority
JP
Japan
Prior art keywords
substrate
wiring layer
layer
light
sio
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP26711487A
Other languages
Japanese (ja)
Other versions
JPH01109735A (en
Inventor
伸夫 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP26711487A priority Critical patent/JPH0687478B2/en
Publication of JPH01109735A publication Critical patent/JPH01109735A/en
Publication of JPH0687478B2 publication Critical patent/JPH0687478B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 〔概要〕 半導体基板上に形成された配線層の被覆状態を検査する
方法に関する。
The present invention relates to a method for inspecting a covering state of a wiring layer formed on a semiconductor substrate.

迅速に,金属配線層の被覆状態の良否を判定し,不良基
板を除去するか,または再処理することを目的とし, 半導体基板上に配線層を形成後,該基板の裏面より波長
1.3〜6μmの赤外光を含む光を照射し,該基板を透過
する光を赤外検出器で検出し,透過光により該配線層の
被覆状態を検査するように構成する。
After the wiring layer is formed on the semiconductor substrate, the wavelength is measured from the back surface of the substrate for the purpose of promptly judging the quality of the covering state of the metal wiring layer and removing or reprocessing the defective substrate.
It is configured to irradiate light including infrared light of 1.3 to 6 μm, detect light transmitted through the substrate with an infrared detector, and inspect the covering state of the wiring layer by the transmitted light.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体基板上に形成された配線層の被覆状態を
検査する方法に関する。
The present invention relates to a method for inspecting a covering state of a wiring layer formed on a semiconductor substrate.

〔従来の技術〕[Conventional technology]

第3図はコンタクトホールの段差被覆を説明する基板断
面図である。
FIG. 3 is a substrate cross-sectional view for explaining step coverage of contact holes.

図において,1はSi基板,2はフィードSiO2層,3はゲートSi
O2層,4はゲートポリSi層,5はPSG層間絶縁層,6はコンタ
クトホール,7はA1配線層である。
In the figure, 1 is the Si substrate, 2 is the feed SiO 2 layer, and 3 is the gate Si.
O 2 layer, 4 is a gate poly-Si layer, 5 is a PSG interlayer insulating layer, 6 is a contact hole, and 7 is an A1 wiring layer.

第4図は配線交差部の段差被覆を説明する基板断面図で
ある。
FIG. 4 is a cross-sectional view of a substrate for explaining step coverage at a wiring intersection.

図において,1はSi基板,7は下層A1配線層,8はPSG層間絶
縁層,9は上層A1配線層である。
In the figure, 1 is a Si substrate, 7 is a lower A1 wiring layer, 8 is a PSG interlayer insulating layer, and 9 is an upper A1 wiring layer.

集積回路のウエハプロセスにおいて,第3図に示される
ように電極引き出し用のコンタクトホール6上(A部)
や,第4図のように2本の配線7,9が絶縁層を介して交
差する部分(B部)で,配線層の被覆が薄くなり,甚だ
しい場合は断線を生ずることがある。
In the integrated circuit wafer process, as shown in FIG. 3, on the contact hole 6 for drawing out the electrode (A portion).
Alternatively, as shown in FIG. 4, the coating of the wiring layer becomes thin at a portion (B portion) where the two wirings 7 and 9 intersect with each other with the insulating layer interposed therebetween, which may cause a disconnection in a severe case.

このような段差被覆を改善する方法として,層間絶縁層
に燐珪酸ガラス(PSG)を用い,これをリフローする方
法が用いられている。
As a method of improving such step coverage, a method of using phosphosilicate glass (PSG) for the interlayer insulating layer and reflowing it is used.

この方法はPSGを基板上に堆積し,第3図の場合はコン
タクトホールの窓開けをした後,1050℃以上に加熱する
と,PSGは流動し,コンタクトホールの急峻な段差をなだ
らかにする。
In this method, PSG is deposited on the substrate, and in the case of Fig. 3, when the contact hole window is opened and then heated to 1050 ° C or higher, the PSG flows and the steep steps of the contact hole are smoothed.

しかし,この方法ではデバイスの微細化が進んで,コン
タクトホールの直径が0.5μm程度になると,流動によ
り孔が塞がってしまうという問題がある。
However, this method has a problem that the device is miniaturized and when the diameter of the contact hole becomes about 0.5 μm, the hole is blocked by the flow.

また,微細化に伴ってプロセスの低温化が必要になり,1
050℃以上に加熱ができなくなってきている。
In addition, with the miniaturization, it is necessary to lower the process temperature.
It is no longer possible to heat above 050 ℃.

さらに第4図の場合は下層配線がA1であるため,上層配
線の段差被覆改善のためのPSGのリフローは困難であ
る。これはA1は500℃程度でPSG,或いはSiO2と激しく反
応して,下層配線に障害を生ずるためである。
Furthermore, in the case of FIG. 4, since the lower layer wiring is A1, it is difficult to reflow the PSG to improve the step coverage of the upper layer wiring. This is because A1 reacts violently with PSG or SiO 2 at about 500 ° C, causing damage to the lower layer wiring.

一方,リフロー温度を下げるため,Pbを含ませたSiO
2や,燐濃度を増やしたPSGが用いられることもあるが,
これらのものは吸湿性が増し,集積回路の特性を劣化さ
せる原因になる。
On the other hand, in order to lower the reflow temperature, SiO containing Pb
2 or PSG with increased phosphorus concentration may be used,
These materials increase hygroscopicity and cause deterioration of integrated circuit characteristics.

また,段差被覆の改善に,エッチングにより段差に丸み
を持たせる方法がある。しかし,その制御は非常に不安
定なものである。
Further, there is a method of making the step round by etching in order to improve the step coverage. However, its control is extremely unstable.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

しかしながら,以上述べた種々の段差被覆改善方法は,
すべての製造ロットにわたって完全無欠にすることは極
めて困難である。
However, the various step coverage improvement methods described above are
It is extremely difficult to be perfect over all production lots.

そこで,本発明は,金属配線層を基板上に堆積直後に,
段差被覆の不良個所を検出し,エッチングや堆積のプロ
セスを再度行って不良基板を修正するか,或いは不良基
板に対して後工程が行われる損失を避けることを目的と
する。
Therefore, the present invention provides, immediately after depositing a metal wiring layer on a substrate,
The purpose is to detect a defective portion of the step coverage and perform the etching or deposition process again to correct the defective substrate, or to avoid a loss in which a subsequent process is performed on the defective substrate.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点の解決は,半導体基板上に配線層を形成後,
該基板の裏面より波長1.3〜6μmの赤外光を含む光を
照射し,該基板を透過する光を赤外検出器で検出し,透
過光により該配線層の被覆状態を検査する方法により達
成される。
To solve the above problems, after forming the wiring layer on the semiconductor substrate,
Achieved by irradiating the back surface of the substrate with light containing infrared light having a wavelength of 1.3 to 6 μm, detecting the light transmitted through the substrate with an infrared detector, and inspecting the covering state of the wiring layer by the transmitted light. To be done.

〔作用〕[Action]

第1図は本発明を説明する半導体基板の断面図である。 FIG. 1 is a sectional view of a semiconductor substrate for explaining the present invention.

図において,1はSi基板,2はフィールドSiO2層,3はゲート
SiO2層,4はゲートポリSi層,5はPSG層間絶縁層,6はコン
タクトホール,7はA1配線層である。
In the figure, 1 is the Si substrate, 2 is the field SiO 2 layer, and 3 is the gate.
SiO 2 layer, 4 is a gate poly Si layer, 5 is a PSG interlayer insulating layer, 6 is a contact hole, and 7 is an A1 wiring layer.

本発明は,A1配線層7を基板の表面側全面に堆積後,そ
の配線層のパターニング前にSi基板1の裏面より赤外光
(IR)を照射し,矢印で示される漏洩赤外光を検出して
断線の有無を判定するものである。
The present invention irradiates infrared light (IR) from the back surface of the Si substrate 1 after depositing the A1 wiring layer 7 on the entire front surface side of the substrate, and before patterning the wiring layer, so that leakage infrared light indicated by an arrow is emitted. This is to detect and determine the presence or absence of disconnection.

ここで,赤外光は波長1.3〜6μmを含むものを用いる
と,Si,SiO2,PSG等はこの波長範囲の赤外光はよく透過
し,A1はどの波長の赤外光も透過しない。
Here, if infrared light having a wavelength of 1.3 to 6 μm is used, Si, SiO 2 , PSG, etc., transmit infrared light in this wavelength range well, and A1 does not transmit infrared light of any wavelength.

一般に,半導体装置は配線金属以外は単結晶および多結
晶Siと,CVD−PSGや,CVD−SiO2や,熱酸化SiO2のような
主成分がSiO2からなる膜よりなっている。
In general, a semiconductor device is composed of single-crystal and poly-crystal Si except for wiring metal, and a film whose main component is SiO 2 such as CVD-PSG, CVD-SiO 2 , and thermally oxidized SiO 2 .

これに対して,Siの透過率は波長が1.3μm付近で大きく
変化し1.3μm以上で増加し,一方SiO2の透過率は6μ
m以上で大きく減少する。
On the other hand, the transmittance of Si changes greatly at wavelengths around 1.3 μm and increases above 1.3 μm, while the transmittance of SiO 2 is 6 μm.
Greatly decreases when m or more.

透過率を測定した一例をあげると,次のようである。An example of measuring the transmittance is as follows.

波長(μm) 1 1.5〜4 10 透過率Si 0.2 99 70 (%)SiO2 90 90 3 PSG 90 90 3 A1 0.0 0.0 0.0 但し,膜厚は,Si:300,SiO2:70,PSG:300,A1:μmであ
る。
Wavelength (μm) 1 1.5 to 4 10 Transmittance Si 0.2 99 70 (%) SiO 2 90 90 3 PSG 90 90 3 A1 0.0 0.0 0.0 However, the film thickness is Si: 300, SiO 2 : 70, PSG: 300, A1: μm.

上表より,Siの厚さが300μm,SiO2の厚さが高々10μmの
半導体装置であれば,波長1.5〜4μmの赤外光は金属
膜がなければ90%以上が透過し,1μmのA1膜があると透
過率は0.0%となることが分かる。
From the above table, in the case of a semiconductor device with a Si thickness of 300 μm and a SiO 2 thickness of at most 10 μm, 90% or more of infrared light with a wavelength of 1.5 to 4 μm is transmitted without a metal film, and 1 μm of A1 It can be seen that the transmittance becomes 0.0% with the film.

上記の測定結果は,1.5〜4μmの波長範囲で行ったが,
上述の理由により1.3〜6μmの波長範囲でも略同等に
近い効果がある。
The above measurement results were measured in the wavelength range of 1.5 to 4 μm,
Due to the above-mentioned reason, there is an effect that is almost equal in the wavelength range of 1.3 to 6 μm.

〔実施例〕〔Example〕

第2図は本発明の一実施例を説明する装置の構成図であ
る。
FIG. 2 is a block diagram of an apparatus for explaining an embodiment of the present invention.

図において,ランプハウス11より出た赤外光はミラー12
で反射して半導体基板13の裏面に入射される。
In the figure, the infrared light emitted from the lamp house 11 is reflected by the mirror 12
It is reflected by and is incident on the back surface of the semiconductor substrate 13.

半導体基板13を透過した光は結像レンズ14により結像面
15上に結像され,結像面15に置かれた赤外検出器16によ
り検出されアンプ17で増幅して出力される。
The light transmitted through the semiconductor substrate 13 is focused by the imaging lens 14 on the imaging surface.
An image is formed on 15 and detected by an infrared detector 16 placed on the image plane 15, amplified by an amplifier 17, and output.

また,図示していないが基板13と結像レンズ14の間にチ
ョッパをおいて,赤外検出器16の出力を交流増幅するこ
ともできる。
Although not shown, a chopper may be placed between the substrate 13 and the imaging lens 14 to AC amplify the output of the infrared detector 16.

この場合、基板表面全域を結像レンズ14で縮小して赤外
検出器16の感光板上に結像させる。
In this case, the entire surface of the substrate is reduced by the imaging lens 14 to form an image on the photosensitive plate of the infrared detector 16.

ランプハウス11より出る赤外光は1.3〜6μmの波長範
囲内の特定の波長の単色光であってもよく,またこの範
囲内の複数の単色光であってもよい。さらに,この範囲
内の光以外の赤外,可視,紫外光が含まれていても,こ
れらの光は金属膜を透過できないので,本発明を実施す
る上で障害となることはない。
The infrared light emitted from the lamp house 11 may be monochromatic light having a specific wavelength within the wavelength range of 1.3 to 6 μm, or may be a plurality of monochromatic lights within this range. Furthermore, even if infrared, visible, or ultraviolet light other than the light within this range is included, these lights cannot pass through the metal film, so that there is no obstacle in carrying out the present invention.

ランプハウス11は,例えば沃素(I)を封入したタング
テンランプを用いる。この場合の発光スペクトルは,波
長が0.2μm以上になると立ち上がり1μm近傍でピー
クになり,波長の増加ととに漸減する連続スペクトルで
ある。
As the lamp house 11, for example, a Tung-ten lamp filled with iodine (I) is used. The emission spectrum in this case is a continuous spectrum that rises at a wavelength of 0.2 μm or more, peaks near 1 μm, and gradually decreases as the wavelength increases.

赤外検出器16は,HgCdTe系の化合物半導体を用いた光起
電力素子,またはPb薄膜をガラス基板に被着した光伝導
素子を用いる。
As the infrared detector 16, a photovoltaic element using a HgCdTe-based compound semiconductor or a photoconductive element in which a Pb thin film is coated on a glass substrate is used.

いま,赤外検出器16の素子を1個使用した場合は,A1膜
のカバレージの悪い場所の数,あるいは悪さの程度に応
じてアンプ17の出力電圧がアナログに変化する。
Now, when one element of the infrared detector 16 is used, the output voltage of the amplifier 17 changes to analog according to the number of places where the coverage of the A1 film is bad or the degree of badness.

一方,赤外検出器16の素子を多数アレイ状に並べたもの
を用いれば,結像面15には基板13の像が得られるので,
アンプ17の出力をコンピュータ処理して基板13のどの場
所がカバレージ不良であるかをマップ化することもでき
る。
On the other hand, if a large number of elements of the infrared detector 16 are arranged in an array, an image of the substrate 13 can be obtained on the image plane 15,
The output of amplifier 17 can also be processed by computer to map which location on substrate 13 is poorly covered.

〔発明の効果〕〔The invention's effect〕

以上詳細に説明したように本発明によれば,迅速に,金
属配線層の被覆状態の良否を判定することができる。
As described in detail above, according to the present invention, it is possible to quickly determine the quality of the covering state of the metal wiring layer.

従って,不良基板を除去することにより,後工程を行う
ことによる損失を除き,または不良基板を再処理するこ
とにより良品基板に変えることができる。
Therefore, by removing the defective substrate, it is possible to eliminate the loss due to the post-process, or by reprocessing the defective substrate, it can be changed to a non-defective substrate.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明を説明する半導体基板の断面図, 第2図は本発明の一実施例を説明する装置の構成図, 第3図はコンタクトホールの段差被覆を説明する基板断
面図, 第4図は配線交差部の段差被覆を説明する基板断面図で
ある。 図において, 1はSi基板, 2はフィールドSiO2層, 3はゲートSiO2層, 4はゲートポリSi層, 5はPSG層間絶縁層, 6はコンタクトホール, 7はA1配線層, 11はランプハウス, 12はミラー, 13は半導体基板, 14は結像レンズ, 15は結像面, 16は赤外検出器, 17はアンプ である。
1 is a sectional view of a semiconductor substrate for explaining the present invention, FIG. 2 is a configuration diagram of an apparatus for explaining an embodiment of the present invention, FIG. 3 is a sectional view of a substrate for explaining step coverage of a contact hole, FIG. 4 is a substrate cross-sectional view for explaining the step coverage at the wiring intersection. In the figure, 1 is a Si substrate, 2 is a field SiO 2 layer, 3 is a gate SiO 2 layer, 4 is a gate poly Si layer, 5 is a PSG interlayer insulating layer, 6 is a contact hole, 7 is an A1 wiring layer, and 11 is a lamp house. , 12 is a mirror, 13 is a semiconductor substrate, 14 is an imaging lens, 15 is an imaging plane, 16 is an infrared detector, and 17 is an amplifier.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上に配線層を形成後,該基板の
裏面より波長1.3〜6μmの赤外光を含む光を照射し,
該基板を透過する光を赤外検出器で検出し,透過光によ
り該配線層の被覆状態を検査することを特徴とする配線
層の検査方法。
1. After forming a wiring layer on a semiconductor substrate, the back surface of the substrate is irradiated with light containing infrared light having a wavelength of 1.3 to 6 μm,
A method for inspecting a wiring layer, which comprises detecting light transmitted through the substrate with an infrared detector and inspecting the covering state of the wiring layer by the transmitted light.
JP26711487A 1987-10-22 1987-10-22 Wiring layer inspection method Expired - Lifetime JPH0687478B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26711487A JPH0687478B2 (en) 1987-10-22 1987-10-22 Wiring layer inspection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26711487A JPH0687478B2 (en) 1987-10-22 1987-10-22 Wiring layer inspection method

Publications (2)

Publication Number Publication Date
JPH01109735A JPH01109735A (en) 1989-04-26
JPH0687478B2 true JPH0687478B2 (en) 1994-11-02

Family

ID=17440258

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26711487A Expired - Lifetime JPH0687478B2 (en) 1987-10-22 1987-10-22 Wiring layer inspection method

Country Status (1)

Country Link
JP (1) JPH0687478B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3300479B2 (en) * 1993-07-19 2002-07-08 浜松ホトニクス株式会社 Semiconductor device inspection system
US6002792A (en) * 1993-11-16 1999-12-14 Hamamatsu Photonics Kk Semiconductor device inspection system
JP3478612B2 (en) * 1993-11-16 2003-12-15 浜松ホトニクス株式会社 Semiconductor device inspection system
JP2002083265A (en) * 2000-09-05 2002-03-22 Nidek Co Ltd Character recognition device for semiconductor wafer, and character recognizing optical unit

Also Published As

Publication number Publication date
JPH01109735A (en) 1989-04-26

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