JPH0690617B2 - Electronic musical instrument - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Industrial field of application" The present invention is capable of storing and reproducing performance data in an electronic musical instrument body and transferring the performance data to an external storage means detachably attached to the musical instrument body. Regarding electronic musical instruments.

"Prior Art" An electronic musical instrument has been developed in which performance data corresponding to a keyboard performance is stored inside and an automatic performance can be performed by the stored performance data. Further, in this type of electronic musical instrument, the performance data stored inside can be transferred to an external memory (for example, Japanese Patent Laid-Open No. 59-139093).
(See the official gazette).

"Problems to be Solved by the Invention" In the conventional electronic musical instrument described above, the performance data stored in the internal memory is uniquely transferred to the external memory without considering the storage capacity of the external memory. If the storage capacity of the external memory is smaller than that of the internal memory, it is not possible to transfer all the performance data read from the internal memory, and a transfer error occurs.

Therefore, in order to avoid such a transfer error, it becomes necessary to make the storage capacity of the external memory equal to or larger than the storage capacity of the internal memory.
For this reason, a memory which is relatively inexpensive and has a small storage capacity cannot be used as an external memory, which causes a cost increase.

Further, as described above, when the performance data is transferred to the external memory having a small storage capacity, the performance data created due to the transfer error is wasted.

The present invention has been made in view of the above-mentioned circumstances. Even when an external memory having a storage capacity smaller than that of the internal memory is used, a transfer error does not occur, and a performance created for transfer is created. The purpose is to provide an electronic musical instrument that does not waste data.

"Means for Solving Problems" The present invention relates to an electronic musical instrument which is provided in the musical instrument main body and has an internal storage means for storing performance data and an external storage means detachably attached to the musical instrument main body. A transfer instruction means for instructing transfer of the performance data, a determination means for determining the storage capacity of the external storage means when the transfer is instructed by the transfer instruction means, and a storage capacity determined by the determination means. Accordingly, it is characterized by comprising a transfer control means for reading the entire performance data or a part of the performance data from the internal storage means and transferring it to the external storage means.

[Operation] According to the above configuration, when the transfer instructing means instructs the transfer of the performance data stored in the internal storage means, the determination means determines the storage capacity of the external storage means, and the transfer control means determines the determined storage. Depending on the capacity, all of the performance data or a part of the performance data is read from the internal storage means and transferred to the external storage means.

As a result, even if an external storage means having a storage capacity smaller than that of the internal storage means is used, a part of the performance data is transferred, so that a transfer error does not occur unlike the conventional case, and the operation data created for transfer can be stored. It will not be wasted.

[Examples] Examples of the present invention will be described below with reference to the drawings.

(1) First Embodiment (1-1) Configuration of the First Embodiment FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. In the figure, 1 is a CPU that controls each part of the device
It is a (central processing unit) and operates based on a program stored in the program memory 2. Reference numeral 3 is a working area in which various data are stored according to the processing of the CPU 1, and various registers described later are set therein.

Reference numeral 5 denotes a key switch unit composed of an upper key UK, a lower key LK, a pedal key PK and a solo key SK, and ON / OFF information of each of the above keys is supplied to the CPU 1 via the key switch interface 6. Here, the solo key SK is a key used at the time of solo performance, and only one of the notes is enabled by the processing of the late arrival priority or the highest note priority. Usually, Solo Key SK is provided on the upper row of Upper Key UK.

Reference numeral 4 denotes a display unit composed of a liquid crystal display and its drive circuit, which displays various messages under the control of the CPU 1.

The panel switch section 8 includes various switches provided on the operation panel, that is, switches for selecting a tone color, effect, rhythm, etc., and switches for controlling performance data. This panel switch section 8
The ON / OFF information of each switch is supplied to the CPU 1 via the panel switch interface 9.

Here, each switch shown in FIG. 2 is a performance data control switch in the panel switch section 8, and these switches will be described below.

(I) Switch FMP / REC When the switch FMP / REC is pressed, the CPU1 stores the performance data corresponding to the performance performed by the operator in the performance data memory.
Remember to 10. The performance data is composed of pitch and on / off information of each key in the key switch section 5 and on / off information (registration information) such as a tone color switch and a rhythm selection switch in the panel switch section 8. When the switch U is pressed while the switch FMP / REC is turned on, the performance data excluding the ON / OFF information of the upper key UK is supplied to the performance data memory 10. Similarly, switch L,
When switch P, switch S, and switch R are pressed, lower key LK, pedal key PK, and solo key SK are turned on / off.
The off information and the registration information are controlled to be removed. Therefore, the performer can select the type of data to be stored in the performance data memory 10.

Here, the data format of the arithmetic data memory 10 is shown in FIG. In this figure, FMP and Mu are upper keys U
This is an upper key area in which K key data is stored. The key data is a combination of pitch data and on / off data of the key. In addition, FMP ・ Ml is a lower key area where the key data of the lower key is stored, FMP ・ M
p is a pedal key area where the key data of the pedal key is stored, FMP • Ms is a solo key area where the key data of the solo key is stored, and FMP • Mr is a registration data area where the registration data is stored. In this case, the upper key area FMP / Mu is 8K bytes and the other areas are 6K each.
It is composed of bytes and has a total capacity of 32 Kbytes.

Upper Key Area FMP / Mu, Lower Key Area FMP / M
l, pedal key area FMP / Mp. solo key area FMP / Ms and registration data area FMP / Mr are respectively pointer P
The addresses designated by u, Pl, Pp, Ps, and Pr are designed to be accessed, and the starting addresses of the areas are 0, n ₁ , n ₂ ...

(Ii) Switch FMP / PLY The switches FMP / PLY are switches that are operated when performing an automatic performance based on the performance data stored in the performance data memory 10. When this switch FMP / PLY is pressed,
The CPU 1 sequentially reads the performance data from the performance data memory 10 and supplies it to the musical sound generating circuit 12 and the rhythm sound generating circuit 13. The tone generation circuit 12 is composed of Upper Key UK and Lower Key LK.
It is a circuit for generating musical tones corresponding to these based on the ON / OFF information of each key such as .. and the ON / OFF information of the tone color selection switch. The rhythm sound generation circuit 13 is a circuit that creates a rhythm accompaniment with the rhythm specified by the rhythm selection switch and with the tempo specified by the tempo specification volume or the like. The output signals of the tone generation circuit 12 and the rhythm sound generation circuit 13 are amplified by the amplifier 14 and then supplied to the speaker 15.

(Iii) Switch SAVE The switch SAVE is a switch operated when the performance data in the performance data memory 10 is transferred to the external memory (hereinafter referred to as RAM pack) 20. When the switch SAVE is pressed, the CPU 1 transfers data according to the processing described later. The RAM pack 20 is removable from the body of the electronic musical instrument, and is a non-volatile RAM that uses a backup battery.
(Random access memory).
The RAM packs in this example are 8K bytes and 3
Two types of 2K bytes are now being used.

(Iv) Switch LOAD The switch LOAD is a switch operated when writing the performance data in the RAM pack 20 to the performance data memory 10. When this switch LOAD is pressed, the CPU 1 causes the RAM pack 2
The performance data in 0 is sequentially transferred to the performance data memory 10.

Further, light emitting diodes 7, 7 ... Which are turned on when the switch is on are provided near the respective switches.

The above is the configuration of this embodiment.

(1-2) Operation of the Embodiment Next, the operation of this embodiment having the above configuration will be described.

Switch Scan Processing First, the CPU 1 starts operation from step SP1 shown in FIG. 4, and then moves to step SP2 to perform initialization processing of each memory and register. Next, switch FMP / REC, FMP
Check if these switches are pressed in the order of PLY, FMP / SAVE, FMP / LOAD (steps SP3 to SP6). If none of these switches are pressed, move to step SP7 After performing the process of, the process returns to step SP3. After that, step until one of the above switches is pressed.
A loop consisting of SP3 to step SP7 is cycled.

Then, when the switch FMP / REC is pressed while circulating through the above loop, the CP1 turns on the light emitting diode 7 provided in the vicinity of the switch FMP / REC, and then moves to the FMP / REC processing routine LU1. The performance data corresponding to the actual performance of is stored in the performance data memory 10.

In the same way, switch FMP / PLY, FMP / SAVE, FMP /
When LOAD is pressed, the light emitting diodes 7 near each
After turning on, the FMP / PLY processing routine LU2, the SAVE processing routine LU3, and the LOAD processing routine LU4 are executed.

Next, each of the above processing routines LU1 to LU4 will be described.

FMP / REC processing routine LU1 First, one bar is divided into n by a timer circuit (not shown) or a timer function by software processing, and “0” is set at the beginning of the bar and “n−1” is set at the end of the bar. For example, n = 19
If it is 2, timing data is created with "0" at the beginning of the bar and "191" at the end of the bar.

Then, when there is a change in the operation of the key, that is, when the key is turned on or off (hereinafter, the change in the key operation is referred to as an event), the storage area of the key having the event (shown in FIG. 3). FMP / Mu, FMP / Ml ... (see the timing data at that time), and
The pointer is incremented by 1 and the key data of the key is written. For example, when an event occurs in the upper key UK, the timing data when the event occurs is written in the address of the upper key area FMP · Ml pointed to by the pointer Pu, and then the pointer Pu is incremented by 1 to the next Write the key data (pitch data and on / off data) at the address.

Then, the above processing is similarly performed for each key and the registration information, and the performance data is stored in the performance data memory 10. At the end of the performance data in each storage area, data END indicating the end of the data is written as shown in FIG.

It should be noted that the vertical line dividing the bar is also taken in as data.

FMP / PLY processing routine LU2 This processing is a processing for reading the performance data in the performance data memory 10 to generate musical tones, and for each area in the performance data memory 10, data is sequentially read from the head address.
This process is as follows.

First, the timing data is read from the address indicated by the pointer (Pu, Pl ...), and this timing data is loaded into the timing register set in the working area 3. Next, the pointer is incremented by 1 to read the key data, and this key data is loaded into the key data register in the working area 3. Then, when the count value of the timer counter for counting the tempo clock and the timing data in the timing register match, the key data in the key data register is read and supplied to the tone generating circuit 12 to generate a tone.

Next, the pointer is incremented, new timing data and new key data are read out and loaded into the timing register and the key data register, respectively. Then, when the value of the timer counter matches the value in the timing register, the sounding process similar to the above is performed. Thereafter, similarly, the timing data and the key data are read from the performance data memory 10 as a pair, and when the values in the timer counter and the timing register match, the tone generation processing is sequentially performed.

SAVE processing routine LU3 As shown in FIG. 4, the SAVE processing routine LU3 is composed of a check processing routine LU3a and a data transmission processing routine LU3b which is performed subsequent to this processing. at first,
The check processing routine LU3a will be described.

(I) Check Processing Routine LU3a FIG. 5 is a flowchart showing the check processing routine LU3a. As shown in this flowchart, when the SAVE switch is pressed, the LEDs in the vicinity of the switch are turned on, and the pointers Pu, Pl, Pp, and Ps each have an initial value, that is, “0”, “n ₁ ”, “n”. Set ₂ ”,“ n ₃ ”, and“ n ₄ ”. Also, the register DSP and the flag OVR set in the working area 3 are cleared (step SP10). Next, in step SP11, the capacity of the RAM pack connected to the main body is checked. In this capacity check process, as shown in FIG. 6, first, it is judged whether or not the RAM pack 20 is properly connected to the main body (step SP1).
2). This determination processing is performed by checking the terminal voltage of the RAM pack 20. If the connection state of the RAM pack 20 is bad, the process moves from step SP12 to step SP13 to display the fact that the connection of the RAM pack 20 is bad on the display unit 4 (FIG. 1), and then the switch scan processing routine ( (Fig. 4)
Return to. On the other hand, when the connection of the RAM pack 20 is normal, the process proceeds to step SP14 and it is determined whether the capacity of the RAM pack 20 is S ₁ or S ₂ . In this embodiment, S ₁ = 8K and S ₂ = 32K, and the capacity is determined by observing the voltage value of a predetermined terminal of the RAM pack 20. If the capacity is S ₂ , the process proceeds to step SP15 and S ₂ is substituted into the register S, and the capacity is
Performs a process of substituting S ₁ if S ₁ proceeds to step SP16 to register S. Then step SP15 or step SP
After performing the process of 16, the process returns to the process routine shown in FIG. 5 and proceeds to step SP17.

In step SP17, it is determined whether or not the data in the upper key area FMP · Mu indicated by the pointer Pu is the data END. If it is not the data END, the process proceeds to step SP18, the pointer Pu is incremented by 1, and the determination in step SP17 is performed again. To do. After that, the loop consisting of steps SP17 and SP18 is circulated until the data END is detected in step SP17. When the data END is detected in step SP17, the process proceeds to step SP19 and the register DSP (Pu
The value +1) is substituted. In this case, since the start address of the upper key area FMP · Mu is “0”, the calculation result in step SP19 is the upper key area FMP.
-It is a value that indicates the amount of data (number of bytes) of Mu. Therefore, when step SP19 ends, the register
A value indicating the data amount of the upper key area FMP / Mu is assigned to the DSP.

Next, in steps SP20 and 21,
Lower key area designated by pointer P1 as in 18
The process of incrementing the content of the pointer Pl is performed until the data of FMP · Ml becomes the END data. Then, when the END data is detected in step SP20, the operation proceeds to step SP21, the operation of DSP + (Pl + n ₁ +1) is performed, and the operation result is substituted into the register DSP. In this case, the value of (Pl−n ₁ +1) is a value indicating the data amount in the lower key area FMP · Ml, as can be seen from FIG. Therefore, the register DSP after the processing of step SP22
The content of is a value indicating the sum of the data amounts in the upper key area FMP / Mu and the lower key area FMP / Ml.

Next, in the loop consisting of steps SP23 and SP24,
In the same way as above, the amount of data in the pedal key area FMP / Mp is detected, and this value is registered in step SP25.
It is added in DSP. Then, in the loop consisting of steps SP26 and SP27, the amount of data in the solo key area FMPMS is detected, and this value is registered in step SP28.
The amount of data in the registration data area FMP / Mu is detected in the loop consisting of steps SP29 and SP30, and this value is registered in step SP31.
It is added in DSP. As a result, the content of the register DSP after the processing of step SP31 becomes the content indicating the total amount of data in each data area. Here, the area DE shown in FIG. 3 is a visual representation of the total amount.

Further, in step SP31, the contents of the register DSP,
That is, the total amount of performance data is displayed on the display unit 4.

Next, in step SP32, it is determined whether or not the content of the register DSP is larger than the content of the register S. At this time,
The register S is set to S ₁ by the processing of steps SP15 and SP16.
Either (8K) or S ₂ (32K) is assigned. If the total amount of performance data in the register DSP is larger than the above numerical value, the determination in step SP32 is "YES".
And then proceed to step SP33. The following processing is performed in step SP33.

○ Flag OVER is set to "1". I.e. step
If the SP32 judgment is "YES", the performance data memory 1
When the performance data in 0 is transferred to the RAM pack 20, it may overflow, so "1" is set to the flag OVER indicating overflow.

The calculation {(DSP-S) / S} * 100 is performed, and the calculation result is assigned to the register DSP. The result of this calculation is a value indicating what percentage overflows the capacity of the RAM pack 20.

Display the overflow rate, which is the calculation result of the above processing, on the display unit 4. The display in this case alternates with the display in step SP31 at 1 second intervals. When the display space of the display unit 4 is large, both are statically displayed.

○ Generate a warning sound. This is to inform the operator that the RAM pack 20 cannot save all performance data.

The above is the process in step SP33, and after this process, the process returns to the main routine via step SP34. That is, the data transmission processing routine LU3b is entered.

On the other hand, if "NO" is determined in step SP32, it means that the overflow of the performance data does not occur. Therefore, the process of step SP33 is not performed, and the data transmission process routine is executed from step SP32 to step 34. Enter LU3b.

(Ii) Data Transmission Processing Routine LU3b Next, the data transmission processing routine LU3b will be described.

When the data transmission processing routine LU3b is entered, pointers Pu, Pl,
Pp, Ps, and Pr are set to the initial values, respectively, and the pointer P indicating the data transfer destination set in the working area 3 is cleared (steps SP40 and SP41). Next, in step SP42, the performance data memory 10 is set to the read mode and the RAM pack 20 is set to the write mode.
Then, the process proceeds to step SP43, it is determined whether the data indicated by the pointer Pu is data END, and if "NO", step S
Moving to P44, the data in the performance data memory indicated by the pointer Pu (in this case, the data in the upper key area FMP · Mu) is transferred to the address in the RAM pack 20 indicated by the pointer P. After this transfer, the pointer P and the pointer
After incrementing each pu by 1, it proceeds to step SP43. After that, the loop consisting of steps SP43 and SP44 is circulated until the determination in step SP43 becomes “YES”. Due to the circulation operation of this loop, the upper key area
The data from the address "0" in the FMP / Mu to the position before the end data END is transferred to the RAM pack 20. Then, when the determination in step SP43 becomes "YES", the process proceeds to step SP45, and the RAM pack 20 indicating the end data END is indicated by the pointer P.
Then, the pointer P is incremented by 1 and the process proceeds to step SP46.

In step SP46, it is determined whether or not the data in the lower key area FMP · Ml indicated by the pointer Pl is the end data END, and if it is not the end data END, the process moves to step SP47 and the RAM indicated by the pointer P in the RAM indicated by the pointer P. Transfer to the address in pack 20. After the transfer, the pointer Pl and the pointer P are both incremented by 1, and the process proceeds to step SP48. In step SP48, RAM pack 2
It is determined whether 0 is fully paid. If such a judgment is made, if the RAM pack 20 is 8 Kbytes, there is a possibility that the RAM pack 20 will be fully distributed during data transfer in the lower key area FMP / Ml. This is because. When transferring the data in the above-mentioned upper key area FMP / Mu, the judgment as in step SP48 is not made, but this is because the capacity of the upper key area FMP / Mu is 8 Kbytes and the RAM pack 20 is fully distributed. This is because there is no possibility that If the determination in step SP48 is "NO", the process moves to step SP46 again, and thereafter, steps SP46 and SP47 are performed until the end data END is detected or the RAM pack 20 is fully distributed. , Through a loop consisting of SP48. By this loop circulation operation, the data in the lower key area FMP · Ml is transferred to the RAM pack 20. When the RAM pack 20 is fully distributed during the loop circulation, the determination in step SP48 is "YES", and step SP5
After moving to 0 and displaying an error on the display unit 4, the switch scan processing routine (the fourth routine) which is the main routine is performed.
Return to Figure). In this way, when the RAM pack 20 becomes full lung during data transfer in the lower key area FMP / Ml,
An error message will be displayed and the data will not be transferred.

On the other hand, RAM during data transfer in the lower key area FMP / Ml
If the pack 20 is not fully distributed, data transfer is performed until end data END is detected in step SP46,
As a result, all the data in the lower key area FMP / Ml is R
Transferred into the AM pack 20.

When the end data END is detected in step SP46, the process proceeds to step SP49 to transfer the end data END to the address in the RAM pack 20 indicated by the pointer P, and then the pointer is incremented by 1.

Next, similarly to the case of data transfer in the lower key area FMP / Ml, data transfer in the pedal key area FMP / Mp is performed in a loop consisting of steps SP51, SP52, SP53, and step SP55, Data transfer in the solo key area FMP / Ms is performed by the loop consisting of SP56 and SP57. In this case, if the RAM pack 20 is fully distributed during the transfer of each data, the determination in step SP53 or step SP57 becomes "YES", and the process returns after displaying an error (steps SP50, SP64). The processing of steps SP54 and SP58 is the same as the processing of step SP45 described above.

After the data transfer in each area mentioned above is done well,
In step SP59, it is determined whether the flag OVR is set to "1". If this determination is "YES", the process moves to step SP60, the display section 4 displays the SAVE end, the warning sound is stopped, and the process returns (step SP64). That is, when the flag OVR is “1”, it is known in advance that the RAM pack 20 will overflow, and therefore, the process returns to the main routine without transferring the registration data.

On the other hand, when the flag OVR is “0”, the data in the registration data area FMP · Mr is transferred to the RAM pack 20 by the loop including steps SP61 and SP62. When the end data END is detected in step SP61, the process moves to step SP63 to transfer the end data END to the address indicated by the pointer P, and thereafter, in step SP60, the SAVE end display is performed and the process returns to the main routine.

The above is the contents of the SAVE processing in this embodiment. According to the above processing, even when the RAM pack 20 overflows, if the transfer-disabled data is only the registration data, other data is transferred as it is and the SAVE processing is ended. In this case, since the registration data is data related to the tone color of the musical tone, the tone color information cannot be transferred, but the data related to the key information can be transferred.
The automatic performance based on the data in the pack 20 will not be disabled.

On the other hand, if there is transfer-disabled data other than the registration data, an error message is displayed to inform the operator that transfer is not possible. The operator sees this display and the display of the overflow rate in step SP33, performs the performance to reduce the performance data again, stores the performance data in the performance data memory 10, and performs the SAVE processing again with the new performance data. You can

In the above process, the read operation is performed for each area of the performance data memory 10.
For 0, data writing is performed sequentially from the head address.

LOAD Processing Routine LU4 Next, the LOAD processing routine will be described.

Since the capacity of the performance data memory 10 is 32 Kbytes as described above and is equal to or larger than the amount of data in the RAM pack 20, the processing such as the check processing LU3a described above is unnecessary, and the RAM pack 20 If the connection status of is normal,
Immediately perform LOAD processing (data import processing). This LOAD processing is performed as follows.

That is, the data is sequentially loaded from the head address of the RAM pack 20 to the upper key area FMP / Mu. When the end data END is detected, the lower key area FMP
Data is taken into Ml, and then end data EN
Each time D is detected, the data acquisition area is switched and the data in the RAM pack 20 is read. By performing this operation, all the performance data in the RAM pack 20 is transferred to the performance data memory 10.

The above is the operation of the first embodiment of the present invention.

(2) Second Embodiment Next, a second embodiment of the present invention will be described. Second
This embodiment is different from the above-described first embodiment only in the check processing routine LU3a, and this processing will be described below with reference to FIG.

First, the processing is started from step SP70, and in step 71, the pointer Pf, the register N and the DSP are cleared. Here, the pointer Pf and the register N are respectively set in the working area 3 in this embodiment, and the pointer Pf points the access address in the performance data memory.

Next, in step SP72, the capacity check process of the RAM pack 20 is performed. This process is exactly the same as the process shown in FIG. When the processing of step SP72 is completed, the process moves to step SP73 and the data indicated by the pointer Pf is the end data.
It is determined whether it is END. If this determination is "NO", the loop consisting of step SP73 and step SP74 is circulated until the determination becomes "YES", and the pointer Pf is incremented. That is, the upper key area FMP · Mu is accessed sequentially from the address “0”. And step
When the end data END is detected in SP73, the process proceeds to step SP75, the register N is incremented by 1, and the value is set to "1". Next, when proceeding to step SP76, N =
Whether it is 1 or not is determined, the determination result is "YES", and the routine proceeds to step SP77. In step SP77 (Pf + 1)
Then, the calculation result is substituted into the register DSP. The value of register DSP at this time is the upper key area FMP
-Since it corresponds to the address of the end data END of Mu, the calculated value (Pf + 1) indicates the data amount of the upper key area FMP-Mu. In step SP77, n ₁ which is the head address of the lower key area FMP · Ml is assigned to the pointer Pf. Then, when the processing of step SP77 ends, steps SP73 and SP
Circulating a loop consisting of 74, lower key area FMP · Ml
Are sequentially accessed from the _first address "n ₁ ". When the end data END is detected, the value of the register N is increased to "2" in step SP75, and the step SP
Step SP79 is reached via 76 and SP78 (DSP + Pf-n ₁ +
1) is performed to sum the data amounts in the upper key area FMP · Mu and the lower key area FMP · Ml, and the calculated result is assigned to the register DSP.

After that, the data amount in each area is sequentially accumulated in the same manner as the above processing (steps SP81, SP83, SP8).
Four). Then, when the processing of step SP84 is performed, the total value (the number of bytes) of the performance data is substituted in the register DSP. The process of step SP85 is performed after this step SP84, and the process of step 84 is the process consisting of steps SP32 and SP33 shown in FIG. 5 described above. That is, the overflow rate is displayed and the flag OVER is written.

The above is the processing in the second embodiment. According to this embodiment, as can be seen from FIG. 8, there is an advantage that the pointer used in the checking process is only the pointer Pf.

(3) Third Example Next, a third example will be described.

In this embodiment, when the end data END is written in each area shown in FIG. 3 in the FMP / REC processing,
A preset end address data memory 30 (first
(See Fig. 10), write the data amount of each area. That, (Pu + 1), ( Pl-n 1 +1), (Pp-n 2
+1), (Ps-n ₃ +1), and (Pr-n ₄ +1) values as data De ₀ , De ₁ , De ₂ , De ₃ , respectively, as shown in FIG. Address "0" to "4"
Write in. Further, the end address data END is written in the address “5” of the end address data memory 30.

Then, as the check processing routine LU3a, the processing shown in FIG. 9 is performed.

First, the processing is started from step SP90, and a predetermined light emitting diode is turned on at step SP91, and a pointer Pe and a register RD for storing end address data are stored.
E, display register DSP, and flag OVR are cleared. Here, the pointer Pe is a pointer for pointing the access address of the end address data memory 10, as shown in FIG. Then move to step SP92, RAM
The capacity check process of the pack 20 is performed. This process is the sixth
The processing is exactly the same as the processing shown in the figure. Then, the process moves to step SP63 and the data indicated by the pointer Pe is the end data EN.
Determine if D. If this determination is “NO”, the flow shifts to step SP94, the value of the data indicated by the pointer Pe is added to the register RDE, and then the pointer Pe is incremented by 1, and the flow returns to step SP93. After that, until the end data END is detected in step SP93, step SP93,
Cycle through a loop consisting of SP94. Therefore, during the circulation of this loop, the data in each address shown in Fig. 10 is
De ₀ , De ₁ , De ₂ and De ₃ are sequentially accumulated. Then, when the end data END is detected in step SP93, the process proceeds to step SP95, and the contents of the register RDE is substituted into the register DSP. According to the processing of this step SP95, the register
A value corresponding to the total amount of data in the performance data memory 10 is substituted in the DSP. Here, if necessary, register DS
The contents of P are displayed on the display unit 4. Next, move to step SP96, and the processing of this step is the step shown in FIG.
The processing is the same as SP32 and step SP33.

The above is the main processing of the third embodiment, and is the same as the above-described first embodiment except for the above processing. This embodiment has the advantage that the checking process is performed at extremely high speed, as can be seen from the flowchart shown in FIG.

In the above embodiment, the display of the contents of the register DSP in step SP95 may be omitted.

(4) Fourth Example Next, a fourth example will be described.

In this embodiment, unlike the above-mentioned first to third embodiments, the memory map of the performance data memory 10 is set as shown in FIG. In this figure, the area indicated by FMP · Mf is an area where the key data is stored, and the head address is the address “0”. In addition, FMP ・ M
The area indicated by r is an area where the resist data is stored, and the head address is "n".

Then, the FMP / REC processing is performed as follows. First,
When a key event occurs, write the timing to the key data area FMP · Mf, then set the pointer P _F to 1
Advance to write part data, on / off data, and pitch data (1 byte in total). Here, the part data is an upper key, a lower key ...
It is data showing parts such as. This writing process
Do it every time an event occurs. The registration data is also written in the same manner as the case of the key data.

Next, the SAVE processing of this embodiment will be described with reference to the flowchart shown in FIG.

When the operation starts from step SP100, step SP101
At the same time as turning on the predetermined light emitting diode,
The pointer P _F , the flag OVR, and the register DSP are cleared, and n is assigned to the pointer Pr. Then, step SP102
After performing the capacity check process of the RAM pack 20 (see FIG. 6), the process proceeds to step SP103 to determine whether P _F > k. The capacity value of the RAM pack 20 has already been assigned to S in this determination. If the determination in step SP103 is "NO", the process moves to step SP104 and it is determined whether the data indicated by the pointer P _F is the end data END. If this determination is "NO", step SP10
The process moves to step 5, the pointer P _F is advanced by 1, and the process moves to step SP103 again. After that, the loop 11 is circulated until it becomes “YES” in step SP103 or step SP104. If the determination in step SP103 is "YES" during the loop l1 circulation, an error is displayed in step SP106, and then the process returns to the main routine (step SP107). The determination in step SP103 is a process of determining whether or not the data amount of the key data area FMP / Mf exceeds the capacity of the RAM pack 20. If it exceeds, it is determined that the performance data cannot be transferred and an error occurs. Display.

Further, when it is determined to be "YES" in step SP104 during the circulation of the loop l1, the calculation of (P _F +1) is performed and the calculation result is substituted into the register DSP. That is, the data amount of the key data area FMP · Mf is substituted. Then step S
In P109, the amount of data in the resist data area FMP · Mr is detected by substantially the same processing as steps SP104, SP105, and SP108 described above. Then, in step SP110, the same processing as in steps SP32 and SP33 shown in FIG. 5 is performed, and then in step SP111, the pointer is set.
P _F and P are cleared, and n is set in the pointer Pr. Next, after checking the connection state of the RAM pack 20 in steps SP112 and SP113, the process moves to step SP114 to set the performance data memory 10 in the read mode and the RAM pack 20 in the write mode. Then, by the loop of steps SP115 and SP116, the data in the key data area FMP · Mf is sequentially transferred from the head address of the RAM pack 20. When the end data is detected in step SP115, the process moves to step SP117 to transfer the end data END to the address indicated by the pointer P, and further advances the pointer P by 1. Next, in step SP118, the same processing as in steps SP59 to SP63 shown in FIG. 7 is performed, after which the process returns to the main routine (step SP64).

The above is the processing of the fourth embodiment. In this embodiment, step SP100 to step SP110 perform the check process.
Corresponding to LU3a, steps SP111 to SP118 correspond to data transmission processing LU3b.

(5) Modified Examples of Each Embodiment Next, various modified examples of each of the above embodiments will be described.

In each of the above embodiments, when the switch U, L, P, etc. is pressed after the switch FMP / REC is pressed, the storage of the part data corresponding to the pressed switch is excluded. Alternatively, when the switch FMP / REC is pressed, the write mode of the performance data memory 10 is enabled, and every time the switch U, L, P ... is pressed thereafter, the data of the part corresponding to the pressed switch is written. The storage may be added sequentially.

In each of the above-mentioned embodiments, the data to be preferentially transferred when the capacity of the RAM pack 20 is insufficient is the key data excluding the registration data, but which data is preferentially transferred may be arbitrarily set. For example, any one of the upper key data, the lower key data, the pedal key data, and the solo key data 1 to 3 may be set in advance so as to be preferentially transferred.

Further, the target of data transfer is not limited to the automatic performance data as in the above embodiments. For example, it may be configured as a system for transferring the tone color data (tone color parameter) of the musical instrument. That is, the data specifying each tone color of the upper key, the lower key, the pedal key, the solo key, and the rhythm sound source can be divided into groups, and any one of these groups can be set as the priority transfer data and the other as the truncated data. This case is particularly suitable when a small capacity RAM pack is connected.

When transferring grouped data to a RAM pack, that is, when transferring upper key data, lower key data, pedal key data, etc., the maximum data that can be transferred from the end data END address of each group. It is also possible to detect the number of groups. Note that such processing is easy as can be seen from the description of the embodiment. When the above processing is performed, extremely efficient data transfer can be performed according to the capacity of the RAM pack.

Further, as the data for grouping, it is also possible to divide the data for each song such as the performance data of the first song, the performance data of the second song .... In this case, the number of songs that can be transferred may be transferred.

Also, like the above, the first movement, the second movement in one song ...
Performance data for each movement may be divided into groups such as.

In the above-described embodiment, the overflow rate is displayed as a numerical value in percentage, but instead of this, a multicolor light emitting diode may be used as the display unit 4 to perform color overflow display. For example, yellow may be displayed when 100% is over, red may be displayed when 200% is over, and green may be displayed when 100% or less. Also during that time, for example,
If it exceeds 130%, it may be displayed as a specific color that continuously changes in color, such as an intermediate color between yellow and red.

[Effect of the Invention] As described above, according to the present invention, when the transfer instructing means instructs the transfer of the performance data stored in the internal storage means, the determining means determines the storage capacity of the external storage means, Since the transfer control means reads all of the performance data or a part of the performance data from the internal storage means according to the determined storage capacity and transfers the performance data to the external storage means, an external storage capacity smaller than the internal storage means. Even if the storage means is used, a transfer error does not occur and the performance data created for transfer is not wasted. Moreover, since it is possible to use a relatively inexpensive external storage means having a storage capacity smaller than that of the internal storage means, it is possible to reduce the cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention, FIG. 2 is a front view showing a panel surface in the same embodiment, and FIG. 3 is a memory map of a performance data memory 10 in the same embodiment, 4 is a flow chart showing a switch scan process in the same embodiment, FIG. 5 is a flow chart showing a check process routine in the same embodiment, FIG. 6 is a flow chart showing a RAM pack capacity check process in the same embodiment, and FIG. Is a flow chart showing a data transmission process in the same embodiment, FIG. 8 is a flow chart showing a check process in the second embodiment of the present invention, FIG. 9 is a flow chart showing a check process in the third embodiment of the present invention, FIG. 10 shows an end address data memory in the same embodiment.
30 is a memory map, FIG. 11 is a memory map of the performance data memory 10 in the fourth embodiment of the invention, and FIG. 12 is a flow chart showing the SAVE processing in the same embodiment. 1 ... CPU (central processing unit), 2 ... program memory, 3 ... working area (the above 1 to 3 are write control section, transfer control section), 5 ... key switch section (input key), 10 ... Performance data memory (internal storage means), 12 ...
… Sound generating circuit (sound signal generating means), 13 rhythm sound generating circuit (sound generating means), 20 RAM pack (external storage means), 30 end address data memory (transfer control section).

Claims (2)

[Claims] 1. An electronic musical instrument, which is provided in a main body of an instrument and has internal storage means for storing performance data, and external storage means detachably attached to the main body of the musical instrument, for instructing transfer of the performance data. A transfer instructing means, a determining means for determining a storage capacity of the external storage means when transfer is instructed by the transfer instructing means, and the performance from the internal storage means according to the storage capacity determined by the determining means. An electronic musical instrument comprising: a transfer control means for reading out all the data or a part of the performance data and transferring the data to the external storage means. 2. The performance data comprises at least key operation data corresponding to a performance operation and registration data representing an attribute of a musical tone to be generated, and a part of the performance data is composed of the performance data. The electronic musical instrument according to claim 1, wherein the registration data is excluded.