JPH0690680B2 - Information processing equipment - Google Patents

Description

TECHNICAL FIELD The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus equipped with a small-capacity random access memory (hereinafter referred to as RAM) that can be read and written by a microprogram.

Conventional Technology Conventionally, this type of information processing device has a small amount of RAM and
It is composed of a register for holding information to be written in AM and an address register for holding this RAM address, and the information held by the register is written as it is at the RAM address designated by the address register.

In such a conventional information processing apparatus, since the information held in the register is written as it is at the RAM address designated by the address register, the information written in the RAM depends on the operation mode of the information processing apparatus. When modified, only the information to be modified is required, and the original information is not required, but the RAM capacity is required for the number modified according to the operation mode, etc. Has the drawback of decreasing

Also, when the microprogram tries to read or write information that is modified by the operation mode to the RAM, the microprogram must determine the modification conditions such as the operation mode and then determine the RAM address. There is a drawback in that reading and writing cannot be performed, which causes a decrease in performance.

OBJECT OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks of the related art, and can reduce the capacity of RAM, reduce the number of microprogram steps, and improve performance. It is intended to provide a processing device.

Configuration of the Invention An information processing apparatus according to the present invention is a readable / writable storage unit, a storage unit for temporarily storing write information for writing in the storage unit, and an address for temporarily storing an address supplied to the storage unit. An information processing device having a storage means, which decodes an address stored in the address storage means and outputs modification information for modifying the write information and an operation instruction for the modification, and a decoder. An arithmetic means for performing arithmetic operation on the write information and the modification information based on the arithmetic instruction from the decoder is provided, and an arithmetic result from the arithmetic means is designated by the address stored in the address storage means. It is characterized in that the data is written in the address of the storage means.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, one embodiment of the present invention comprises a small capacity random access memory (hereinafter referred to as RAM) 1, a register 2, an address register 3, a decoder 4 and an arithmetic circuit 5. RAM1 is composed of 512 words (one word is 32 bits), and is a RAM that a microprogram can read and write. Register 2
Is a 32-bit register that holds information to be written to the RAM 1 input via the input line 10. The address register 3 is a register for holding an address which is input via the signal line 11 for reading and writing the RAM 1, and is composed of 8 bits.

The register 2 and the address register 3 can be controlled not only by hardware but also by a micro program.

Whether the decoder 4 is valid or invalid is controlled according to the operation mode of the information processing device, and the RAM 1 held by the address register 3 is controlled.
Is decoded, and the data and the operation instruction corresponding to this address are output as shown in FIG. The arithmetic circuit 5 is RA held by the register 2.
The information to be written to M1 and the data output from the decoder 4 and used to modify the information held in the register 2 are input, and an operation based on the operation instruction output from the decoder 4 is performed. Write to RAM1.

The output of the arithmetic circuit 5 is held in the address register 3.
Written to RAM1 address.

FIG. 2 is a diagram showing the contents of the output with respect to the input to the decoder 4 of FIG. In the figure, the decoder 4 is a signal line 1
According to the contents of the address and the operation mode respectively inputted via 2, 13, the data and the contents of the arithmetic instruction are outputted to the arithmetic circuit 5 through the signal lines 15, 16.

FIG. 3 is a diagram for explaining the operation of one embodiment of the present invention. In the figure, the contents stored in the register 2 and the address register 3 are shown for each case.

Next, the operation of the embodiment of the present invention will be described with reference to FIGS.

In case 1, register 2 has a hexadecimal value of "00002100"
(“” Represents a hexadecimal number) is held, and this data is input to the arithmetic circuit 5 via the signal line 14. At this time, the address register 3 holds the hexadecimal "00" address, and this address is RA through the signal line 12.
It is input to M1 to indicate a write address and is supplied to the decoder 4 as an address for decoding.

The decoder 4 receives the address "00" supplied via the signal line 12 and the binary "0"(", which is the operation mode of the information processing device supplied via the signal line 13, represents a binary number. ) Is input, decoding is performed based on the contents shown in FIG. Since the operation mode of the information processing apparatus is binary '0', the decoder 4 outputs the hexadecimal signal via the signal line 15 regardless of the address supplied from the address register 3 via the signal line 12. “00000000” is output to the arithmetic circuit 5, and at the same time, the arithmetic instruction of “logical sum” is transmitted to the arithmetic circuit 5 via the signal line 16.

The arithmetic circuit 5 receives the hexadecimal "0000" supplied via the signal line 14.
2100 "and hexadecimal“ 00000 ”supplied via signal line 15.
000 "is logically ORed in accordance with the" logical OR "operation instruction instructed via the signal line 16, and the operation result is output to the RAM 1 via the signal line 17. The calculation result input via the signal line 17 is written in the address of the RAM 1 held in the address register 3.

That is, when the operation mode of the information processing device is binary '0' as in case 1, the information held in the register 2 is written as it is to the address of the RAM 1 held in the address register 3. Be done.

In case 2, register 2 has a hexadecimal value of "00002100"
Is held, and this data is input to the arithmetic circuit 5 via the signal line 14. The address register 3 holds a hexadecimal "00" address. This address is input to the RAM 1 via the signal line 12 to indicate a write address, and is also used as an address for the decoder 4 to perform decoding. Supplied.

Decoder 4 is a hexadecimal "00" supplied via signal line 12
By inputting an address and a binary "1" which is the operation mode of the information processing apparatus and is supplied via the signal line 13, decoding is performed based on the contents shown in FIG.

Since the operation mode of the information processing device is binary '1', the hexadecimal address "00" supplied via the signal line 12 becomes significant as the decode information, and the signal line 15 from the decoder 4 is connected. The hexadecimal “7FFFE000” is output to the arithmetic circuit 5 via the signal line 16 and the arithmetic instruction of “logical product” is transmitted to the arithmetic circuit 5 via the signal line 16.

The arithmetic circuit 5 receives the hexadecimal "0000" supplied via the signal line 14.
Hexadecimal "7FFFE000" supplied via 2100 "and signal line 15
And are logically ANDed by a “logical AND” operation instruction instructed via the signal line 16 and the operation result is input to the RAM 1 via the signal line 17. The calculation result input via the signal line 17 is written in the address of the RAM 1 held in the address register 3.

That is, the hexadecimal result "00002000" is written to the address "00" of RAM1.

In case 3, register 2 is hexadecimal "FFFFF000"
Is held and this data is input to the arithmetic circuit 5 through the signal line 14. Address register 3 has a hexadecimal "0"
The 1 "address is held, and this address is the signal line
It is input to the RAM 1 via 12 to indicate a write address and is supplied to the decoder 4 as an address for decoding.

The decoder 4 is a hexadecimal "01" supplied via the signal line 12.
And the binary '1' which is the operation mode of the information processing apparatus and is supplied via the signal line 13 are decoded based on the contents shown in FIG.

Since the operation mode of the information processing device is binary '1', the address of hexadecimal "01" supplied via the signal line 12 becomes significant as the decoding information, and via the signal line 15
Hexadecimal “00000800” is output to the arithmetic circuit 5, and at the same time, the arithmetic instruction of “logical sum” is sent to the arithmetic circuit 5 via the signal line 16.

The arithmetic circuit 5 is a hexadecimal "FFFF supplied via the signal line 14.
F000 "and hexadecimal" 0000080 "supplied via signal line 15
"0" is logically ORed by a "logical OR" operation instruction instructed via the signal line 16, and the operation result is output to the RAM 1 via the signal line 17. The calculation result input via the signal line 17 is written in the address of the RAM 1 held in the address register 3.

That is, the hexadecimal result "FFFFF800" is written to the address "01" in RAM1.

In case 4, the register 2 has a hexadecimal number "03FFC200".
Is held, and this data is input to the arithmetic circuit 5 via the signal line 14. The address register 3 holds a hexadecimal "02" address. This address is input to the RAM 1 via the signal line 12 to indicate a write address, and is also used as an address for the decoder 4 to perform decoding. Supplied.

The decoder 4 is a hexadecimal "02" supplied via the signal line 12.
And the binary '1' which is the operation mode of the information processing apparatus and is supplied via the signal line 13 are decoded based on the contents shown in FIG.

Since the operation mode of the information processing device is binary '1', the hexadecimal address “02” supplied via the signal line 12 becomes significant as the decode information, and the signal via the signal line 15
Hexadecimal "00001000" is output to the arithmetic circuit 5, and the arithmetic instruction of "arithmetic addition" is sent to the arithmetic circuit 5 through the signal line 16.

The arithmetic circuit 5 is a hexadecimal "03FF supplied via the signal line 14.
C200 "and the hexadecimal" 0000100 "supplied via signal line 15
0 "and arithmetic addition operation are performed according to the operation instruction of" arithmetic addition "instructed via the signal line 16, and the operation result is signal line.
Output to RAM1 via 17. The operation result input via the signal line 17 is written in the address of the RAM 1 held in the address register 3.

That is, the hexadecimal result "03FFD200" is written to the address "02" of RAM1.

In case 5, register 2 has a hexadecimal number "03F00000"
Is held, and this data is input to the arithmetic circuit 5 via the signal line 14. The address register 3 holds a hexadecimal “03” address. This address is input to the RAM 1 via the signal line 12 to indicate a write address, and is also used as an address for the decoder 4 to perform decoding. Supplied.

Decoder 4 is a hexadecimal "03" supplied via signal line 12
And the binary '1' which is the operation mode of the information processing apparatus and is supplied via the signal line 13 are decoded based on the contents shown in FIG.

Since the operation mode of the information processing device is binary '1', the hexadecimal "03" address supplied via the signal line 12 becomes significant as decode information, and via the signal line 15
Hexadecimal "00000000" is output to the arithmetic circuit 5, and the arithmetic instruction of "logical sum" is transmitted to the arithmetic circuit 5 through the signal line 16.

The arithmetic circuit 5 is a hexadecimal “03F0” supplied via the signal line 14.
0000 "and the hexadecimal" 0000000 "supplied via signal line 15
"0" is logically ORed by a "logical OR" operation instruction instructed via the signal line 16, and the operation result is input to the RAM 1 via the signal line 17. The calculation result input via the signal line 17 is written in the address of the RAM 1 held in the address register 3.

That is, the hexadecimal result "03F00000" is written to the address "03" in RAM1.

In this way, the address held in the address register 3 is decoded by the decoder 4, and the RAM 1 from the decoder 4 is decoded.
The operation circuit 5 performs an operation on the basis of the modification information for modifying the write information to the memory and the operation instruction for this modification, and the operation result is stored in the address of the RAM1 designated by the address held in the address register 3. By writing, when the information written to RAM1 is modified by the operation mode of the information processing device, it is not necessary to have the same number of information modified by the operation mode, and the only information (operation Since we only need to store the (result),
The capacity of RAM1 can be reduced.

In addition, since the information modified by the operation mode is the only information in RAM1, the microprogram does not need to judge the operation mode and determine the address of RAM1 when reading and writing. The number of steps can be reduced and the performance can be improved.

Although the operation mode of the information processing device is used as the validity confirmation signal in the decoder 4 in the embodiment of the present invention,
It is obvious that this operation mode can be used as a part of the input data (for example, added to the upper part of the address).

As described above, according to the present invention, the address supplied to the RAM is decoded, the modification information and the operation instruction for modifying the write information to the RAM are obtained, and the operation instruction is based on the operation instruction. By writing the calculation result of the write information and the modification information to the relevant address of the RAM, the capacity of the RAM can be reduced, the number of steps of the microprogram can be reduced, and the performance can be improved. There is an effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the contents of output with respect to the contents of input in the decoder of FIG. 1, and FIG. 3 is a diagram for explaining the operation of the embodiment of the present invention. FIG. Description of symbols of main parts 1 ... RAM 4 ... Decoder 5 ... Operation circuit

Claims (1)

[Claims] 1. Information having a readable / writable storage means, a storage means for temporarily storing write information for writing in the storage means, and an address storage means for temporarily storing an address supplied to the storage means. A processing device, a decoder for decoding an address stored in the address storage means to output modification information for modifying the write information and an operation instruction for the modification, and the operation from the decoder Arithmetic means for arithmetically operating the write information and the modification information based on an instruction is provided, and the arithmetic result from the arithmetic means is stored in the address of the storage means specified by the address stored in the address storage means. An information processing device characterized by being written.