JPH0690681B2 - Cache memory control method - Google Patents

Description

DETAILED DESCRIPTION [Overview] A cache memory control method in which a plurality of main memory read ports are used for prefetching, and it is possible to perform a desired number of prefetches within a maximum allowable number of block fetches. A plurality of main memory read ports for the purpose of enabling to enter the next block fetch processing before the completion of the preceding block fetch, and the main memory device via the main memory read port in response to the block fetch request. In a cache memory control method for transferring data between a cache memory and a cache memory, a prefetch request signal generation circuit, a prefetch activation circuit, a prefetch remaining number output circuit, and a signal repetition output circuit are provided to generate a prefetch request signal. A plurality of prefetch operations are performed in response to a sequential signal from the circuit. It constructed as give rise via a main memory read port.

[Industrial application field]

The present invention relates to a cache memory control method in an information processing apparatus having a cache memory of a store-through method or a swap method, which holds a copy of a part of the contents of a main storage device (MS), and particularly to the information processing apparatus. Block for the main memory (MS) when a mishit occurs in response to an instruction fetch request from the instruction unit (I unit) in the central processing unit (CPU), an operand fetch request, etc. Control method for the prefetch request of.

The access time to the cache memory in the central processing unit (CPU) of the information processing device is very large due to the trend of increasing the capacity of the main memory (MS) accompanying the recent remarkable progress in semiconductor technology. Tends to become.

On the other hand, with the increase in the processing amount of the information processing apparatus and the diversification, the demand for the improvement of the processing capacity of the information processing apparatus is increasing more and more. In order to improve the performance, it is necessary to efficiently transfer valid data from the main storage device (MS) into the cache memory with a short access time.

[Conventional technology]

FIG. 6 is a schematic diagram of an information processing apparatus having a cache memory.

An information processing apparatus including cache memories (OP-CACHE, IF-CACHE) 52, 53 includes an instruction unit (Iu) (hereinafter referred to as I unit) 1A and a storage control unit (Su) as shown in the figure. A central processing unit (CPU) 1 including a 1B (hereinafter, referred to as an S unit) 1C and an arithmetic unit (Eu) (hereinafter, referred to as an E unit) 1C, a storage control device (MCU) 2, and a main storage device (MS) ) 3 and the cache memory (OP-CACHE, IF-CACHE) 52, 53 is the S unit 1B described above.
It is provided inside.

In such an information processing apparatus, the S unit 1B which has received the instruction fetch request by the instruction fetch request (IF-REQ) signal from the I unit 1A, when the instruction exists in the cache memory (IF-CACHE) 53, , An instruction fetch status valid (IF-STV) signal is returned to the I unit 1A, and if the instruction does not exist in the cache memory (IF-CACHE) 53, an instruction fetch line missing detection ( (Hereinafter referred to as "IF-LMD") signal, and sends a main memory request (MS-REQ) signal to the main memory control unit (MCU) 2, and the storage control unit (MCU) 2 By controlling the MS) 3, a block fetch including the instruction is performed.

In addition, the operand fetch request (OP-RE
The S unit 1B which has received the operand fetch request by the Q) signal has the operand in the cache memory (OP-CAC
If it exists in the HE) 52, an operand status valid (hereinafter referred to as OP-STV) signal is returned to the I unit 1A, and the operand is cache memory (OP-CACH).
E) If not present in 52, for I Unit 1A,
An operand line missing detection (OP-LMD) signal is returned, and a main memory request (MS-REQ) signal is sent to the main memory control unit (MCU) 2 so that the storage control unit (hereinafter referred to as MCU)
2) controls the main memory (MS) 3 to perform a block fetch including the operand.

At this time, together with the main memory request (MS-REQ) signal, the main memory request address (MS-REQ-ADRS) signal and the type of the request, for example, instruction fetch, prefetch, address translation buffer fetch, operand fetch, etc. The request identifier (REQ-ID) shown is transmitted.

Then, when the block fetch data (MS-DATA) is returned from the main memory device (MS) 3, a return identifier (RTN-ID) indicating the type of the data {the above corresponds to the request identifier (REQ-ID)}. At the same time, an identifier (DATA-ID) indicating the number of bytes of data is returned.

A conventional method for the block fetch will be described with reference to FIG.

FIG. 7 is a diagram for explaining a conventional cache memory control system, in which (a) shows an address system, (b) shows a data system, (c) shows a control system, and (d) shows a request. An example of an identifier (REQ-ID) is shown. However, in the following description, an example of the operand cache memory will be mainly described unless otherwise specified.

First, FIG. 7A shows an address system of a configuration example of a conventional main memory read port.

As can be seen from the figure, in the conventional method, the main memory read ports (OP-BFAR, PR-BFAR, TR-BFAR, IF-BFAR) 35 to 38 are fixed depending on the type of the block fetch request.
Was equipped with.

Therefore, when the S unit 1B sends various block fetch requests to the MCU 2, the request address is set in the main memory address register (hereinafter, referred to as MSAR) 30, and Operand block fetch address register (hereinafter OP-BFAR
35), those related to prefetch requests to the prefetch address register (PR-BFAR) 36, those related to address translation buffer (TLB) requests to the TLB block fetch address register (TR-BFAR) 37, and instruction fetch requests In the case of the above, the request address is set in the instruction fetch block address register (IF-BFAR) 38, respectively.

Also, the request address set in MSAR30 is
The request address is sent and cleared immediately,
Read port above (OP-BFAR, PR-BFAR, TR-BFAR, IF-BFA
R) The request address set to 35 to 38 is held until the processing by the block fetch request is completed.

FIG. 8 is an operation time chart of the cache memory control method, (a) shows the case of the conventional method, and (b) shows the case of the present invention described later.

First, the conventional cache memory control operation will be described in more detail with reference to FIG.

In each cycle shown in FIG. 8A, the P cycle indicates a priority cycle, and the T / W cycle is a cycle for performing address conversion, a directory search cycle for the directory 50 of the cache memory, or the cycle. A write cycle to the directory 50, a B / S cycle is a read cycle from the data array 51 of the cache memory, or a write cycle to the data array 51, and an R cycle is a result cycle.

As shown in the address system of FIG. 7 (a), in the P cycle, the operand fetch request address (IU-OP-REQ-ADRS) sent from the I unit 1A is It is set as an effective address register in the operand T cycle effective address register (hereinafter referred to as OP-TEAR) 10, converted into an absolute address by the operand address conversion buffer (OP-TLB) 40, and a part of the effective address. (That is, search tag address) in the operand cache directory (OP CACHE
DIR) 50 is searched, and the absolute value (that is, the comparison tag address) is compared in the comparator (C) 50a.

In the next B cycle, the absolute address is the operand B cycle absolute address register (hereinafter OP-BAA).
R) is set to 20, and the comparison result in the T cycle is the operand directory collation register (hereinafter OP
-Called DMR) 21 and, as a result of the comparison, if there is a match with any way (that is, set), the above OP-DMR 21 sends the above OP-STV signal to the I unit.
It is sent to 1A, and the address set in the operand B cycle effective address register (hereinafter referred to as OP-BEAR) 22 causes the operand cache data array (OP CACHE DATA ARRAY) 51, for example, 16 ways (W
Data of (AY 0 to WAY F) is read out, and one of the ways is selected by the signal transmitted from the OP-DMR 21.

Also, from the above comparison, if there is no match with any way, that is, if there is a cache mishit,
An OP-LMD signal is sent from the OP-DMR 21 to the I unit 1A.

In the next R cycle, if a cache hit occurs, the operand cache data array (OP CAC
The data selected from the HE DATA ARRAY) 51, as shown in the data system of FIG.
It is written to the register (OWR) 100 in the unit) 1C.

However, in the case of a cache miss, the requested address set in OP-BAAR20 in FIG. 7 (a) is M
It is set in SAR30 and OP-BFAR35, and the requested address of MCU2 is sent from MSAR30.

When the request address is sent to the MCU2, FIG. 7 (c)
In the control system shown in FIG. 2, the block fetch control unit (hereinafter referred to as BF-CNTL) 80 causes the MS-REQ signal 90 and the seventh
As shown in FIG. 3D, the type of the main memory read port,
That is, a request identifier (REQ-ID) 91 indicating the type of the request is created and sent to the MCU 2 to start the block fetch including the operand.

At this time, the block fetch is performed, for example, in units of 64 bytes, and the MS returned from the main storage device (MS) 3 is returned.
-DATA is sent in 8 byte units divided into 8 times. The data identifier (DATA-ID) is an identifier indicating which byte data at this time is the data.

When sending data from the MCU 2 to the central processing unit (CPU) 1, several cycles before the MS-DATA is sent {in the time chart of FIG. 8, for example, 3 cycles (τ) before}
In addition to the data output instruction (DOW) signal from the MCU 2, a return identifier (RTN-ID) {request identifier (REQ-ID) described above
Equivalent to} signal and the data identifier (DA
TA-ID) signal transmission is started.

By these controls, the operand move-in register even side (OP-MIR-EVN) 65E, shown in the data system of FIG. 7 (b),
Operand move-in register odd number side (OP-MIR-ODD) 65
The MS-DATA is set to O, and the operand cache data in register even side (OP-CDIR-EVN) 70 and the operand cache data in register odd side (OP-CDI
R-ODD) 71.

“BYPASS” shown in the time chart of FIG. 8 means that the data within 8 bytes designated by the request address from the I unit 1A that has activated the block fetch request is shown in FIG. ) Is a time chart for writing to the register (OWR) 100 without going through the operand cache data array (OP CACHE DATA ARRAY) 51 shown in the data system of FIG.
When data is set in both the operand cache data in register even side (OP-CDIR-EVN) 70 and the operand cache data in register odd side (OP-CDIR-ODD) 71, the operand cache data array (OP CACHE DATA ARRAY) 51 to the operand cache data in register even side (OP-CDIR-EVN) 70, operand cache data in register odd side (OP-CDI
R-ODD) 71 contents, simultaneously showing a time chart for writing 16 bytes of data.

Therefore, in the move-in operation, the 16-byte write operation is performed four times to move-in the 64-byte data. As shown in the time chart of FIG. 8, until the move-in ends, that is,
Until the block fetch is completed, the'OP-BFAR-VALID signal 'indicating that the above-mentioned operand block fetch address register (OP-BFAR) 35 is valid will continue to be sent, as shown in the time chart. In addition, the next operand request can be sent is the above-mentioned'OP-BFAR-VALID signal 'corresponding to the preceding operand request.
This is one cycle after the end of the transmission of.

Prefetch (PR) block fetch request, address translation table (TR) block fetch request, instruction (I
The same thing was done for the block fetch request of F).

Then, prefetching that occurs in response to the block fetching request that occurs as described above is performed as follows.

In FIG. 9, the above-mentioned operand address is registered by a signal (O) given to the multiplexer 252 from the priority control circuit 250 which has received the operand request.
The data is transferred to the main memory address register (MSAR) 30 via the PT-EAR) 10 and the register (OP-B-AAR) 20 and fetched as described above.

In parallel with this, if the operand request signal + R_OP_REQ is output from the I unit and the signal + R_NEXT_LINE_PREFETCH is output from the I unit 1A indicating that processing of two or more blocks is required, if a cache mishit occurs in the next block. , The input condition of the AND circuit 201 of FIG. 10 is satisfied, the flip-flop circuit 208 is set, and the block fetch request signal for prefetch +
PF_REQ is output on line 209 (see FIG. 4 (a)).
The block fetch request signal + PF_REQ on this line 209 is
As shown in FIG. 10, the fetch address of the address register (PF-EAR) 112, which is selected and output by the priority control circuit 250 and generates and holds the fetch address for the next block, is multiplexed by the output signal. The data is transferred to the main memory address register (MSAR) 30 (FIG. 7 (a)) in the same manner as in the operand fetch via 252 and the fetch is performed in the same manner as described above. However, in this case, the request address set in the register (OP-BAAR) 20 is set in the register (PR-BFAR) 36, and the request identifier (REQ-ID) “01” is sent from the block fetch controller 80. Register (REQ
-ID) 91 is set. Also, from the MCU2 to the central processing unit 1
When sending data to, the data output (DOW) instruction signal and return identifier (RTN-I) transferred from the MCU2 to the control system (Fig. 7 (c)) are sent as in the case of operand fetch.
D) signal and data identifier (DATA-ID) signal cause MS-DATA returned from the main storage device (MS) 3 to be the prefetch move-in register even side (PR-MIR) of the data system of FIG. 7 (b). -EVN) 66E, prefetch move-in register odd side (PR-MIR-ODD) 61O is set in 8 bytes each, and operand cache data in register even side (OP-CDIR-EVN) 70, operand cache data in register odd side (OP-CDIR-ODD) 71 is set.
The subsequent "BYPASS" or move-in (MoveIn) is the same as the case of operand fetch.

[Problems to be solved by the invention]

In the above conventional method, the main memory read port (35 to 38) is fixed depending on the type of block fetch request, and the request address of the block fetch is held until the block fetch of the request is completed. Therefore, if a request of the same type is sent from the I unit 1A, and the data of the request address does not exist in the cache memory and the processing of the first block fetch request is started, the block fetch Until the processing is completed, the subsequent transmission of the same type of block fetch request is delayed, and efficient move-in cannot be performed.

In addition to this limitation, as is clear from the above,
The block that can be prefetched in the operand fetch can be performed only for the block next to the block that is operand-fetched. That is, there was no means to further set the flip-flop circuit 208 for prefetching. Therefore, even if a miss hit can be predicted in the I unit for a longer period of time due to the operation, the block must be read again to perform the operand fetch, and the move-in efficiency is low also from this point.

The present invention was created in view of the above problems, and an object of the present invention is to provide a cache memory control method capable of performing a desired number of prefetches within the maximum allowable number of block fetches.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention. In the figure, 2 ₁ , ..., 2 m are main memory 3 and cache memory 5
And a plurality of main memory read ports that are provided between and to enable the next block fetch processing to be started before the completion of the preceding block fetch. Reference numeral 7 denotes a prefetch start-up circuit that causes the prefetch request signal generation circuit 6 to generate the first prefetch request signal in response to a cache mishit. A prefetch remaining number output circuit 8 receives the number of prefetch blocks and outputs the number of remaining prefetch blocks for each prefetch operation. Then, the signal repetitive output circuit 9 responsive to the output of the circuit 8 causes the prefetch request signal generation circuit 6 to generate the second and subsequent prefetch request signals every time a predetermined time has elapsed since the start of the first prefetch operation. The present invention is configured so that a sequential prefetch request signal is generated to cause a sequential prefetch operation via a plurality of main memory read ports.

[Work]

If a prefetch is required when a block fetch is generated, the prefetch activation circuit 7 generates the first prefetch request signal from the prefetch request signal generation circuit 6 and the first empty port of the plurality of main memory read ports. The prefetch operation of the corresponding block is started via.

In addition to this prefetch, if a block to be further prefetched is indicated by the prefetch remaining number circuit 8, the preceding prefetch operation is not completed every time a predetermined time elapses after the start of the preceding prefetch operation. However, the signal repetitive output circuit 9 causes the prefetch request signal generation circuit 6 to sequentially generate the prefetch request signals, and the prefetch corresponding to the sequentially generated prefetch request signals is an empty port next to the preceding main memory read port. Is done using.

Therefore, the function of advancing to the sequential block fetch before the completion of the preceding fetch in the block fetch can be effectively used in the prefetch, and efficient move-in or the like can be achieved.

〔Example〕

FIG. 2 is a diagram showing a configuration example of the cache memory control system of the present invention, in which (a) shows an address system,
(B) shows a data system, (c) shows a control system,
(D) shows an example of the request identifier (REQ-ID), and (e) shows the block fetch address register code (BFAR-COD).
E) shows an example of block fetch address registers (BFAR.0,1,2,3) 31 to 34, move-in registers (MIR0-EVN, ODD, MIR1-EVN, ODD, ... MIR3-EVN). , ODD)
60E, 60O, 61E, 61O, ..., 63E, 63O, block fetch control unit (BF-CNTL) 80 ′, and related mechanism, and prefetch request signal generation circuit in the block fetch control circuit of FIG. 2 (c) The detailed view of FIG. 3 (FIG. 3) is the means necessary for carrying out the present invention. The same reference numerals indicate the same objects throughout the drawings.

The cache memory control method of the present invention will be described below with reference to FIGS.

Even if the present invention is implemented, in each operation cycle in the S unit 1B, that is, in the P cycle, T cycle, and B cycle, the same operation as the conventional method is performed, but in the R cycle. Conventionally, depending on the type of block fetch request (block fetch, prefetch, ...)
The block address register that holds the request address is fixed as, for example, a register (OP-BFAR) 35, a register (PR-BFAR) 36, ... In the conventional method shown in FIG. However, in the present invention, the main memory read ports (BFAR.0,1,2,3) 31 to 34 are no longer fixed to the type of block fetch, and as long as there are free ports. The difference is that the block fetch request addresses of the same type can be held. The operation at this time is controlled by the BFARn-VALD (n = 0,1,2,3) signal sent from the block fetch controller (BF-CNTL) 80 'shown in the control system of FIG. 2 (c). To be done.

That is, when holding the block fetch request address, the BFARn-VALD (n = 0,1,2,3) signal is'off '.
And the requested address is held in the register having the smallest number (n) of the register, and the BFARn-VALD (n
= 0,1,2,3) is controlled to be'on '{second
See block fetch controller (BF-CNTL) 80 'in FIG.

Further, when the MS-REQ signal 90 shown in the control system of FIG. 2 (c) is sent, the request identifier (REQ-ID) 91 'is sent in the present invention as in the conventional method. The generation condition is different from the request identifier (REQ-ID) 91 described in the method.

That is, the request identifier (REQ-ID) 91 in the conventional system indicates the type of the block fetch address registers (BFAR) 35 ... 38, that is, the type of the block fetch request, but the request identifier (REQ-ID in the present invention The ID) 91 'simply identifies the block fetch address registers (BFAR.0,1,2,3) 31 to 34, as shown in FIG. The block fetch address register code (BFAR-CODE) indicating the type is generated in the block fetch control unit (BF-CNTL) 80 'as described above at that time, as shown in FIG. 2 (e). Corresponds to'empty 'captured by block fetch request, that is, block fetch address register (BFAR.0,1,2,3) 31-34 with BFARn-VALD (n = 0,1,2,3)' off ' And retain the code of the block fetch type (OP, PR, TR, IF) This is done {see FIGS. 2 (c) and 2 (e)}.

Therefore, the return identifier (RTN-
ID) (equivalent to REQ-ID), the block fetch address register (BFAR.0,1,2,3) 31-34 number (00,0
1,10,11) and recognizes the selector (SE
L) 82 is accessed to select and output the block fetch address register code (BFAR-CODE).

In the conventional method, the return identifier (RTN-ID) is used as a control signal when writing the move-in data (MS-DATA) from the main storage device (MS) 3 to the cache memory data array (OP CACHE DATA ARRAY) 51. Used {Bypass move-in control unit (Bypass M
ove In CONTROL) 81}, but in the present invention, the above
BFAR-CODE controls the bypass move-in control unit 81 'shown in FIG. 2 (c).

Bypassing block fetch data (MS-DATA) from the main memory (MS) 3 when the present invention is implemented (Bypas
s) and Move In timing are as shown in the time chart of FIG. 8 (b), and when the same type of block fetch request is being processed, that is, BFAR0-VALID is'on '. Also, the same type of block fetch does not overlap at one time, specifically, 8τ (64-byte move-in required for the move-in processing is
The next same block fetch request can be sent as long as the time required to write to the cache memory data array (OP CACHE DATA ARRAY) 51 four times in units of 16 bytes is secured.

This feature is also used for prefetching.

That is, the block fetch request of the operand as described above is issued, and the block fetch is performed in the same manner as described above, for example, the use of the block fetch address register (BFAR0) 31 and the corresponding block fetch address register code (BFAR0). -Started by holding CODE).

In parallel with this, a signal B_PFCODE_BiT0 to 1 representing the number of blocks to be prefetched subsequent to the block of the cache memory data array (OP CACHE DATA ARRAY) 51 that has been required to be fetched from the block described above. If the number is 4 (BFAR0 to BFAR3), it consists of 2 bits. ] From the I unit 1A to the prefetch control circuit of the block fetch control circuit 80 '(the third
(See the drawing) and set in the 2-bit flip-flop circuit 200. This allows the AND circuit 202
"1" is generated from AND circuit 204, and OR circuit 206
The flip-flop circuit 208 (corresponding circuit of the prefetch request signal generation circuit 6 in FIG. 1) is set via the
A prefetch request signal + PF_REQ (see FIG. 4 (b)) is generated on 9. This AND circuit 202,204, OR circuit 2
Reference numeral 06 constitutes a specific circuit example of the prefetch start-up circuit 7 of FIG.

The above-mentioned four cycles in the S unit 1B for the generated prefetch request signal + PF_REQ are started after a predetermined time has elapsed (see FIG. 4 (b)). In that P cycle, the signal + PF_GO is generated. With this signal, the number of remaining blocks signal PFCODE_BiTO to 1 for resetting and prefetching the flip-flop circuit 208 is set.
(This signal is generated by the multiplexer 210, the subtracter 212 and the 2-bit flip-flop circuit 214. The multiplexer 210, the subtractor 212 and the 2-bit flip-flop circuit 2
Reference numeral 14 is a configuration example of the prefetch remaining number output circuit 8 of FIG. ) Is set in the 2-bit flip-flop circuit 214, and a signal is set in the delay circuit 216 that gives a delay time required until the next prefetch request signal + PF_REQ is generated in order to perform efficient move-in. Consists of the required number of latches and sequentially shifts the signal every machine cycle.

In the R cycle for this prefetch, the next block fetch address register (BFAR1) 32 is used and the corresponding block fetch address register code (BFAR-CODE) is held in the same manner as described above, and A block fetch (first prefetch block) is started.

As shown in FIG. 5, the address for this first prefetch block is the value obtained by adding 64 in the adder 110 to the address for the preceding block fetch in the adder (the address one block ahead) is the register ( PF-EAR)
The address of the register (PF-EAR) 112, which is held in 112, is used for the prefetch block at the start of the first prefetch in the same manner as in the conventional case. This relationship also applies to the prefetch of the second and subsequent blocks, and the detailed description thereof will not be repeated below.

At the start of this first prefetch, the block fetch for the first block that was started earlier is not completed, but it will be completed after the time required to perform the above-described procedure has elapsed (FIG. 4 (b). )reference).

If there is a block to be prefetched following the first prefetch block that has just started, that is, if the AND circuit 220 continues to generate a signal of "1", an output signal is generated from the delay circuit 216 described above. Output signal is generated from the AND circuit 222 at the time of prefetch request signal + PF_REQ for the second prefetch block.
Is output from the flip-flop circuit 208. A delay circuit 216, AND circuits 220, 222, and an OR circuit which sequentially generate the second and subsequent sets in the flip-flop circuit 208.
Reference numeral 206 shows a configuration example of the signal repetitive output circuit 9 of FIG.

The operation after the generation of the prefetch request signal + PF_REQ described above proceeds in accordance with the above description, and the detailed description thereof will be omitted.

As described above, according to the present invention, in an information processing device including a cache memory, a main memory read port that is not related to the type of the block fetch is used to perform the block fetch when a hit miss occurs in the cache memory. As long as a plurality of ports are provided and the port is vacant, even if the same type of block fetch request is used, the vacant port is used, without waiting for the preceding block fetch process of the same type to end. At least, the timing required for the move-in process can be shifted to perform multiple processes of the same type of block fetch. Since this multiple block fetch function is also fused with the system for prefetch to construct an integrated system for performing block fetch for the fetch block and prefetch block, efficient move-in and bypass can be achieved. .

〔The invention's effect〕

As described above in detail, the cache memory control method of the present invention is an information processing apparatus having a store-through method or a swap method cache memory that holds a copy of a part of the contents of the main memory (MS). In order to prevent a decrease in the efficiency of block transfer from the main memory (MS) due to waiting for a block fetch request to the main memory until the preceding block fetch of the same type is completed, As long as a main memory read port is provided and a free port exists in the port, the block fetch request is sent out using the free port regardless of the type of the block fetch request, Since the multi-processing is performed, the main memory read port is fixed to the type of block fetch for the main memory. Therefore, even if the same type of block fetch occurs, or if multiple prefetches are required following the block fetch, as long as there is a free port, The same type of block fetch can be set, and effective data can be efficiently transferred from the main memory (MS) to the cache memory with a short access time.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a diagram showing a configuration example of a cache memory control system of the present invention, FIG. 3 is a detailed view of a main part of a prefetch control circuit of the present invention, and FIG. An operation time chart of the cache memory control system of the present invention, FIG. 5 is a detailed diagram of a prefetch address generation system of the present invention, FIG. 6 is a schematic diagram of an information processing apparatus having a cache memory, and FIG. 7 is a conventional cache FIG. 8 is a diagram for explaining the memory control system, FIG. 8 is an operation time chart of the cache memory control system, FIG. 9 is a diagram showing a conventional prefetch address control system, and FIG. FIG. In FIG. 1 and FIG. 3, 2 ₁ , 2 ₂ , ..., 2m are a plurality of main memory read ports, 3 is a main memory device, 5 is a cache memory, 6 is a prefetch request signal generation circuit (flip-flop circuit). 208), 7 is a prefetch starting circuit (AND circuits 202, 204, OR circuit 206), 8 is a prefetch remaining number output circuit (2-bit flip-flop circuits 200, 214, multiplexer 210, subtractor 21)
2) and 9 are signal repetitive output circuits (delay circuit 206, AND circuit 220, 2
22).

Claims (1)

[Claims] 1. A plurality of main memory read ports (2 ₁ , ..., 2 m) that enable the next block fetch process to be entered before the completion of the preceding block fetch, and respond to a block fetch request. The main memory read port (2 ₁ , ...
., 2m) in the cache memory control system for controlling data transfer between the main memory device (3) and the cache memory (5), the prefetch request signal generation circuit (6) and the cache mishit In response, a prefetch activation circuit (7) that generates the first prefetch request signal from the prefetch request signal generation circuit (6), and a prefetch remaining count output that receives the prefetch block number and outputs the remaining prefetch block number for each prefetch operation A circuit (8), and a signal repetition for prefetch that causes the prefetch request signal generation circuit (6) to generate second and subsequent prefetch signals at predetermined time intervals while the number of remaining prefetch blocks is given. An output circuit (9) is provided, and the prefetch signal generation circuit (6) Then the cache memory control method, wherein a responsive prefetch operation to the prefetch request signal output was set to give rise via a plurality of main memory read port.