JPH0690877B2 - Semiconductor memory - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor memory, and more particularly to equalizing precharge potentials of a pair of bit lines in the same column.
MOS for equalization to short circuit between bit lines to protect
The present invention relates to a semiconductor memory including an (insulated gate type) transistor.

[Technical background of the invention]

In this type of conventional static type semiconductor memory, for example, each column is provided with P channel transistors T ₁ and T ₂ for precharging corresponding to a pair of bit lines BL and ▲ ▼ as shown in FIG. Connected, above bit line BL, ▲
The bit line BL, ▲ ▼ is located closer to the precharge transistors T ₁ and T ₂ than the memory cells M _{1 to} Mn connected to ▼.
A P-channel transistor T ₃ for equalization is connected between them. L _PR is a precharge control line for supplying a precharge signal _PR to the gates of the transistors T ₁ , T ₂ and T ₃ , and WL _{1 to} WLn are memory cells of a specific row among the memory cells M _{1 to} Mn. Is a word line for selecting.

In the above semiconductor memory, the precharge transistors T ₁ and T are used in each column when reading or writing.
₂ is turned on and the bit line BL, ▲ ▼ is precharged by the precharge power supply V _PR , and at the same time, the equalizing transistor T ₃ is turned on and the precharge potentials of the bit lines BL, ▲ ▼ are made equal.

[Problems of background technology]

By the way, since the bit line BL, ▲ ▼ is added with wiring resistance, wiring capacitance, junction capacitance in each memory cell, etc., precharging and equipotential at positions close to the precharging transistors T ₁ and T _2. Compared with the operation of equalization, at a position far from the precharging transistors T ₁ and T ₂ , the raising of potential and equalization of potential by precharging are delayed. Due to such a delay, the potential of the bit line BL, ▲ ▼ is not uniform yet, that is, the bit line BL, ▲ ▼ has a potential difference, the memory cell of a specific row is selected and its information is read. Bit line BL, ▲
During this period, the correct potential difference due to the read information cannot be obtained. In this case, if the potential difference due to the read information between the bit lines BL and ▲ ▼ is sensed by a latch type sense amplifier (not shown), the latch data in the previous read cycle and the read information in the present read cycle are At different times, this information lengthens the time required to invert the potential relationship between the bit lines BL and ▲ ▼.

Therefore, it is necessary to lengthen the precharge time to sufficiently perform the precharge so that the potential difference between the bit lines due to the delay of the precharge is eliminated. However, as the memory capacity increases, the bit line additional capacity increases, and the bit line resistance increases due to the reduction of the wiring width. Therefore, it is necessary to further lengthen the precharge time. It becomes a big factor to prevent the change.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and provides a semiconductor memory in which a bit line pair quickly becomes equipotential during precharge and high-speed reading is possible.

SUMMARY OF THE INVENTION That is, the present invention provides a semiconductor memory including an equalizing transistor for equalizing the precharge potentials of a pair of bit lines in the same column, in a memory cell group connected to the bit lines. Connect the equalizing transistor between the bit lines near the memory cell where the precharge by the bit line precharging transistor is most delayed,
A precharge line for supplying a precharge signal to the control terminal of the bit line precharge transistor is branched and connected to the control terminal of the equalizing transistor.

Therefore, in precharging, since the bit lines are equipotentialized in the vicinity of the memory cell where precharging is most delayed, even if the precharging time is short, the potential difference between the bit lines during precharging is eliminated, and the read operation is speeded up. Can be planned.

Example of Invention

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 2 shows a part of each column in the static semiconductor memory. The insertion position of the equalizing transistor T ₃ is different from that of the conventional example shown in FIG. 1, and the other parts are the same. Therefore, the same reference numerals as those in FIG. 1 are given and the description thereof is omitted.

That is, the equalizing Torajisuta T _3, the bit line BL by the precharge transistors T _1, T precharge transistors T ₁ and in the vicinity of the memory cell farthest M ₂ from _2, farther from T _2, ▲ ▼ It is connected to the.

According to the above configuration, the bit lines BL, ▲ ▼ bit BL by equalizing transistors T ₃ pulley charge is near the most delayed memory cell during precharge, ▲
Since ▼ is equipotentialized, bit line BL, ▲ ▼
Makes the equipotentialization faster than in the conventional example. Therefore, it is possible to solve the problem due to the delay of precharge without making the precharge time longer than in the conventional example, and to obtain a normal potential difference between the bit lines due to the read information from the memory cell of a specific row after that. You can Therefore, the above memory enables higher speed operation than the conventional memory, and the larger the capacity of the memory, the larger the delay in precharge becomes, and the equalizing operation at the position farther from the precharge power source as described above. The effect of speeding up is increased.

The present invention is not limited to the static type memory of the above embodiment, and the equalizing transistor is not limited to one. That is, as shown in FIG. 3, an equalizing transistor T ₄ is added to the position of T ₃ of the conventional example (FIG. 1), and further, several transistors in the memory cells M _{1 to} Mn are added as shown in FIG. By adding the equalizing transistors T ₅ ... Between the bit lines at (or one) cell intervals, the potential equalization of the bit lines BL, ▲ ▼ can be made faster.

〔The invention's effect〕

As described above, according to the semiconductor memory of the present invention, it is possible to quickly equalize the potentials of bit line pairs in the same column during precharging, speed up the read operation of the memory, and increase the memory capacity. It is possible to solve the problem due to the delay of precharge accompanying the above.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a part of a conventional semiconductor memory, and FIG.
FIG. 3 is a circuit diagram showing a part of a semiconductor memory according to an embodiment of the present invention, and FIGS. 3 and 4 are circuit diagrams showing other embodiments. BL, ▲ ▼ …… bit line, M _{1 to} Mn …… memory cell, T ₁ ,
T ₂ …… Precharge transistor, T _{3 to} T ₅ …… Equalize transistor.

 ─────────────────────────────────────────────────── --- Continuation of the front page (56) Reference JP-A-57-169994 (JP, A) JP-A-56-117389 (JP, A) JP-A-56-10587 (JP, A) JP-A-60- 234293 (JP, A)

Claims (2)

[Claims] 1. A semiconductor memory comprising an equalizing transistor for equalizing the precharge potentials of a pair of bit lines in the same column, wherein the pair of bit lines are set to a precharge potential with respect to each other. A bit line precharge transistor having a current path connected between a power supply and each bit line; a precharge line for supplying a precharge signal to a control terminal of the bit line precharge transistor; and the precharge line And a means for branching a precharge signal to distribute the precharge signal, and a plurality of branch precharge lines connected to the control terminals and current paths connected between a pair of bit lines. And an equalizing transistor, wherein one of the equalizing transistors is Semiconductor memory characterized by precharging by Tsu preparative line precharging transistors are arranged in the vicinity of the most delayed memory cell. 2. The semiconductor memory according to claim 1, wherein the equalizing transistors are provided at intervals of one or a plurality of the memory cells.