JPH0691222B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device.

[Conventional technology]

As a configuration of a conventional semiconductor memory device, N of 102 as shown in FIG.
A device using MOS and a polysilicon resistor of 101 has been devised and provided as a product. FIG. 2 shows the cross-sectional structure, 202 indicates NMOS 201, polysilicon 203 is an insulating film, and 204 is a wiring material.

[Problems to be solved by the invention]

In the conventional technology, the following problems occur when the density is further increased and transistors, resistors, etc. are miniaturized in the future. The resistance value of the polysilicon resistance is the total current consumption in the holding state of the memory device, that is, the polysilicon resistance, within the range in which a current that can hold information can flow even if the memory cell is affected by external noise or diffusion leak. Must be set so that the total sum of the currents flowing through is extremely low. The market demands that, no matter how the degree of integration increases, the holding current should be the same or lower than before, and at the worst, the resistance value of polysilicon is the same as the rate of improvement of the degree of integration. It must be high in proportion. But increasing resistance is
There is a risk that the retention capacity of the memory cell will be reduced and the data will be destroyed by external noise and diffusion leak.
The present invention solves these problems and provides a new memory cell structure.

[Means for solving problems]

The present invention solves the above-mentioned problems by newly forming polysilicon II on polysilicon I via an insulating film.

[Work]

 The present invention will be described with reference to FIGS.

In FIG. 3, reference numerals 301, 302 and 303 denote polysilicon I, and 305 denotes polysilicon II. 301 and 303 are P with high impurity concentration
A mold region 302 is a low-concentration P-type impurity region serving as a resistance. 304 is a depletion layer generated by the potential of 305. 305
The depletion layer further expands when the potential of
It reaches the bottom of, and it becomes like Fig. 4. At this time, 30
The current flowing from 1 to 303 is almost cut. When this is measured, it becomes like FIG. V _A is the potential of 305 and I
Is the current between 301 and 303. A memory cell using this invention is shown in FIG. The operation of FIG. 6 is a bistable flip-flop as in FIG. However, compared with the conventional example of FIG. 1, the current between V _DD and V _SS in the memory operating state can be made very small due to the effect of FIG. Further, when V _A is low, the resistance becomes extremely low, so that the holding capacity is extremely high and the resistance to external noise and leak current becomes strong.

〔Example〕

A cross-sectional view of the present invention is shown in FIG. 701 is polysilicon I, 702 is an insulating film, and 703 is polysilicon II. A wiring member 705 is connected to the power source and the drain or gate of the N-MOS through this wiring member.

FIG. 8 shows another structure. FIG. 8 shows only the polysilicon I in FIG. 7, 801 is a P-type impurity region, and 802 is an N-type impurity region. This 802 is for suppressing the current when the V _A is high in the characteristics of FIG. 5 to be lower than that of the example of FIG. 7, and has the effect of reducing the current consumption of the entire integrated circuit. Further, FIG. 9 is also for the same purpose, in which a polysilicon III of 901 is newly provided to expand the depletion layer inside the polysilicon I from above and below to suppress the current.

〔The invention's effect〕

The present invention, as described above, keeps the current consumption low,
In addition, the present invention proposes a memory cell having a high retention capability for external noise, leak current, etc., and provides a semiconductor memory device using the same.

[Brief description of drawings]

 Fig. 1, Fig. 2 ... Fig. Showing a conventional example Fig. 3, Fig. 4, Fig. 5 ... explanatory diagram of the present invention Fig. 6, Fig. 7 ... diagram showing an embodiment of the present invention 8 and 9 ... Diagram showing an embodiment of the present invention

Claims (1)

[Claims] 1. A semiconductor memory device comprising a flip-flop in which inputs and outputs of two inverters, each of which is formed by connecting a transistor and a load element in series between respective power supplies, are cross-connected to each other. A crystalline silicon film, a second polycrystalline silicon film provided above the first polycrystalline silicon film via a first insulating film, and provided above the second polycrystalline silicon film via a second insulating film. The load element has a third polycrystalline silicon film, and the load element has a structure in which a first conductive type polycrystalline silicon layer and a second conductive type polycrystalline silicon layer provided in the second polycrystalline silicon film are stacked. A semiconductor memory device having, and applying a predetermined potential to the first polycrystalline silicon film and the third polycrystalline silicon film above the load element.