JPH0691440B2 - Random pulse pattern generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A random pulse pattern generation circuit for generating in parallel i (i is an integer of 2 or more) data strings in which one data string is a random pattern with control bits. With regard to the above, regarding the purpose of providing a random pulse pattern generation circuit for generating a random pulse pattern with a control bit, which can reduce power consumption and cost by using a low-speed element, a single data string Is a circuit that generates in parallel i data strings that form a random pattern with control bits, is an n-stage shift register, and out of the 2n states that are generated, 2n-1 except the all 0 states. And a random pattern generating means for extracting i data strings by utilizing the property of the m-series returning through all states And a control bit inserting means for inserting the control bit at a predetermined position in the i data string from the data selecting means. When the control bit inserting means inserts the control bit, the processing clock of the random pattern generating means is stopped at the inserting timing to insert the control bit, and the data selecting means generates the random pattern at the same inserting timing. It is configured to replace the i data strings extracted from the means.

[Industrial application field]

The present invention relates to a random pulse pattern generation circuit that generates in parallel i data strings in which a single data string is a random pattern with control bits.

For example, data for testing the transmission line and the transmission device may be added to the third group signal (45 Mbps) in the North American digital data transmission device.

This test data is composed of a control bit portion and a data bit portion, and the data bit portion is required to have any data pattern.

Therefore, an m-series generator is used as a circuit for generating a random pattern, and control bits are inserted into the data string extracted from this m-series generator to generate it.

However, in order to generate this with a serial data string, an element capable of high speed (45 Mbps) is required, and therefore, it is required to be able to generate at a relatively low speed (for example, 22 Mbps or less).

[Conventional technology]

FIG. 5 is a block diagram illustrating a conventional example, and FIG. 6 is a diagram illustrating a data frame format.

FIG. 6 shows the frame format of the third group signal (45 Mbps) in the North American digital data transmission device.

This frame format consists of a control bit area (a) consisting of frame bits, parity bits, and game alarm bits, and a data bit area (b) consisting of 84 bits.

When used for testing a communication line, frame bits are added to the control bit area (a) and the data bit area (b) is transmitted to the communication line to be tested as a random pulse pattern.

As shown in FIG. 5, a conventional example of the generation of a random pulse pattern for this test is shown in FIG. 5, in which 15 stages of flip-flop circuits (hereinafter referred to as FF circuits) 12 (1) to 12 (15) and a final stage of FFs are used. It is generated in the random pattern generation unit 1 including the circuit 12 (15) and the EX-NOR circuit 13 that takes the exclusive OR of the outputs of the FF circuit 12 (14) immediately preceding the circuit 12 (15).

A clock at a predetermined speed (for example, 45 Mbps) is used as a clock for operating the random pattern generator 1.
MCLK is used.

The control bit insertion circuit 3 inserts a frame bit into the pulse pattern extracted from the random pattern generator 1 to generate a random pulse pattern PN for testing. Note that the clock MCLK is used as the insertion timing at this time.
TIM1 reproduced from is used.

The random pattern generator 1 which forms the above-mentioned 15-stage shift register generates a pulse pattern by the generator polynomial X ¹⁵ + X + 1 = 0.

That is, the random pattern generating unit 1 constituting the shift register of this 15 stage generates 2 ¹⁵ state, the inner all except the state of 0 (2 ¹⁵ -1) state can all occur that Yes, this happens repeatedly.

[Problems to be solved by the invention]

As shown in FIG. 6 (A) (however, FIG. 6 (B) will be described later), for example, when a random pulse pattern for test is generated as a 45 Mbps third-order group signal, the fifth example in the conventional example is used.
As shown in the figure, the pulse pattern was generated serially.

In this case, the element used for the random pattern generation unit 1 and the like needs to be a high-speed element, which causes a problem that power consumption increases and cost also increases.

It is an object of the present invention to provide a random pulse pattern generation circuit for generating a random pulse pattern with control bits, which can reduce power consumption and cost by using a low-speed element.

[Means for solving problems]

 FIG. 1 shows a block diagram illustrating the principle of the present invention.

The principle block diagram of the present invention shown in FIG. 1 shows a functional block of a random pulse pattern generation circuit having the same function as described in FIG.

The random pattern generating means 10 in the random pulse pattern circuit is an n-stage shift register, and an m-sequence returning through all (2n-1) states excluding all 0 states of 2n states to be generated. The data selecting means 20 replaces the i data strings extracted from the random pattern generating means 10 at the control bit insertion timing TiMn. The control bit inserting means 30 is the data selecting means 20.
The control bit is inserted at a predetermined position in one data string from the control signal at the control bit insertion timing TiMn, and the P / S conversion means 50 converts the i data string with the control bit inserted into a serial signal. The conversion is performed, and the provision of these is a means for solving this problem.

[Work]

For example, when an i-parallel random pattern is generated from the random pattern generating means 10, the position for taking out i data strings is determined by the nature of the m series, and the i data strings are controlled by the data selecting means 20 as control bits. It is replaced at the insertion timing TiMn.

Then, control bits are inserted at the replaced positions, and the i data strings are serially converted so that the data bit portion has a random pulse pattern, thereby reducing the consumption of the random pulse pattern circuit. Power and cost reduction can be achieved.

〔Example〕

Hereinafter, the gist of the present invention will be specifically described with reference to the embodiments shown in FIGS.

FIG. 2 is a block diagram illustrating an embodiment of the present invention, FIG. 3 is a diagram illustrating a time chart in the embodiment of the present invention, and FIG. 4 is a diagram illustrating a pulse pattern with a frame in the embodiment of the present invention. Are shown respectively. The same reference numerals denote the same objects throughout the drawings.

The embodiment of the present invention shown in FIG. 2 is an OR circuit 11 and a 15-stage FF as the random pattern generating means 10 described in FIG.
Random pattern generator 10a including circuits 12 (1) to 12 (15) and EX-NOR circuits 13 and 14, DF.F circuit 21 and JK-FF circuit 2 as data selection means 20.
2, a selector 23, 24, a NOR circuit 25, 26, a data select section 20a consisting of an EX-OR circuit 27, and a control bit inserting section 30a consisting of control bit inserting circuits 31 and 32 as a control bit inserting means 30
This is an example configured from and.

In addition to the above, FIG. 2 shows the output of the EX-OR circuit 27 as a parity bit counter 40 and control bit insertion circuits 31,3.
A P / S conversion circuit 50 that outputs two parallel random patterns PN output from 2 is added.

The random pattern generator 10a, which generates a pulse pattern by the generator polynomial X ¹⁵ + X + 1 = 0, uses the property of the m-sequence to generate two data such as channels (1) and (2) in FIG. 6 (B). Columns can be created.

In the case of this embodiment, the data string is taken out from the output of the FF circuit 12 (15) at the final stage and the data string is taken out from the output of the FF circuit 12 (7) due to the nature of the m-sequence, as shown in FIG. .

Further, FIG. 6 (A) is also data after the channels (1) and (2) in FIG. 6 (B) are serially converted by the P / S conversion circuit 50, and any data is in the form of a random pattern. Is forming.

Using the data strings of channels (1) and (2) in FIG. 6 (B), parallel data with frames PN1 and PN2 (this is 22 Mbps when the data rate in FIG. 6 (A) is 45 Mbps).
With the speed of.

That is, the timing TiM1 at which a control bit (frame bit in this embodiment) is inserted into the channel (1) (PN1) by a circuit (not shown) (for example, a reference clock generation circuit) and the channel (2) (PN2). And a timing TiM2 for inserting a control bit.

Next, the data sequence obtained by inhibiting the clock MCLK for the random pattern generation unit 10a at the timing TiM2 becomes the data sequence shown in FIGS. 2 and 3.

In addition, the DF.F circuit 21 in the data select section 20a from the data string
Prepare a data string shifted by 1 bit via.

The timings TiM1 'and TiM2' shown in FIG. 2 are obtained by shifting the timings TiM1 and TiM2 by 1 bit.

The JK-FF circuit 22 generates a signal for switching the selection of the selectors 23 and 24 at the timing TiM1 and the timing TiM2 '.

The selectors 23 and 24 switch between two inputs by a signal. The two inputs of the selector 23 are a data string,
And a data string as two inputs of the selector 24,
Becomes

Further, the selectors 23 and 24 are switched so that when the signal is "H", the data string is output to PN1, the data string is output to PN2, and when the signal is "L", the data string is output to PN1 and the data string is output to PN2. .

At this time, the random pattern generation unit 10a sets the timing T
Clock MCLK is stopped by iM2. Further, FIG. 3 shows the time chart described above.

NOR installed behind selectors 23 and 24 shown in FIG.
Circuits 25 and 26 are control bit insertion circuits 31 and 32 and are PN1 and PN.
This is to fix the position where the control bit is inserted in 2 to "L". The BX-OR circuit 27 outputs "H" when both PN1 and PN2 are in "L", and uses this as the parity bit. The parity bit counter 40 counts and synchronizes control bit insertion.

The data string shown in FIG. 3 is the data string selected by the selectors 23 and 24, and the positions of the symbols H, A, and P shown by the diagonal lines are the control bit insertion positions.

That is, when the data string is the switching signal "H" (hatched portion), the data string is switched from the data string to the data string, and the data string is switched from the data string to the data string.

As shown in FIG. 4, in the P / S conversion circuit 50, the parallel data strings of PN1 and PN2 are shown at the bottom, and PN1, PN2, PN1, PN
Convert to a serial data string in the order of 2, ...

This serial data string has a control bit insertion circuit
It is composed of the frame bits inserted at 41 and 42 and the data bits having a random data pattern.

〔The invention's effect〕

According to the present invention as described above, the processing speed of the random pulse pattern circuit is reduced, so that the power consumption and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention, FIG. 2 is a block diagram illustrating an embodiment of the present invention, FIG. 3 is a diagram illustrating a time chart in the embodiment of the present invention, and FIG. FIG. 5 is a diagram illustrating a pulse pattern with a frame in an embodiment of the present invention, FIG. 5 is a block diagram illustrating a conventional example, and FIG. 6 is a diagram illustrating a data frame format. In the figure, 1,10a is a random pattern generation unit, 3,31,32 are control bit insertion circuits, 10 is a random pattern generation means, 11 is an OR circuit, 12 (1) to 12 (15) are FF circuits, 13, 14 is an EX-NOR circuit, 20 is a data selection means, 20a is a data selection section, 21 is a DF.F circuit, 22 is a JK-FF circuit, 23 and 24 are selectors, 25 and 26 are NOR circuits, and 27 is an EX- circuit. An OR circuit, 30 is a control bit insertion unit, 30a is a control bit insertion unit, 40 is a parity counter, and 50 is a P / S conversion circuit.

Claims (1)

[Claims] 1. An i (i is an integer of 2 or more) in which a unified data string becomes a random pattern with control bits.
This is a circuit that generates book data strings in parallel, is an n-stage shift register, and returns through all 2n-1 states except all 0 states of the 2n states that are generated, m series Random pattern generating means (10) for extracting i data strings by utilizing the property of i and i extracted from the random pattern generating means (10).
Data selecting means (20) for replacing the data string of the book at the control bit insertion timing (TiMn), and inserting the control bit at a predetermined position in the i data string from the data selecting means (20) Control bit insertion means (30) for inserting at timing (TiMn); and P / S conversion means (50) for converting the i data strings in which the control bits have been inserted into serial signals. When the control bit is inserted by the inserting means (30), the processing clock of the random pattern generating means (10) is stopped at the control bit inserting timing (TiMn) to insert the control bit, and the data select In the means (20), the random pattern generating means (1 A random pulse pattern generation circuit characterized in that one data string extracted from (0) is replaced.