JPH0691519B2 - Signal processing method - Google Patents

Description

The present invention relates to a signal processing system, and more particularly to a signal processing system for a digital wireless communication line that transmits a zero continuous suppression code such as a BnZS code.

[Conventional technology]

In the digital wireless communication system, the transmission signal is scrambled for the purpose of flattening the transmission spectrum in the wireless section and facilitating extraction of the bit timing signal on the receiving side. This scramble processing is performed by the signal processing devices of the transmitting terminal station and the receiving terminal station, together with the insertion / extraction (multiplexing) of the parity check bits and frame synchronization signals necessary for monitoring the wireless section. In a microwave band digital radio communication system having a large transmission capacity, a digital multiplexed signal multiplexed by a digital multiplexing terminal device is input as an input signal. Conventionally, this digital multiplexed signal has a predetermined number of stages. AMI code (Alternate Mark Inve) scrambled with the pseudo random code (PN code) of
rsion) is used. Therefore, in the signal processing device on the wireless communication line side, synchronous scrambling processing (also called reset type) is performed by superimposing the signal processing device on the wireless communication line side so that the overall purpose of spectrum flattening can be achieved. Is designed.

In recent years, with the spread of digital signal transmission, a conventional AMI code (usually simply called a bipolar code, which is a bipolar code "1" with positive and negative pulses "+ A" and "-A" alternately assigned, has a bipolar RZ << (Return-to-Zero) code), and replaces n consecutive "0" s with a replacement code of a specific pattern that includes a pulse that violates the positive / negative alternating pulse rule of the AMI code and transmits the BnZS code. (Bipolar with n Zeros Substitut
zero continuous suppression code such as ion) has come to be adopted as a standard of CCITT. That is, the B ₃ ZS code and the B ₆ ZS code are already used in the United States, and the B ₈ ZS code is also planned to be used in Japan.

On the other hand, in the radio receiving device of each intermediate relay station including the receiving terminal station, the flat characteristic of the frequency spectrum of the received signal is constantly monitored, and when an abnormality is detected, an adaptive equalization circuit provided in each receiving device is detected. Is controlled so that the frequency spectrum of the output of the receiver becomes flat. The purpose of this compensation is to compensate for changes in the transmission band characteristics due to fading in each radio transmission section and prevent deterioration of the code error rate. In the conventional method of transmitting the AMI code, even if all the information signals input to the digital multiplexing terminal device are "0", the digital multiplexed signal transmitted from this is subjected to a predetermined number of scrambling processes. Since the bipolar rule that positive and negative pulses alternately appear is maintained, the unipolar signal that is code-converted by the signal processing device on the wireless communication line side is a scrambled signal, and a fixed number of stages of synchronization are applied to this. The transmission spectrum is flattened by the conventional signal processing method in which the type scramble processing is performed for transmission, and no problem occurs in the operation of the equalization circuit of the wireless reception device.

[Problems to be solved by the invention]

However, in the case of transmitting a BnZS code, if the information signal input to the digital multiplexing terminal equipment has a sequence of n "0" s, a specific replacement code including a pulse that violates the bipolar rule is transmitted. Therefore, when performing code conversion into a unipolar signal on the wireless line side, it is necessary to detect the bipolar rule violation pulse and the replacement code and output the original binary information signal. That is, when all the information signals input to the digital multiplexing terminal device become "0", the digital multiplexed signal output from the digital multiplexing terminal device is a positive and negative pulse and "0" in BnZS code. However, the output of the code conversion circuit on the wireless communication line side is continuous "0". Therefore, since only the scrambling process of the signal processing device on the wireless communication line side is performed, the spread spectrum is not sufficient and the transmission spectrum is not flat, and the adaptive equalization circuit of the wireless receiving device of the opposite station operates and fading occurs. Although not present, the transmission band characteristic is changed, and conversely the transmission quality is deteriorated. This phenomenon is not only when the information signal is continuous "0",
The same applies when the mark rate of the information signal is significantly reduced. Further, in the case of transmitting a plurality of digital multiplexed signals by one radio carrier as in the multi-phase modulation method, if the mark rate of one digital multiplexed signal is lowered, the transmission quality of other digital multiplexed signals is also reduced. There is a problem of deterioration and increase in errors.

One way to solve this problem is to increase the number of stages of the PN code generator that generates the PN code for the scrambling process. There is a problem in application to.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a signal processing system capable of transmitting a BnZS code through an existing digital wireless communication line by eliminating the above-mentioned problems by adding an additional circuit to a conventional device.

[Means for solving problems]

The signal processing system of the present invention is a signal processing system for performing synchronous scrambling and descrambling processing on a transmission signal at a transmitting terminal station and a receiving terminal station of a digital wireless communication line,
At the transmitting terminal side, a mark ratio detecting means for detecting a mark ratio of the code-converted unipolar signal to generate a control signal, and a mark ratio detecting means which operates in response to the control signal and superimposes on the synchronous scrambling process, Self-synchronous scramble means for performing a synchronous scramble process, and control information transmission means for transmitting the control signal to the receiving terminal station with additional bits inserted in the transmission signal, the receiving terminal station side, the Control signal detecting means for detecting the control signal from the additional bit transmitted from the transmitting terminal station, and self-synchronous descramble for operating in response to the output of the control signal detecting means to restore the self-synchronous scramble processing. And means.

〔Example〕

 The present invention will now be described in detail with reference to the drawings.

1 (a) and 1 (b) are block diagrams showing configurations of a transmission signal processing unit and a reception signal processing unit according to an embodiment of the present invention, respectively. As shown in FIG. 1 (a), the transmission signal processing unit on the transmission terminal side of the wireless communication line includes a code conversion circuit 1 that converts a BnZS code into a unipolar signal, and a speed conversion to convert a frame synchronization signal or the like. A transmission signal processing circuit 2 for inserting additional bits, a mark ratio detection circuit 3 for detecting a mark ratio of a unipolar signal and generating a control signal, a scramble circuit 4 for performing a synchronous scrambling process on a speed-converted data signal, A PN code generator 5 for generating a scramble signal and a self-synchronizing scramble means 6 for performing self-synchronous scrambling processing by superimposing on the signal subjected to the synchronous scramble processing controlled by the output of the mark ratio detection circuit 3. Synchronous scramble circuit (S.SCR circuit) 7, self-synchronous scramble control circuit (S.SCR control circuit) 8 and self-synchronous scramble signal generator (S.SCR generator) Vessel)
It is composed of 9 and 9.

As shown in FIG. 1 (b), the reception signal processing unit provided on the side of the receiving terminal opposite to the self-synchronization type descrambling circuit (S.DSCR circuit) constituting the self-synchronization type descrambling means 10 is provided. ) 11, self-synchronous descramble signal control circuit (S.DSCR control circuit) 12, self-synchronous descramble signal generator (S.DSCR generator) 13, frame synchronization circuit 14, and transmitted from the transmitting end station A control signal detection circuit 15 for detecting a control signal, a descrambling circuit 16 for restoring the synchronous scrambling process performed on the transmitting side, and a PN code generator 5 for generating the descramble signal, which is the same as the transmitting side. The reception signal processing circuit 17 performs reverse speed conversion to extract additional bits, and the code conversion circuit 18 converts a unipolar signal into a BnZS code.

In FIG. 1 (a), a BnZS code format digital multiplexed signal 101 input from a digital multiplexing terminal device not shown in the drawing is code-converted by a code conversion circuit 1 into a unipolar signal 102, which is then transmitted. It is input to the processing circuit 2, where additional bits such as a parity check bit, a frame synchronization signal, a meeting monitoring signal, etc. are inserted, and the wireless section signal 103 is sent to the scramble circuit 4. The wireless section signal 103 comprises an M-stage shift register and is controlled by a timing signal 104 from the transmission signal processing circuit 2. The PN code generator 5 outputs a PN code output 10 from the PN code generator 5.
The signal in the data section excluding the additional bits is subjected to random code conversion by 5 and sent to the S.SCR circuit 7. The processing up to this point is the same as the scramble processing in the conventional signal processing method.

Generally, there is no regularity in the characteristics of a multiplexed signal having a high degree of multiplicity, and in a normal line use condition, the characteristic of a digital multiplexed signal 101 from a digital multiplexing terminal device is close to a random code, and the mark of a unipolar signal 102 is indicated. The rate is also close to 50%.
This value is a predetermined mark rate (eg 10%)
Control signal 10 of the output of the mark ratio detection circuit 3
6 is configured to be "H" level. At this time SS
The CR control circuit 8 is in the cutoff state, the scramble signal is not input to the S.SCR circuit 7, and the radio section signal 107 randomly converted in the scramble circuit 4 is directly used as the baseband signal 108 in the modulator of the transmission device (see FIG. (Not shown) and sent to the opposite relay station. in this case,
As described above, since the unipolar signal 102 has a property close to a random code, the transmission spectrum is sufficiently spread only by the scrambling process by the scrambling circuit 4, and the equalizing circuit of the receiving device does not operate abnormally.

On the other hand, when the communication line is in a dormant state and the information signal is not input to the digital multiplexing terminal equipment, the digital multiplexed signal 101 does not become a series of "0" because of the BnZS code, and contains many positive and negative pulses. However, the code-converted unipolar signal 102 is in a continuous state of "0", and the mark ratio detection circuit 3 detects a decrease in the mark ratio. If this value is below a predetermined mark rate (for example, 5%),
The control signal 106 changes from "H" level to "L" level. On the other hand, the S.SCR control circuit 8 changes from the blocking state to the passing state when the next timing signal 104 is input, and at the same time, the S.SCR
The generator 9 starts operation from the reset state and its output
In addition to the synchronous scrambling process by the scramble circuit 4, the self-synchronous scrambling process is applied to the wireless section signal 107 in addition to the S.SCR circuit 7. Therefore, even if the unipolar signal 102 is in a continuous state of "0", the spread spectrum is sufficiently performed. The mark ratio detection circuit 3 is controlled by the timing signal 104, and is composed of a counter that counts pulses in one frame period. The above-described mark ratio determination is performed before the end of the frame period. The control signal 106 is applied to the transmission signal processing circuit 2 and is transmitted to the receiving terminal side using one of the monitoring bits in the additional bits.

On the receiving terminal side opposite to the above, the control signal transmitted from the transmitting terminal side is detected by the monitoring bit in the additional bits, and the self-synchronous descramble means corresponding to the transmitting side is detected.
Operate 10 to restore the original signal. That is, in FIG. 1B, the received and demodulated baseband signal 109
Is descrambled by the S.DSCR circuit 11 to obtain a wireless section signal 110 that has undergone only synchronous scrambling processing corresponding to the wireless section signal 107 on the transmitting side. This signal is frame-synchronized in the frame synchronization circuit 14, and is applied to the code conversion circuit 18 via the descramble circuit 16 and the reception signal processing circuit 17, where it is converted into the BnZS code and the digital multiplexed signal 101 on the transmission side. The output signal 111 is the same as that of, and is sent to a digital multiplexing terminal device (not shown).

The control signal detection circuit 15 receives the control of the frame synchronization signal 112 extracted by the frame synchronization circuit 14, detects the control signal from the monitoring bit of the branch signal 113 branched from the output of the frame synchronization circuit 14, and transmits the control signal. The control signal 114 of "H" level or "L" level is sent to the S.DSCR control circuit 12 and the S.DSCR generator 13 in response to the control signal transmitted from the. The S.DSCR control circuit 12 and the S.DSCR generator 13 are controlled by the control signal 114 and the frame synchronization signal 112, and are similar to the S.SCR control circuit 8 and the S.SCR generator 9 on the transmission terminal side. Is configured to start and stop the descrambling process at frame breaks in synchronization with the self-synchronizing scramble means on the transmitting side, and prevent a bit error from occurring at the time of switching.

According to the above configuration, the transmission spectrum is flattened regardless of the mark ratio of the unipolar signal 102, and therefore the adaptive equalization circuit of the receiving device does not operate abnormally, and the digital multiplexed signal on the transmitting terminal side. 101 is transmitted without error to the digital multiplexing terminal equipment on the receiving terminal side. Further, since the spread spectrum is always sufficiently performed, the interference with the adjacent line and other conditions do not deteriorate. The self-synchronous scramble system has a drawback that a 1-bit error occurring in a transmission path affects other bits, but in this system, the self-synchronous scramble process is performed only when the amount of transmitted information is small. This can minimize this effect.

In the embodiment of FIG. 1 (b) described above, the branch signal 113 input to the control signal detection circuit 15 is configured to be branched from the output of the frame synchronization circuit 14, but it is branched from the front of the frame synchronization circuit 14. Alternatively, the control signal may be detected from the reception signal processing circuit 17. Further, the above-mentioned embodiment is configured to perform the self-synchronous scramble processing on all bits including the additional bit by the ordinary self-synchronous scramble and descramble circuit. By using the circuit described in (1), it is possible to configure a circuit that performs the self-synchronous scramble process only in the data section excluding the additional bits. In this case, it is possible to detect the frame synchronization signal and the control signal before the self-synchronization type descrambling means. Further, in the above-mentioned embodiment, the transmitting side performs the scrambling process and then the self-synchronous scrambling process, and the receiving side performs the self-synchronous descramble process and then the synchronous scrambling process. The self-synchronous scramble means 6 of FIG. 1 (a) is provided in front of the scramble circuit 4 in reverse order, and the self-synchronous descramble means 10 of FIG. 1 (b) is inserted after the descramble circuit 16. It can also be configured as follows. Although the above description has been made for the BnZS code, it is a zero continuous suppression code having similar properties.
Similar processing is possible for HDBn codes (High Density Bipolar n).

〔The invention's effect〕

As described above in detail, according to the signal processing method of the present invention, the self-synchronous scrambling and descrambling means is added to the conventional digital radio communication line without changing the frame structure, and the code-converted unipolar is added. By detecting the mark ratio of the signal and operating it only when the mark ratio is small, there is an effect that a data signal in a transmission code format such as BnZS code or HDBn code can be transmitted without error regardless of the mark ratio.

[Brief description of drawings]

1 (a) and 1 (b) are block diagrams showing configurations of a transmission signal processing unit and a reception signal processing unit according to an embodiment of the present invention. 1, 18 ... Code conversion circuit, 2 ... Transmission signal processing circuit, 3 ...
Mark ratio detection circuit, 4 scramble circuit, 5 ...
PN code generator, 6 ... Self-synchronizing scrambling means, 7
...... Self-synchronous scramble circuit (S.SCR circuit), 8 ...
… Self-synchronous scramble control circuit (S.SCR control circuit), 9 …… Self-synchronous scramble signal generator (S.SC
R generator), 10 …… Self-synchronous descrambling means, 11
...... Self-synchronous descramble circuit (S.DSCR circuit), 12
...... Self-synchronous descramble control circuit (S.DSCR control circuit), 13 …… Self-synchronous descramble signal generator (S.DSCR control circuit)
DSCR generator), 14 ... Frame synchronization circuit, 15 ... Control signal detection circuit, 16 ... Descramble circuit, 17 ... Received signal processing circuit.

Claims (1)

[Claims] 1. A signal processing system for applying synchronous scrambling and descrambling processing to a transmission signal at a transmitting end station and a receiving end station of a digital wireless communication line, wherein a mark of a unipolar signal subjected to code conversion is provided on the transmitting end station side. Mark ratio detection means for detecting a rate and generating a control signal; self-synchronous scramble means which operates in response to the control signal and superimposes on the synchronous scramble processing to perform self-synchronous scramble processing; Control information transmitting means for transmitting a signal to the receiving terminal station by means of additional bits inserted into the transmission signal, wherein the receiving terminal station side receives the control signal from the additional bits transmitted from the transmitting terminal station. Control signal detecting means for detecting, and a self-synchronous descrambler which operates in response to the output of the control signal detecting means to restore the self-synchronous scramble processing. Signal processing method being characterized in that a rumble means.