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JPH069243B2 - Solid-state image sensor - Google Patents
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JPH069243B2 - Solid-state image sensor - Google Patents

Solid-state image sensor

Info

Publication number
JPH069243B2
JPH069243B2 JP62219461A JP21946187A JPH069243B2 JP H069243 B2 JPH069243 B2 JP H069243B2 JP 62219461 A JP62219461 A JP 62219461A JP 21946187 A JP21946187 A JP 21946187A JP H069243 B2 JPH069243 B2 JP H069243B2
Authority
JP
Japan
Prior art keywords
solid
state image
image sensor
charge injection
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62219461A
Other languages
Japanese (ja)
Other versions
JPS6461056A (en
Inventor
幸彦 前島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP62219461A priority Critical patent/JPH069243B2/en
Publication of JPS6461056A publication Critical patent/JPS6461056A/en
Publication of JPH069243B2 publication Critical patent/JPH069243B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Light Receiving Elements (AREA)
  • Photometry And Measurement Of Optical Pulse Characteristics (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は固体撮像素子に関し、特に狭禁制帯幅の半導体
を用いた固体撮像素子に関する。
The present invention relates to a solid-state image sensor, and more particularly to a solid-state image sensor using a semiconductor having a narrow bandgap.

〔従来の技術〕[Conventional technology]

一般に、赤外線検知素子においては狭禁制帯幅の半導体
を用いたものが高感度である事が知られており、単体の
赤外線検知素子を一次元、あるいは二次元に配列した構
成により高感度の固体撮像素子が得られる。
In general, it is known that infrared detectors that use semiconductors with a narrow bandgap have high sensitivity, and a single infrared detector is arranged in a one-dimensional or two-dimensional array to provide a highly sensitive solid-state sensor. An image sensor is obtained.

このような固体撮像素子の構成としては、例えば、ソサ
イェティ・オブ・ホトオプティカル・インスツルメンテ
ィション・エンジニアーズ(Society of Photooptical I
nstrumentation Engineers)第443巻1983年第1
20頁に記載されているように、狭禁制帯幅の半導体に
よる赤外線感応層を有する半導体基板上に赤外線検知素
子を配列し信号読出用CCD(Charge Coupled Devices)
上に配列して設けられた信号電荷注入領域のそれぞれと
赤外線検知素子のそれぞれを電気的に接続したハイブリ
ッド構造が知られている。
Examples of the configuration of such a solid-state image pickup device include, for example, Society of Photooptical Instrument Engineers (Society of Photooptical I
nstrumentation Engineers) Volume 443 Volume 1 1983
As described on page 20, an infrared detection element is arranged on a semiconductor substrate having an infrared sensitive layer made of a semiconductor having a narrow band gap, and a CCD (Charge Coupled Devices) for signal readout is arranged.
There is known a hybrid structure in which each of the signal charge injection regions arranged above and each of the infrared detection elements are electrically connected.

第2図は従来の固体撮像素子の一例を示す半導体チップ
の断面図である。
FIG. 2 is a sectional view of a semiconductor chip showing an example of a conventional solid-state imaging device.

第2図に示すように、半絶縁性CdTe基板9の上にエ
ピタキシャル成長させたP型Hg0.7Cd0.3Te層3の
表面にN型拡散領域4を配列して形成し、N型拡散領域
4のそれぞれに接続してインジウム電極5を形成する。
インジウム電極5のそれぞれに対応して電荷転送用CC
Dチップ6の上に形成された信号電荷注入領域7のそれ
ぞれにインジウム電極5のそれぞれを電気的に接続して
固体撮像素子を構成する。赤外線8の照射により変換さ
れた電荷は、インジウム電極5を介して信号電荷注入領
域7へ注入され、電荷転送用CCDチップ6による信号
処理を経て外部に映像信号が読み出される。
As shown in FIG. 2, N-type diffusion regions 4 are formed by arraying on the surface of the P-type Hg 0.7 Cd 0.3 Te layer 3 epitaxially grown on the semi-insulating CdTe substrate 9. The indium electrode 5 is formed by connecting to each of them.
CC for charge transfer corresponding to each of the indium electrodes 5
Each of the signal charge injection regions 7 formed on the D chip 6 is electrically connected to each of the indium electrodes 5 to form a solid-state image sensor. The charges converted by the irradiation of the infrared rays 8 are injected into the signal charge injection region 7 through the indium electrode 5, and the image signal is read out through the signal processing by the charge transfer CCD chip 6.

上記の様な構造が有効な理由を以下に述べる。赤外線検
知素子には狭禁制帯幅の半導体を用いた方が高感度が得
られる為に、ここではHg0.7Cd0.3Teを用いてい
る。この場合は最大波長5μm程度までの赤外線を検知
できる。Hg0.7Cd0.3Teのエピタキシャル成長の基
板としては赤外線を透過するCdTe層9が適してい
る。この赤外線検知素子を多数配列した場合、特に二次
元の配列の時、赤外線検知素子からの出力信号線は極め
て複雑になり、CCD等の信号読出用集積回路を通して
外部に映像信号を読み出す必要がある。Hg0.7Cd0.3
Teの様な狭禁制帯幅の半導体材料では高性能のCCD
は作れない。従って、高性能のCCDが容易に作れるシ
リコン上にこれを形成し、両者を接続する。Hg0.7
0.3Teは150℃以上の高温にさらされると種々の
結晶欠陥を生ずる為に、この接続の際には低温で圧着が
可能なインジウム電極を用いる。
The reason why the above structure is effective will be described below. Higher sensitivity can be obtained by using a semiconductor with a narrow bandgap for the infrared detection element, so Hg 0.7 Cd 0.3 Te is used here. In this case, infrared rays having a maximum wavelength of about 5 μm can be detected. The CdTe layer 9 which transmits infrared rays is suitable as a substrate for epitaxial growth of Hg 0.7 Cd 0.3 Te. When a large number of the infrared detecting elements are arranged, especially in the case of a two-dimensional arrangement, the output signal line from the infrared detecting element becomes extremely complicated, and it is necessary to read the video signal to the outside through a signal reading integrated circuit such as CCD. . Hg 0.7 Cd 0.3
High-performance CCD for semiconductor materials with narrow bandgap such as Te
Can't make Therefore, a high-performance CCD is formed on silicon which can be easily formed, and both are connected. Hg 0.7 C
Since d 0.3 Te causes various crystal defects when exposed to a high temperature of 150 ° C. or higher, an indium electrode capable of pressure bonding at a low temperature is used for this connection.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

従来の固体撮像素子は、液体窒素を用いて77K程度に
冷却して使用されることが多い。この場合、常時冷却し
ておくのではなく、実際に使用する時だけ冷却して使用
されるのが、効率的であり普通であるため、固体撮像素
子が常温と低温の温度サイクルを何度も経る事になる。
シリコンの熱膨脹係数は2.33×10−6/℃である
のに対し、CdTeは約4.5×10−6/℃と異な
り、更にインジウムは機械的強度の極めて弱い金属であ
る為に、この様に激しい温度変動があるとインジウム電
極5にストレスがかかり、遂には破壊に至る事がある。
これは検知部の出力信号が断線する事を意味するので、
この固体撮像素子は正常な動作をしなくなる。また、仮
に破壊にまで至らなくてもインジウム電極5の変形等に
よってその抵抗が微妙に変動して雑音源になる事もあ
る。従って、この固体撮像素子の信頼性は非常に低いも
のとなる。
Conventional solid-state imaging devices are often used after being cooled to about 77K using liquid nitrogen. In this case, it is efficient and normal to use it by cooling it only when it is actually used, rather than by constantly cooling it. Will pass.
While the coefficient of thermal expansion of silicon is 2.33 × 10 −6 / ° C., CdTe is different from about 4.5 × 10 −6 / ° C., and indium is a metal having extremely weak mechanical strength. If such a drastic temperature change occurs, stress is applied to the indium electrode 5, and eventually it may be destroyed.
This means that the output signal of the detector is disconnected, so
This solid-state image sensor does not operate normally. Even if the indium electrode 5 is not destroyed, its resistance may slightly change due to deformation of the indium electrode 5 and may become a noise source. Therefore, the reliability of this solid-state image sensor is extremely low.

本発明の目的は、激しい温度変動を経ても特性変動の少
ない信頼性の高い固体撮像素子を提供する事にある。
It is an object of the present invention to provide a highly reliable solid-state image pickup device that has little characteristic variation even after undergoing severe temperature variation.

〔問題点を解決するための手段〕 本発明の固体撮像素子は、シリコン基板上に直接或いは
緩衝層を介して形成された一導電型のHgCd1-x
eのような狭禁制帯幅半導体層と前記狭禁制帯幅半導体
層の表面に配列して形成された反対導電型の拡散領域と
を有する赤外線検出チップと、シリコンで形成され前記
拡散領域のそれぞれに対応して表面に配列された信号電
荷注入領域を有する電荷転送集積回路チップと、一端を
前記拡散領域に接合し他端を前記信号電荷注入領域に接
合して前記拡散領域のそれぞれと前記信号電荷注入領域
のそれぞれとを電気的に接続する柱状のインジウム電極
とを備えて構成される。
[Means for Solving the Problems] The solid-state imaging device of the present invention is a single conductivity type Hg x Cd 1-x T formed directly on a silicon substrate or via a buffer layer.
An infrared detection chip having a narrow bandgap semiconductor layer such as e and a diffusion region of opposite conductivity type formed on the surface of the narrow bandgap semiconductor layer, and each of the diffusion regions formed of silicon. A charge transfer integrated circuit chip having a signal charge injection region arranged on the surface corresponding to, and one of the diffusion regions and one of the diffusion regions by connecting one end to the diffusion region and the other end to the signal charge injection region. A columnar indium electrode electrically connecting each of the charge injection regions is provided.

〔作用〕[Action]

本発明の構成は、シリコンを狭禁制帯幅の半導体の成長
用基板として用い、狭禁制帯幅の半導体上に配列された
赤外線検知素子とシリコンを半導体基板とする信号読出
用集積回路チップ上の信号電荷注入領域をインジウム電
極で接続するものである。狭禁制帯幅の半導体基板とし
てシリコンを用いる事により、これと信号読出用集積回
路チップの熱膨脹率差はなくなり、激しい温度変動に対
してもインジウム電極の変形や破壊は防止される。従っ
て、信頼性の高い固体撮像素子が得られる。
According to the structure of the present invention, silicon is used as a substrate for growing a semiconductor having a narrow bandgap, and an infrared detection element arranged on the semiconductor having a narrow bandgap and a signal reading integrated circuit chip having silicon as a semiconductor substrate are arranged. The signal charge injection region is connected by an indium electrode. By using silicon as the semiconductor substrate having a narrow bandgap, the difference in the coefficient of thermal expansion between the semiconductor substrate and the signal reading integrated circuit chip is eliminated, and the indium electrode is prevented from being deformed or destroyed even when the temperature changes drastically. Therefore, a solid-state image sensor with high reliability can be obtained.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明す
る。
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例を示す半導体チップの断面図
である。第1図に示すように、P型又は半絶縁性シリコ
ン基板1の上にエピタキシャル成長した半絶縁性GaAs層
2と、半絶縁性GaAs層2の上にエピタキシャル成長した
P型Hg0.7Cd0.3Te層3と、P型Hg0.7Cd0.3
e層3の表面に配列して形成したN型拡散領域4とN型
拡散領域4のそれぞれに接続して設けられたインジウム
電極5と、シリコンを半導体基板とするCCDチップ6
の上にインジウム電極5のそれぞれに対応するように配
列して設けられた信号電荷注入層7を有している。
FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of the present invention. As shown in FIG. 1, a semi-insulating GaAs layer 2 epitaxially grown on a P-type or semi-insulating silicon substrate 1 and a P-type Hg 0.7 Cd 0.3 Te layer 3 epitaxially grown on the semi-insulating GaAs layer 2. And P-type Hg 0.7 Cd 0.3 T
An N-type diffusion region 4 formed on the surface of the e-layer 3 and an indium electrode 5 connected to each of the N-type diffusion region 4, and a CCD chip 6 having silicon as a semiconductor substrate.
The signal charge injection layer 7 is arranged on the upper surface of the indium electrode 5 so as to correspond to each of the indium electrodes 5.

シリコンとHg0.7Cd0.3Teは基本的にはよく似た結
晶型を持ってはいるが、その格子定数がシリコンの5.
43Åに対してHg0.7Cd0.3Teは6.48Åと大き
く異なる為に、従来はこれらの間のヘテロエピタキシー
は困難であるとされてきた。しかし、近年のエピタキシ
ャル成長技術の進歩により、例えば分子線エピタキシー
法等によって格子定数の大きく異なる物質同志のヘテロ
エピタキシーも可能になった。例えば、GaAsは格子
定数が5.65Åとやはりシリコンと異なるにもかかわ
らず、応用物理学会講演会予稿集、昭和60年春季号第
747頁に記載されている様にシリコン上に単結晶が成
長できる。また、プロシーディング・オブ・ザ・セコン
ド・インターナショナル・コンファレンス・オン・II−
IV・コンパウンズ(Proceedings of the 2nd Internatio
nal Conference on II-IV Compouds)1985年3月1
02〜107頁に記載されている様に、GaAs層の上
にもHg1-xCdTeの単結晶層の成長が可能であ
る。本実施例では、シリコン基板1の上に緩衝層として
半絶縁性GaAs層2を設け半絶縁性GaAs層2の上にP型H
0.7Cd0.3Te層3を設けることによって、P型Hg
0.7Cd0.3Te層3の表面に配列して形成したN型拡散
領域4とシリコンを基板とするCCDチップ6をインジ
ウム電極5で接続しても、両者の間の熱膨脹率の差の影
響を軽減できるので、激しい温度変動に際してもインジ
ウム電極5の変形又は破壊は生じにくくなる。またシリ
コン基板1は一般には波長3〜5μmの赤外線の殆どを
透過させるので、赤外線撮像素子の感度に対しての影響
は非常に小さく、波長5μmまでの赤外線像を検知でき
る。
Although silicon and Hg 0.7 Cd 0.3 Te have basically similar crystal types, the lattice constant of silicon is 5.
Since Hg 0.7 Cd 0.3 Te is significantly different from 6.48 Å against 43 Å, it has been conventionally considered that heteroepitaxy between them is difficult. However, due to recent advances in epitaxial growth technology, heteroepitaxy of substances having greatly different lattice constants has become possible by, for example, the molecular beam epitaxy method. For example, although GaAs has a lattice constant of 5.65Å, which is also different from that of silicon, a single crystal grows on silicon as described in Proceedings of the Japan Society of Applied Physics, Spring 1985, p. it can. Also, Proceeding of the Second International Conference on II-
IV ・ Compounds (Proceedings of the 2nd Internatio
nal Conference on II-IV Compouds) March 1985 1
As described on pages 02 to 107, it is possible to grow a single crystal layer of Hg 1-x Cd x Te on the GaAs layer. In this embodiment, a semi-insulating GaAs layer 2 is provided as a buffer layer on the silicon substrate 1 and a P-type H is provided on the semi-insulating GaAs layer 2.
g 0.7 Cd 0.3 Te layer 3 provides P-type Hg
Even if the N-type diffusion region 4 formed on the surface of the 0.7 Cd 0.3 Te layer 3 and the CCD chip 6 having a silicon substrate are connected by the indium electrode 5, the influence of the difference in thermal expansion coefficient between them is reduced. Therefore, the indium electrode 5 is unlikely to be deformed or destroyed even when the temperature changes drastically. Further, since the silicon substrate 1 generally transmits most of infrared rays having a wavelength of 3 to 5 μm, the influence on the sensitivity of the infrared imaging device is very small, and infrared images up to a wavelength of 5 μm can be detected.

ここで、P型Hg0.7Cd0.3Te層3の代りにP型Hg
0.8Cd0.2Te層を用いることにより、10μm程度ま
での赤外線像を検知できる。この場合には波長10μm
程度の赤外光がシリコン基板1で若干吸収されるため、
若干の感度低下は生ずるが、実用上は問題にならない。
Here, instead of the P-type Hg 0.7 Cd 0.3 Te layer 3, P-type Hg
By using the 0.8 Cd 0.2 Te layer, an infrared image up to about 10 μm can be detected. In this case, the wavelength is 10 μm
Since some infrared light is slightly absorbed by the silicon substrate 1,
Although a slight decrease in sensitivity occurs, it is not a problem in practical use.

また、シリコン基板上に上記の様な単結晶を成長させる
のは比較的難しい技術を必要とするが、多結晶を成長さ
せるのは容易である。例えば、Hg0.7Cd0.3Teの多
結晶を成長させ、その上にホトダイオードを形成した場
合には、その暗電流が、極めて大きい等の影響がある
が、大きな感度を必要としない場合には低コストの固体
撮像素子を実現できる効果がある。
Further, it is relatively difficult to grow such a single crystal on a silicon substrate, but it is easy to grow a polycrystal. For example, when a polycrystal of Hg 0.7 Cd 0.3 Te is grown and a photodiode is formed on it, the dark current is extremely large. However, if large sensitivity is not required, the cost is low. There is an effect that the solid-state image pickup device can be realized.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、固体撮像素子の使用時に
おける激しい温度変動に対してもインジウム電極の切
断、はがれの発生を抑えることが可能となり信頼性の高
い固体撮像素子を実現できるという効果を有する。
INDUSTRIAL APPLICABILITY As described above, the present invention has an effect that it is possible to realize a highly reliable solid-state image sensor because it is possible to suppress the occurrence of indium electrode disconnection and peeling even with a drastic temperature change during use of the solid-state image sensor. Have.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例を示す半導体チップの断面
図、第2図は従来の固体撮像素子の一例を示す半導体チ
ップの断面図である。 1…シリコン基板、2…半絶縁性GaAs層、3…P型Hg
0.7Cd0.3Te層、4…N型拡散領域、5…インジウム
電極、6…CCDチップ、7…信号電荷注入領域、8…
赤外線、9…CdTe基板。
FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of the present invention, and FIG. 2 is a sectional view of a semiconductor chip showing an example of a conventional solid-state imaging device. 1 ... Silicon substrate, 2 ... Semi-insulating GaAs layer, 3 ... P-type Hg
0.7 Cd 0.3 Te layer, 4 ... N type diffusion region, 5 ... Indium electrode, 6 ... CCD chip, 7 ... Signal charge injection region, 8 ...
Infrared, 9 ... CdTe substrate.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】シリコン基板上に直接或いは緩衝層を介し
て形成された一導電型のHgCd1-xTeのような狭
禁制帯幅半導体層と前記狭禁制帯幅半導体層の表面に配
列して形成された反対導電型の拡散領域とを有する赤外
線検出チップと、シリコンで形成され前記拡散領域のそ
れぞれに対応して表面に配列された信号電荷注入領域を
有する電荷転送集積回路チップと、一端を前記拡散領域
に接合し他端を前記信号電荷注入領域に接合して前記拡
散領域のそれぞれと前記信号電荷注入領域のそれぞれと
を電気的に接続する柱状のインジウム電極とを備えたこ
とを特徴とする固体撮像素子。
1. A narrow forbidden band width semiconductor layer such as Hg x Cd 1 -x Te of one conductivity type formed directly or through a buffer layer on a silicon substrate and a surface of the narrow forbidden band semiconductor layer. An infrared detection chip having diffusion regions of opposite conductivity type formed in an array; and a charge transfer integrated circuit chip having a signal charge injection region formed of silicon and arranged on the surface corresponding to each of the diffusion regions. A columnar indium electrode having one end bonded to the diffusion region and the other end bonded to the signal charge injection region to electrically connect each of the diffusion regions and each of the signal charge injection regions. A solid-state image sensor.
JP62219461A 1987-09-01 1987-09-01 Solid-state image sensor Expired - Lifetime JPH069243B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62219461A JPH069243B2 (en) 1987-09-01 1987-09-01 Solid-state image sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62219461A JPH069243B2 (en) 1987-09-01 1987-09-01 Solid-state image sensor

Publications (2)

Publication Number Publication Date
JPS6461056A JPS6461056A (en) 1989-03-08
JPH069243B2 true JPH069243B2 (en) 1994-02-02

Family

ID=16735790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62219461A Expired - Lifetime JPH069243B2 (en) 1987-09-01 1987-09-01 Solid-state image sensor

Country Status (1)

Country Link
JP (1) JPH069243B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994017557A1 (en) * 1993-01-19 1994-08-04 Hughes Aircraft Company Thermally matched readout/detector assembly and method for fabricating same
US8154099B2 (en) 2009-08-19 2012-04-10 Raytheon Company Composite semiconductor structure formed using atomic bonding and adapted to alter the rate of thermal expansion of a substrate
GB2489924A (en) * 2011-04-06 2012-10-17 Isis Innovation Integrating III-V or II-VI devices with high resistivity silicon or germanium substrates

Also Published As

Publication number Publication date
JPS6461056A (en) 1989-03-08

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