JPH0693004B2 - Integrated circuit test method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a test of an integrated circuit such as an LSI. In order to improve the operation speed at the time of the test, the test data is stored in advance inside the LSI, and at the time of the test operation. By providing a storage means for sequentially storing output data that has passed through the functional circuit while outputting the test data sequentially, it is possible to speed up the high-speed operation during the test, that is, the internal operation time. .

[Industrial application field]

The present invention relates to a test of an integrated circuit such as an LSI, and more particularly to a test method of an LSI, which is provided with means for storing test data of a functional circuit inside the LSI and performs the test.

[Conventional technology]

FIG. 4 shows a block diagram for explaining a conventional LSI test method.

In FIG. 4, the LSI under test 11 is configured by using, for example, a flip-flop (hereinafter referred to as FF) in an input / output stage and a combinational circuit, and it is assumed that a delay in signal transmission due to a plurality of logics occurs inside. .

The LSI tester 12 creates test data and a clock to be transmitted to the LSI under test 11, compares the test data passed through the LSI under test 11 with normal output data, and detects an abnormality.

When the LSI under test 11 is tested using this LSI tester 12, a set of test data is set each time a certain function is tested.
It is necessary to set the clock and then check the output, and when data is externally applied to the FF input, the load on the external LSI tester 12 limits the test speed.

[Problems to be solved by the invention]

According to the above conventional technique, the LSI tester 12 is used to
In the case of testing 1, it was necessary to perform complicated processing procedures, such as strobe time and tester load delay correction, and as a result, testing at high operating speeds was difficult.

Therefore, the L configured as shown in the test LSI 11 shown in FIG.
Since the FF is used for the output in SI, the delay of the output signal related to the internal delay cannot be determined, and the output data changes in synchronization with the clock.
When testing the quality of, it was necessary to carry out a test at actual operation or at an operating speed higher than that. For this reason, it became necessary to install an expensive LSI tester capable of high-speed test processing.

An object of the present invention is to solve the above-mentioned problems and to realize a test with a simple structure and an inexpensive device.

[Means for solving problems]

 FIG. 1 shows a block diagram of the principle of the LSI test system of the present invention.

In FIG. 1, the functional circuit 10 performs the main functional processing of the LSI under test 11. The shift register 1 sequentially stores test data input from the outside and given to the functional circuit 10,
During the test operation of the functional circuit 10, the stored test data is sequentially output, and the test data output through the functional circuit 10, that is, the output data is sequentially stored.

The first switching circuit 2 selects the input data from the outside during the normal operation of the functional circuit 10 and the test data from the shift register 1 during the test operation, and supplies them to the functional circuit. .

The second switching circuit 3 selects either the output data output from the functional circuit or the output data of the functional circuit 10 stored in the shift register 1 and outputs it to the outside.

[Action]

The case where the LSI under test 11 shown in FIG. 1 judges the quality of the functional circuit 10 is shown below.

If the test data of the functional circuit 10 is stored in advance in the shift register 1 from the outside, first, the first switching circuit 2 is operated to output the output of the shift register 1 to the functional circuit.
Connect it so that it entangles with 10. Then shift register 1
While the test data is sequentially output to the functional circuit 10, the output data from the functional circuit 10 is sequentially stored from the end of the queue of the shift register 1.

At this time, the functional circuit 10 is operated at a predetermined operating speed, for example, the operating speed of the LSI to obtain output data, and after all the output data is stored, the second switching circuit 3 is operated to shift the shift register 1 Connect to output the stored data of.

Finally, use an LSI tester, for example,
The functional circuit 10 is read by reading the output data of the functional circuit 10 stored in the shift register 1 at the speed of the capability of the SI tester.
The quality of is determined.

〔Example〕

 FIG. 2 shows the first embodiment of the present invention.

In FIG. 2, those having the same reference numerals as those in FIG. 1 are the same functional blocks, and the first and third switching circuits 2, 4
Is given from the outside, and the first switching circuit 2 receives the input data given from the outside to the functional circuit 10 and One of the output test data is selected and output to the functional circuit 10. The third switching circuit 4 selects either the external test data or the data output via the functional circuit 10. Is selected and output to the shift register 1. The second switching circuit 3 selects either the output data from the functional circuit 10 or the output data from the shift register 1 according to signals * OD and * OC provided from the outside and outputs the selected data to the outside.

When the LSI shown in FIG. 2 is tested, TEST is set to “0” and test data is loaded in advance to the shift register 1 via the third switching circuit 4. Then, TEST is set to "1" to set the test operation state, and while sequentially outputting the test data loaded in the shift register 1 to the functional circuit 10 via the first switching circuit 2,
The data output through the fixed function 10 is transferred to the third switching circuit 4
It is sequentially loaded again into the shift register 1 via. Here, by giving a clock signal of a target speed from CLOCK, output data at a speed equivalent to the actual operation is stored in the queue in the shift register 1.

Finally, by giving "0" to * OD and "1" to * OC of the second switching circuit 2, the functional circuit 10 stored in the shift register 1
It becomes possible to read the output data of. At this time LS
For example, a device for determining the quality of output data is used for the output OUTB of I, and the LSI is tested by applying a clock at an arbitrary speed.

Next, FIG. 3 shows a second embodiment.

In FIG. 3, shift registers 1-1 and 1-2 store test data and output data of the functional circuit 10, respectively.

The first and second switching circuits 2 and 3 follow a signal * TEST which is given from the outside and selects one of the normal operation and the test operation, and the first switching circuit 2 does not operate during the normal operation. The input data from the INA is supplied to the functional circuit 10 with the test data stored in the first shift register 1-1 during the test operation. The second switching circuit 3 outputs the output data from the functional circuit 10 during the normal operation, and outputs the output data of the functional circuit 10 stored through the queue of the second shift register 1-2 during the test operation. The data is sequentially output to the outside.

When the LSI shown in FIG. 3 is tested, necessary test data is loaded in advance in the first shift register 1-1. continue*
By setting TEST to “0” and applying a clock having a target speed, the test data is output to the functional circuit 10, and the output data passing through the functional circuit is sequentially stored in the queue of the second shift register 1-2. go.

The test data ends here, and the second shift register 1-2
The queue is filled with output data and is output from the beginning of the previously stored output data via QUTB. At this time, the test is performed by installing an external device for judging the quality of the output data, that is, a tester, and changing to a clock having a speed sufficient for the test.

〔The invention's effect〕

As described above in detail, according to the present invention, the LSI under test is
By providing a storage means to store the test data and output data of the functional circuit inside the LSI, it is possible to perform the test at the same speed as the actual use without using a dedicated LSI tester that operates at high speed. This is effective in easily determining the operation delay failure of.

In addition, by removing the LSI itself as a defect, it is also effective in reducing the initial defect in actual use.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of an LSI test system of the present invention, FIG. 2 is a first embodiment of the present invention, FIG. 3 is a second embodiment of the present invention, and FIG. 4 is a conventional LSI test system. It is a block diagram explaining. In the drawing, 1,1-1,1-2 are shift registers, 2,3,4 are switching circuits, 10 is a functional circuit, 11 is an LSI under test, and 12 is an LSI tester. Show.

Claims (2)

[Claims] 1. In an integrated circuit, a functional circuit (10) and test data to be given to the functional circuit (10) are sequentially stored, and at the time of a test operation of the functional circuit (10),
Storage means (1) for sequentially storing output data that has passed through the functional circuit (10) while sequentially supplying the test data to the functional circuit (10), and test data output from the storage means (1) and externally First switching means (2) for selecting any one of the input data of (1) and giving it to the functional circuit (10), output data of the functional circuit (10) and the storage means (1).
A second switching means (3) for selecting and outputting any one of the output data of the functional circuit (10) stored in the functional circuit (10) stored in the storage means (1). While outputting test data for 10) to the functional circuit (10) successively, the output data passed through the functional circuit (10) is stored in the storage means (1) and stored in the storage means (1). An integrated circuit test system characterized by outputting the output data of the functional circuit (10) to the outside of the integrated circuit for testing. 2. The integrated circuit test system according to claim 1, wherein said storage means (1) is a first-in first-out queue.