JPH069307B2 - Method for manufacturing composite circuit board - Google Patents
Method for manufacturing composite circuit boardInfo
- Publication number
- JPH069307B2 JPH069307B2 JP62184009A JP18400987A JPH069307B2 JP H069307 B2 JPH069307 B2 JP H069307B2 JP 62184009 A JP62184009 A JP 62184009A JP 18400987 A JP18400987 A JP 18400987A JP H069307 B2 JPH069307 B2 JP H069307B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- glass
- conductor
- composite circuit
- connecting conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by conductive adhesives
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Combinations Of Printed Boards (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は各種電子機器に用いられる回路モジュール・混
成集積回路等における回路基板に関するものであり、特
に高密度実装のために積層化・複合化した複合回路基板
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board in a circuit module, a hybrid integrated circuit or the like used in various electronic devices, and in particular, a composite formed by stacking and compounding for high-density mounting. It relates to a circuit board.
従来の技術 近年電子部品の小形化・高密度実装化の進展には著しい
ものがあり、特に回路基板の多層化・積層化が多方面で
検討されている。2. Description of the Related Art In recent years, there have been remarkable advances in miniaturization and high-density mounting of electronic components, and in particular, multi-layering / multi-layering of circuit boards has been studied in various fields.
たとえば、グリーンシート法によるCR内蔵多層セラミ
ック基板については、ISHM日本本部発行のインター
ネプコン・ジャパン/セミコンダクター,86ISHM
特別セミナー予稿集のP.25〜P.32に記載されて
いる。この場合、高密度化という点では従来の厚膜印刷
法による回路基板等と比較して優れている半面、下記の
欠点を有している。第1に電極材料・抵抗体材料・絶縁
材料・誘電体材料の異種材料を同時焼結するため、その
材料選定・製造工程を厳密に管理する必要があり、また
含有する有機材料の飛散性が悪いため、短時間焼成が困
難である。以上の理由により、製造コストが高いという
欠点を有している。For example, regarding the CR built-in multilayer ceramic substrate by the green sheet method, Internepcon Japan / Semiconductor, 86ISHM, published by ISHM Japan Headquarters
P. of Special Seminar Proceedings 25-P. 32. In this case, in terms of high density, it is superior to the conventional circuit board and the like by the thick film printing method, but has the following drawbacks. First, since different materials such as electrode material, resistor material, insulating material, and dielectric material are co-sintered, it is necessary to strictly control the material selection and manufacturing process. Since it is bad, it is difficult to fire for a short time. For the above reasons, it has a drawback that the manufacturing cost is high.
また、第2として内層に抵抗体を構成する場合、抵抗値
修正が困難である。これは、抵抗体上に絶縁層が介在す
るため、レーザ・ビーム等の透過が不可能なためであ
る。そのため、高精度な抵抗素子を内層に形成すること
は不可能である。Secondly, when a resistor is formed in the inner layer, it is difficult to modify the resistance value. This is because the insulating layer is interposed on the resistor, so that the laser beam or the like cannot be transmitted. Therefore, it is impossible to form a highly accurate resistance element in the inner layer.
以上のグリーンシート法の欠点を克服する方法として
は、焼結済のセラミック基板の用いて回路形成を施こし
た複数個の回路基板に対して、それらをはんだにより接
合した積層型混成ICの試みが上げられる。これは特開
昭62−43197号公報に記載されている。前記のは
んだ接合法は、その特長として下記の点があげられる。As a method for overcoming the above-mentioned drawbacks of the green sheet method, a trial of a laminated hybrid IC in which a plurality of circuit boards on which circuits have been formed by using a sintered ceramic board is joined by soldering Can be raised. This is described in JP-A-62-43197. The above-mentioned solder joining method has the following features.
(1) 電気的,機械的接合を同時にリフローで行えるた
め経済的である。(1) Economical because electrical and mechanical joining can be performed simultaneously by reflow.
(2) 各基板毎に特性確認ができるため、歩留りを向上
させることができる。(2) Since the characteristics can be confirmed for each substrate, the yield can be improved.
(3) 設計変更に対し、各基板の一部を変更すればよ
く、敏速な開発と試作対応ができる。(3) With respect to design changes, only a part of each board needs to be changed, which enables rapid development and trial production.
(4) 各基板ごとに抵抗,コンデンサ,インダクタン
ス,部品実装用として機能を分割するため、クロストー
ク等の回路設計上の問題を簡素化できる。(4) Since the functions are divided for each substrate, such as resistance, capacitor, inductance, and component mounting, problems such as crosstalk in circuit design can be simplified.
(5) 抵抗体のレーザートリミングを行った後、各基板
間の接合を行うため高精度な抵抗素子が得られる。(5) Since the resistors are laser-trimmed and then the substrates are joined together, a highly accurate resistive element can be obtained.
以上の特長を有したR.C.L内蔵型積層化複合回路基板を
提供することが前記発明の目的であった。It was an object of the invention to provide a laminated composite circuit board with built-in RCL having the above features.
発明が解決しようとする問題点 しかしながら特開昭62−43197号公報に見られる
焼結済セラミック回路基板をはんだで接合するはんだ接
合法は、下記の問題点を有している。第1の問題点は、
温度サイクル等による熱疲労による破断を起こしやすい
点である。特に電極材質としてAg,AgPd,Cu等の厚膜電
極を用いた場合、はんだ中のSn拡散によって合金層を形
成し、機械的に脆くなるという接続信頼性上の欠点を有
している。Problems to be Solved by the Invention However, the solder joining method for joining a sintered ceramic circuit board, which is disclosed in JP-A-62-43197, with solder has the following problems. The first problem is
This is a point that breakage easily occurs due to thermal fatigue due to temperature cycles and the like. In particular, when a thick film electrode such as Ag, AgPd, or Cu is used as the electrode material, there is a drawback in connection reliability that an alloy layer is formed due to Sn diffusion in the solder and mechanically becomes brittle.
また、第2の問題点として、後往低において部品あるい
はICベアチップを実装する際、接合に用いたはんだの
融点以下でなければならないという操作温度の制約があ
った。実際には部品実装は通常、Sn/Pb=60/40程度の共
晶はんだが用いられるが、はんだ付け温度としては20
0℃〜250℃でのはんだ浸漬またはリフロー法等が使
用されているえ。またICベアチップのボンディングに
しても、超音波併用熱圧着方式で200℃〜300℃程
度の予熱が必要となる。以上の後工程加熱条件を考慮に
入れると、はんだによる基板接合法では、はんだの融点
が高い高温はんだしか使用できない。具体的には、Pb含
有率90%以上が必要となる。一般的にはんだ組成中の
Pbが多くなると、はんだが酸化されやすくなり、いわゆ
る「イモはんだ」が発生しやすくなる。この現象は接合
強度劣化を招きやすく、信頼性上の問題が多い。以上の
ように接合に用いられるはんだが共晶はんだの場合、部
品実装に温度制約があり通常のはんだ付けや、ボンディ
ングが不可能となる点と、あるいは接合に高温はんだを
使用した場合、Pb酸化を抑制する方法をとらなければ接
合強度とその信頼性に問題が生じる点が欠点として残っ
ている。これらを要約すると、後工程での部品実装時の
加熱条件を考慮すると、適合するはんだ材料が非常に限
られてくるということである。以上が第2の問題点であ
る。Further, as a second problem, when mounting a component or an IC bare chip in a low backlash, there is a restriction on the operating temperature that it must be below the melting point of the solder used for joining. Actually, eutectic solder with Sn / Pb = 60/40 is usually used for component mounting, but the soldering temperature is 20
The solder dipping or reflow method at 0 ° C to 250 ° C is used. Moreover, even in the bonding of the IC bare chip, preheating at about 200 ° C. to 300 ° C. is required by the thermocompression bonding method using ultrasonic waves. Taking the above post-process heating conditions into consideration, only high-temperature solder having a high melting point can be used in the substrate joining method using solder. Specifically, a Pb content of 90% or more is required. Generally in the solder composition
When Pb is increased, the solder is easily oxidized and so-called "potato solder" is likely to be generated. This phenomenon easily causes deterioration of the bonding strength and has many problems in reliability. As described above, when the solder used for joining is eutectic solder, there is a temperature restriction on component mounting and normal soldering or bonding becomes impossible, or when high temperature solder is used for joining, Pb oxidation The problem remains that the bonding strength and its reliability will be problematic if a method of suppressing the above is not taken. To summarize these, the solder materials that can be used are very limited in consideration of the heating conditions for mounting components in the subsequent process. The above is the second problem.
第3の問題点として積層された各基板間には、20μm
〜200μm程度の間隙が存在するため高温高湿中での
湿気の進入を阻止できず耐湿性能に問題が生じる点があ
げられる。具体的には配線導体間のマイグレーションに
よる短絡不良,内蔵抵抗,コンデンサ,インダクタンス
素子または実装部品の故障,吸湿による絶縁不良が発生
しやすい。The third problem is that the space between the stacked substrates is 20 μm.
Since there is a gap of about 200 μm, it is impossible to prevent the ingress of moisture in high temperature and high humidity, which causes a problem in moisture resistance performance. Specifically, short circuits due to migration between wiring conductors, failures in built-in resistors, capacitors, inductance elements or mounted parts, and insulation failures due to moisture absorption are likely to occur.
以上のように、特開昭62−43197号公報に見られ
るはんだ接合法は、安価で、かつRCL内蔵可能で高密
度な積層化複合回路基板を提供できるものの、その接合
強度と接合信頼性及び耐湿性の点で非常に問題が多く、
実用性に乏しいものであった。As described above, the solder joining method disclosed in Japanese Patent Laid-Open No. 62-43197 can provide a high-density laminated composite circuit board that is inexpensive and can be embedded in the RCL, but its joining strength, joining reliability, and There are many problems in terms of moisture resistance,
It was poor in practicality.
本発明はかかる点に鑑みてなされたもので、接合強度及
びその信頼性に優れ、更に耐湿性に優れたRCL内蔵型
積層化複合回路基板を提供することを目的としている。The present invention has been made in view of the above points, and an object of the present invention is to provide an RCL built-in type laminated composite circuit board having excellent bonding strength and reliability, and also excellent moisture resistance.
問題点を解決するための手段 本発明は上記問題点を解決するため、焼結済みセラミッ
ク等から成る無機系絶縁基板上に電極形成、あるいは抵
抗素子形成、回路配線形成を施こした複数個の回路基板
を用いている。ここまでははんだ接合法と同様である。
前記回路基板の所望の電極上に接続用導体を塗布形成
し、更に各接続用導体の周囲及び間隙にシール用ガラス
を塗布形成した後、前記接続用導体が相い対向し、その
周囲をシール用ガラスが密閉するように各回路基板を積
層した状態で焼成温度350℃〜700℃にて焼成する
ことにより、前記接続用導体及びシール用ガラスを焼結
接着させる点が本発明の特徴である。また、接続用導体
としてはAg,Pd,Pt,Cuのうち、いずれか種の金属また
はこれらの混合物、あるいは前記金属を主成分とし、ガ
ラスフリット,有機バインダ等とを混練したペースト状
導体組成物を使用している。シール用ガラスとしては軟
化点300℃〜700℃のガラスフリット、あるいは前
記ガラスフリットを主成分とし、有機バインダを添加し
て混練したペースト状絶縁体組成物を使用している。Means for Solving the Problems In order to solve the above problems, the present invention provides a plurality of electrodes, resistance elements, or circuit wirings formed on an inorganic insulating substrate made of sintered ceramic or the like. It uses a circuit board. The process up to this point is the same as the solder joining method.
A connection conductor is applied and formed on a desired electrode of the circuit board, and sealing glass is applied and formed around each connection conductor, and then the connection conductors face each other and seal the periphery. It is a feature of the present invention that the connecting conductor and the sealing glass are sintered and adhered by baking at a baking temperature of 350 ° C. to 700 ° C. in a state where each circuit board is laminated so that the glass for sealing is sealed. . As the connecting conductor, any one of Ag, Pd, Pt, and Cu, or a mixture thereof, or a paste-like conductor composition containing the above metal as a main component and kneading with a glass frit, an organic binder, or the like. Are using. As the glass for sealing, a glass frit having a softening point of 300 ° C. to 700 ° C., or a paste-like insulator composition containing the above glass frit as a main component and kneading with an organic binder added is used.
作 用 本発明は、前記の構成により、前述した従来の焼結済セ
ラミックを用いたはんだ接合法の問題点を解決すること
となる。本発明においては、はんだ以外の高融点金属と
してAg,Pd,Pt,Cuのうちいずれか1種の金属またはこ
れらの混合物を用いている。望ましくは、これらの金属
を微粉化した金属粉にガラスフリット,有機バインダを
添加しペースト状に混練した導体組成物を用いることが
できる。これは回路基板表面の電極上に接続用導体を着
膜する際、スクリーン印刷法を用いることができ実用性
が高い。Operation The present invention solves the above-mentioned problems of the conventional solder joining method using the sintered ceramics. In the present invention, any one metal of Ag, Pd, Pt, and Cu or a mixture thereof is used as the refractory metal other than solder. Desirably, a conductor composition in which glass frit and an organic binder are added to metal powder obtained by pulverizing these metals and kneaded into a paste can be used. This is highly practical because a screen printing method can be used when depositing the connecting conductor on the electrodes on the surface of the circuit board.
以上の接続用導体は350℃〜700℃の温度領域で回
路基板表面の電極、たとえばAg,AgPd,Cu等に対し拡散
・合金化する。あるいは、ガラスフリットを添加したペ
ースト状導体組成物の場合は、ガラスフリットが回路基
板表面の電極に対し、適度に濡れることにより接合力を
得ることができる。この接続用導体の形状・組成・焼成
雰囲気・温度をコントロールすることで電気的接続性と
機械的接合強度及びその信頼性を得ることができる。The above connecting conductor is diffused / alloyed with electrodes on the surface of the circuit board, for example, Ag, AgPd, Cu, etc., in the temperature range of 350 to 700 ° C. Alternatively, in the case of a paste-like conductor composition to which glass frit is added, the glass frit can obtain a bonding force by appropriately wetting the electrode on the surface of the circuit board. By controlling the shape, composition, firing atmosphere, and temperature of this connecting conductor, it is possible to obtain electrical connectivity, mechanical bonding strength, and reliability thereof.
更に接続用導体の周囲に設けたシール用ガラスについて
も、300℃〜700℃にて充分に軟化するガラスフリ
ット組成を選択することにより接続導体間を密閉構造と
し、耐湿性に優れた複合回路基板を提供することとな
る。また、接続用導体のみであってもはんだによる接合
に比べて優れた信頼性を有しているが、更にシール用ガ
ラスの接着効果により、各基板間の接合を補強する構造
であるため、接合強度が大幅に向上する。Further, regarding the sealing glass provided around the connecting conductor, a composite frit having excellent moisture resistance is formed by selecting a glass frit composition that is sufficiently softened at 300 ° C. to 700 ° C. to form a sealed structure between the connecting conductors. Will be provided. In addition, even if only the connecting conductor is used, it has superior reliability compared to soldering, but since the bonding effect of the sealing glass reinforces the bonding between the substrates, Strength is greatly improved.
実施例 以下本発明について図面を参照しながら詳細に説明す
る。第1図は本発明の一実施例における複合回路基板の
製造法を示す図である。第1図(a)は、本発明における
複合回路基板に用いる各回路基板の断面を示す図であ
る。第1図(a)において1は第1の回路基板、2は第2
の回路基板を示している。前記第1,第2回路基板1,
2は、それぞれ焼結済みセラミック等の無機系絶縁基板
であり、今回は純度96%のアルミナを使用している。
そのアルミナ表面には電極3が形成されている。これら
の回路基板は図中には省略されているがそれぞれ回路配
線形成,抵抗素子形成,コンデンサ素子形成,インダク
タンス素子形成,多層化等が厚膜印刷法,グリーンシー
ト法,薄膜法,メッキ法等によって施されたものを必要
に応じて使用すればよい。本実施例において電極3はCu
電極を用いており、厚膜Cuペーストをスクリーン印刷に
よってアルミナ基板上に塗布したものを850℃〜95
0℃の窒素雰囲気中で焼成することにより得られたもの
である。EXAMPLES Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing a method of manufacturing a composite circuit board according to an embodiment of the present invention. FIG. 1 (a) is a view showing a cross section of each circuit board used in the composite circuit board of the present invention. In FIG. 1 (a), 1 is a first circuit board and 2 is a second circuit board.
The circuit board of FIG. The first and second circuit boards 1,
Reference numeral 2 is an inorganic insulating substrate such as a sintered ceramic, and this time, alumina having a purity of 96% is used.
The electrode 3 is formed on the surface of the alumina. Although these circuit boards are omitted in the figure, circuit wiring formation, resistance element formation, capacitor element formation, inductance element formation, multilayering, etc. are thick film printing methods, green sheet methods, thin film methods, plating methods, etc. What was given by it may be used as needed. In this embodiment, the electrode 3 is Cu
An electrode is used, and a thick film Cu paste applied on an alumina substrate by screen printing is used at 850 ° C to 95 ° C.
It was obtained by firing in a nitrogen atmosphere at 0 ° C.
第1図(b)は、前記第1,第2の回路基板1,2の電極
上にそれぞれ接続用導体4とシール用ガラス5を塗布し
た状態を示している。接続用導体4は電極3と同様、厚
膜Cuペーストを用いてスクリーン印刷によって30μm
〜100μm程度の膜厚で塗布し乾燥させたものであ
る。接続用導体4に用いる厚膜Cuペーストとしては、Cu
粉80〜98wt%,ガラスフリット2〜20wt%,有機
バインダ2〜20wt%のものを使用した。また、Cu粉に
ついては650℃以下での焼結性が得やすいように、粒
径1.5μm以下の微粉を使用した。シール用ガラス5
は軟化点350℃〜500℃のガラスフリットを主成分
とし、有機バインダを添加して混練した厚膜ガラスペー
ストを使用し、スクリーン印刷によって前記接続用導体
4と等しい膜厚になるように塗布後、乾燥させたもので
ある。FIG. 1 (b) shows a state in which the connecting conductor 4 and the sealing glass 5 are applied onto the electrodes of the first and second circuit boards 1 and 2, respectively. Like the electrode 3, the connection conductor 4 is 30 μm thick by screen printing using a thick film Cu paste.
It is applied and dried in a film thickness of about 100 μm. The thick film Cu paste used for the connecting conductor 4 is Cu
80 to 98 wt% powder, 2 to 20 wt% glass frit, and 2 to 20 wt% organic binder were used. As for the Cu powder, a fine powder having a particle size of 1.5 μm or less was used so that the sinterability at 650 ° C. or less was easily obtained. Glass for seal 5
Is a glass frit having a softening point of 350 ° C. to 500 ° C. as a main component, a thick film glass paste added with an organic binder and kneaded, and applied by screen printing so as to have a film thickness equal to that of the connecting conductor 4. , Dried.
第1図(c)は接続用導体4及びシール用ガラス5を塗布
した第1の回路基板1と第2の回路基板2をそれぞれ前
記接続用導体4が相い対向するように積層した後、焼成
によって接合・一体化した複合回路基板の断面図であ
る。接続用導体4及びシール用ガラス5の焼成は、50
0℃〜650℃の窒素雰囲気中で同時に行い、第1の回
路基板1と第2の回路基板2を接合・一体化した。なお
接合強度とその信頼性を向上させる目的で接続用導体及
びシール用ガラス半乾燥状態で積層し、10g/10kg
程度の荷重を加えて再加熱することで、更に良好な接合
性が認められた。あるいは、焼成時に10g〜10kg程
度の荷重を加えても同様に接合性の向上が得られる。FIG. 1 (c) shows a structure in which the first circuit board 1 and the second circuit board 2 coated with the connecting conductor 4 and the sealing glass 5 are laminated so that the connecting conductors 4 face each other. FIG. 4 is a cross-sectional view of a composite circuit board joined and integrated by firing. Firing of the connecting conductor 4 and the sealing glass 5 is 50
The first circuit board 1 and the second circuit board 2 were joined and integrated by simultaneously performing them in a nitrogen atmosphere at 0 ° C to 650 ° C. For the purpose of improving the joint strength and its reliability, the conductor for connection and the glass for sealing are laminated in a semi-dried state, and 10 g / 10 kg
By applying a moderate load and reheating, a better bondability was confirmed. Alternatively, even if a load of about 10 g to 10 kg is applied at the time of firing, the bondability can be similarly improved.
以上の構成及び製造法により作製された複合回路基板は
電気的接合性に優れ、0.5mm×0.5mmのボンディン
グパッド面積において50mΩ以下の導体抵抗が得られ
た。また10mm×10mm角のテスト用回路基板2枚を使
用し、0.5mm×0.5mmのボンディングパッド40個
を四方に配置し、その周囲及び間隙にシール用ガラスを
配置して接合した試料において5kg・f以上の接着強度
が得られ、その性能が充分に実用性の高いものであるこ
とを確認した。The composite circuit board manufactured by the above structure and manufacturing method has excellent electrical bonding properties, and a conductor resistance of 50 mΩ or less was obtained in a bonding pad area of 0.5 mm × 0.5 mm. In addition, using two test circuit boards of 10 mm x 10 mm square, 40 bonding pads of 0.5 mm x 0.5 mm are arranged in all directions, and a sealing glass is arranged around the bonding pads and bonded to the sample. It was confirmed that an adhesive strength of 5 kg · f or more was obtained and the performance was sufficiently high in practical use.
なお本実施例においては、接続用導体4として溶融温度
の高いCu膜を使用しているため、後工程での部品のはん
だ付けや、ICベアチップのボンディング時の基板予熱
等において使用できる温度範囲が従来のはんだ接続法に
比べて非常に広い。In this embodiment, since the Cu film having a high melting temperature is used as the connecting conductor 4, the temperature range that can be used in the soldering of parts in the subsequent steps, the substrate preheating at the time of bonding the IC bare chip, etc. It is much wider than the conventional solder connection method.
また、接続用導体の周囲及び間隙をシール用ガラスで密
封する構造のため、湿気の侵入を防ぎ耐湿性に優れた複
合回路基板を実現している。Further, since the periphery of the connecting conductor and the gap are sealed with the sealing glass, a composite circuit board which prevents moisture from entering and has excellent moisture resistance is realized.
更に具体的な応用例として他の実施例を第2図に示す。
第2図は4個の回路基板を積層した実施例を示す図であ
り、断面構造を第2図(a)に、斜視図を第2図(b)に示し
てる。第2図において、6はIC実装用基板、7はコン
デンサブロック基板、8はインダクタンスブロック基
板、9は抵抗内蔵リードレスチップキャリア基板を示し
ている。Another embodiment is shown in FIG. 2 as a more concrete application example.
FIG. 2 is a view showing an embodiment in which four circuit boards are laminated, a sectional structure is shown in FIG. 2 (a), and a perspective view is shown in FIG. 2 (b). In FIG. 2, 6 is an IC mounting substrate, 7 is a capacitor block substrate, 8 is an inductance block substrate, and 9 is a leadless chip carrier substrate with a built-in resistor.
10,10′,10″,10は各基板表面上の電極を
示している。最下段のリードレスチップキャリア基板9
上には抵抗素子11が形成され、端面電極12によって
マザーボードに対してはんだ付けされる。13は各基板
の表裏を電気的に接続するスルーホールであり、そのス
ルーホール部の電極上には接続用導体14が塗布されて
いる。更に接続用導体14の周囲及び間隙にはシール用
ガラス18が塗布されており、前述した実施例と同様に
して各基板を積層した後、一括して焼成することにより
電気的にかつ機械的に一体化したRCL内蔵複合回路基
板を得ている。以上のようにして一体化された複合回路
基板の最上段であるIC実装用基板6上にICベアチッ
プ15がダイボンディングによって固定され、ボンディ
ングワイヤー16により、IC実装用基板上の配線と接続
されている。17はICベアチップの封止用樹脂を示し
ている。Reference numerals 10, 10 ', 10 "and 10 indicate electrodes on the surface of each substrate. The leadless chip carrier substrate 9 at the bottom.
A resistance element 11 is formed on the top and soldered to the mother board by the end face electrodes 12. Reference numeral 13 is a through hole that electrically connects the front and back of each substrate, and a connection conductor 14 is applied on the electrode of the through hole portion. Further, a sealing glass 18 is applied to the periphery and the gap of the connecting conductor 14, and the respective substrates are laminated in the same manner as in the above-described embodiment, and then fired collectively to electrically and mechanically. An integrated RCL built-in composite circuit board is obtained. The IC bare chip 15 is fixed by die bonding on the IC mounting board 6 which is the uppermost stage of the composite circuit board integrated as described above, and is connected to the wiring on the IC mounting board by the bonding wire 16. There is. Reference numeral 17 indicates a resin for sealing the IC bare chip.
以上のように本実式例によるRCL内蔵複合回路基板を
用いて高密度でかつ面実装対応の積層型混成集積回路が
形成される。As described above, by using the composite circuit board with built-in RCL according to the present example, a high-density and surface-mountable laminated hybrid integrated circuit is formed.
発明の効果 以上説明したように本発明によれば、下記に列記する諸
々の効果がある。Effects of the Invention As described above, according to the present invention, there are various effects listed below.
(1) 焼結済みセラミック等の無機系基板を用いた回路
基板をそれぞれ個々に作製後、接続用導体で接合する構
造のため、グリーンシート法等の同時焼結技術に比べて
製造方法が簡素化されかつ歩留りが向上する。その結果
低コスト化が実現できる。(2) 個々の基板において、
予め抵抗素子形成・抵抗値修正を実施した後、各基板間
の接合を行う際、その焼成温度が350℃〜700℃と
比較的低温のため、抵抗値変化が非常に小さくなりその
結果、高精度な抵抗素子が複合回路基板内部に内蔵でき
る。(1) The manufacturing method is simpler than the simultaneous sintering technology such as the green sheet method because the structure is such that each circuit board that uses an inorganic substrate such as sintered ceramics is individually manufactured and then joined with the connecting conductor. And the yield is improved. As a result, cost reduction can be realized. (2) In each board,
After forming the resistance element and correcting the resistance value in advance, when the bonding between the substrates is performed, the firing temperature is relatively low at 350 ℃ ~ 700 ℃, the resistance value change is very small, resulting in high An accurate resistance element can be built in the composite circuit board.
(3) 従来のはんだ接合法の問題点であったSn拡散等
による接合強度劣化を防ぎ、基板間の接合信頼性が飛躍
的に向上する。(3) The deterioration of the bonding strength due to Sn diffusion or the like, which is a problem of the conventional solder bonding method, is prevented, and the bonding reliability between the substrates is dramatically improved.
(4) 溶融温度の高い接続用導体を使用するため、後工
程での部品実卒における温度条件として350℃以下の
任意の温度が選択できるため、はんだ接合法に比べて工
程設計が容易となる。(4) Since a connecting conductor with a high melting temperature is used, it is possible to select an arbitrary temperature of 350 ° C or less as a temperature condition for graduating parts in the subsequent process, making the process design easier than the solder joining method. .
(5) 各基板間の間隙をシール用ガラスで密封する構造
のため、耐湿性が向上すると同時に接合強度も向上す
る。(5) Since the gap between the substrates is sealed with the sealing glass, the moisture resistance is improved and the bonding strength is also improved.
以上のような諸効果が得られるため、本発明による複合
回路基板の製造方法は、その実用的効果は大なるものが
ある。Since the above-described various effects are obtained, the method for manufacturing a composite circuit board according to the present invention has a great practical effect.
第1図a〜cは本発明の一実施例における複合回路基板
の製造方法を示す工程図、第2図a,bは本発明の具体
的な応用例を示す断面図及び斜視図である。 1……第1の回路基板、2……第2の回路基板、3……
電極、4……接続用導体、5……シール用ガラス、6…
…IC実装用基板、7……コンデンサブロック基板、8
……インダクタンスブロック基板、9……抵抗内蔵リー
ドレスチップキャリア基板、10,10′,10″,1
0……電極、11……抵抗体、12……端面電極、13
……スルーホール、14……接続用導体、15……IC
ベアチップ、16……ボンディング用ワイヤー、17…
…封止用樹脂、18……シール用ガラス。1A to 1C are process diagrams showing a method for manufacturing a composite circuit board according to an embodiment of the present invention, and FIGS. 2A and 2B are a sectional view and a perspective view showing a concrete application example of the present invention. 1 ... First circuit board, 2 ... Second circuit board, 3 ...
Electrodes, 4 ... Connection conductor, 5 ... Sealing glass, 6 ...
... IC mounting board, 7 ... Capacitor block board, 8
...... Inductance block substrate, 9 ... Leadless chip carrier substrate with built-in resistor 10,10 ', 10 ", 1
0 ... Electrode, 11 ... Resistor, 12 ... End surface electrode, 13
...... Through hole, 14 ...... Connection conductor, 15 ...... IC
Bare chip, 16 ... Bonding wire, 17 ...
... Sealing resin, 18 ... Sealing glass.
Claims (4)
抗素子形成、回路配線形成を施こした複数個の回路基板
を有し、前記回路基板の所望の電極上に接続用導体を塗
布形成し、更に各接続用導体の周囲及び間隙にシール用
ガラスを塗布形成した後、前記接続用導体が相い対向
し、その周囲をシール用ガラスが密閉するように各回路
基板を積層した状態で焼成することにより、前記接続用
導体及びシール用ガラスを焼結接着し、電気的かつ機械
的に一体に構成したことを特徴とする複合回路基板の製
造方法。1. A plurality of circuit boards on which electrodes, resistance elements or circuit wirings are formed on an inorganic insulating substrate, and a connecting conductor is formed by coating on desired electrodes of the circuit board. In addition, after the sealing glass is applied and formed on the periphery and the gap of each connecting conductor, the connecting conductors face each other, and the circuit boards are laminated so that the sealing glass hermetically seals the periphery. A method for manufacturing a composite circuit board, characterized in that the connecting conductor and the sealing glass are sintered and adhered by firing to form an electrically and mechanically integrated body.
れか一種の金属またはこれらの混合物、あるいは前記金
属を主成分とし、ガラスフリット,有機バインダ等とを
混練したペースト状導体組成物であることを特徴とする
特許請求の範囲第1項記載の複合回路基板の製造方法。2. The conductor for connection is a paste-like conductor obtained by kneading a metal of any one of Ag, Pd, Pt and Cu, or a mixture thereof, or a glass frit, an organic binder or the like containing the metal as a main component. It is a composition, The manufacturing method of the composite circuit board of Claim 1 characterized by the above-mentioned.
℃のガラスフリット、あるいは前記ガラスフリットを主
成分とし、有機バインダを添加して混練したペースト状
絶縁体組成物であることを特徴とする特許請求の範囲第
1項記載の複合回路基板の製造方法。3. The glass for sealing has a softening point of 300 ° C. to 700 ° C.
2. A method for producing a composite circuit board according to claim 1, which is a glass frit at 0.degree. C. or a paste-like insulator composition containing the glass frit as a main component and kneading with an organic binder added. .
率系セラミック基板,チタン酸バリウム等の高誘電率系
セラミック基板,フェライト等の磁性体基板のうち、少
なくとも1種から成ることを特徴とする特許請求の範囲
第1項記載の複合回路基板の製造方法。4. An inorganic insulating substrate material comprising at least one of a low dielectric constant ceramic substrate such as alumina, a high dielectric constant ceramic substrate such as barium titanate, and a magnetic substrate such as ferrite. A method of manufacturing a composite circuit board according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62184009A JPH069307B2 (en) | 1987-07-23 | 1987-07-23 | Method for manufacturing composite circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62184009A JPH069307B2 (en) | 1987-07-23 | 1987-07-23 | Method for manufacturing composite circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6428889A JPS6428889A (en) | 1989-01-31 |
| JPH069307B2 true JPH069307B2 (en) | 1994-02-02 |
Family
ID=16145730
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62184009A Expired - Lifetime JPH069307B2 (en) | 1987-07-23 | 1987-07-23 | Method for manufacturing composite circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH069307B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19847537A1 (en) * | 1998-10-15 | 2000-05-04 | Mannesmann Vdo Ag | Circuit board with conductor tracks arranged on both sides |
| JP2005311188A (en) * | 2004-04-23 | 2005-11-04 | Fuchigami Micro:Kk | Multilayer wiring board |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS505374A (en) * | 1973-05-28 | 1975-01-21 | ||
| JPS602551B2 (en) * | 1977-07-13 | 1985-01-22 | ダイハツ工業株式会社 | Misshift prevention mechanism for gear shift operation device |
| JPS6243197A (en) * | 1985-08-21 | 1987-02-25 | 株式会社日立製作所 | Laminate type hybrid ic |
| JPS63220598A (en) * | 1987-03-10 | 1988-09-13 | 三菱鉱業セメント株式会社 | Ceramic multilayer interconnection board and manufacture of the same |
-
1987
- 1987-07-23 JP JP62184009A patent/JPH069307B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6428889A (en) | 1989-01-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6436316B2 (en) | Conductive paste and printed wiring board using the same | |
| JPS63107087A (en) | Hybrid integrated circuit board | |
| EP0997941B1 (en) | Conductive paste and ceramic printed circuit substrate using the same | |
| JP2001307547A (en) | Conductive composition and printed circuit board using the same | |
| JPH069307B2 (en) | Method for manufacturing composite circuit board | |
| JP2002043758A (en) | Multilayer substrate and manufacturing method thereof | |
| JP2005268672A (en) | substrate | |
| JP2885477B2 (en) | Multilayer wiring board and method of manufacturing the same | |
| JPS61108192A (en) | Low temperature sintered multilayer ceramic substrate | |
| JP2001143527A (en) | Conductive paste and ceramic wiring board using the same | |
| JP3666308B2 (en) | Conductive paste and ceramic electronic components | |
| JPS62196811A (en) | Ceramic substrate with built-in capacitor | |
| JP2000188475A (en) | Manufacture of ceramic multilayer substrate | |
| JPH11177016A (en) | Hybrid integrated circuit device | |
| JPH11126797A (en) | Wiring board connection structure | |
| JPS6016749B2 (en) | Packages for integrated circuits | |
| JPS60176296A (en) | Method of producing glazed resistance element interal multilayer substrate | |
| JPH04225297A (en) | Manufacture of ceramic board | |
| JPH0544200B2 (en) | ||
| JPH06232528A (en) | Hybrid integrated circuit board and manufacture thereof | |
| JP2839308B2 (en) | Multilayer wiring board | |
| JP2842707B2 (en) | Circuit board | |
| JPS60169194A (en) | Substrate for hybrid integrated circuits | |
| JPH0821780B2 (en) | Laminated composite ceramic substrate and manufacturing method thereof | |
| JPH0467360B2 (en) |