JPH0693222B2 - User definition macro instruction definition method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a microprogram control type information processing apparatus having a rewritable control memory, and particularly defines macro instructions created by a user in the information processing apparatus. Regarding the scheme.

[Conventional technology]

Conventionally, in a microprogram control type information processing apparatus having a rewritable control memory, when a macro instruction created by a user (user-defined macro instruction) is defined separately from a macro instruction which is basically provided by the system itself. , A microcode string corresponding to the user-defined macro instruction to be defined is prepared in the main memory, and this microcode string is defined as an area on the main memory of the control memory corresponding to the user-defined macro instruction to be defined. By specifying the area, the transfer means inside the central processing unit almost unconditionally transfers the contents of the specified area in the main memory to the specified area in the control memory.

[Problems to be solved by the invention]

Therefore, if the user erroneously specifies the address of the control storage area, the microcode corresponding to the system-provided macroinstruction that realizes the original function of the information processing device may be destroyed. There was a problem with reliability.

The present invention has been made in view of such circumstances,
The purpose thereof is to prevent the destruction of the microcode or the like corresponding to the system-provided macro instruction already stored in the control memory, and to enable the definition of the user-defined macro instruction.

[Means for solving problems]

In order to achieve the above object, the present invention is, in the first invention, a microprogram control type information processing apparatus having a rewritable control memory, in which a microcode string corresponding to each macroinstruction is stored. The map memory for storing the start address of the control memory and the code of the user-defined macro instruction to be defined are
In response to a defining macroinstruction having as a parameter a main memory address storing information including a microcode string corresponding to the user-defined macroinstruction to be defined as a second parameter, the first parameter First checking means for checking whether or not the code of the user-defined macro instruction shown is a code released as a user-defined macro instruction; and information stored in the address on the main memory indicated by the second parameter. Second check means for checking whether or not the area of the control memory corresponding to the micro start address of the inside is unused; and the second parameter according to the check results of the first and second check means. The microcode string is read from the indicated main memory address, and the control corresponding to the micro start address is read. Sequentially stores into the storage area and a microcode transfer means.

In addition, in the second aspect of the present invention, in addition to the above configuration,
Third checking means for checking whether or not the content stored at the address on the main memory indicated by the second parameter is microcode is provided, and the microcode transferring means is the first, second and third. The microcode is transferred in consideration of the check result of the check means.

[Action]

When the user defines a new user-defined macro instruction in the information processing device, first, in the main memory, a microcode string corresponding to the user-defined macro instruction and in which area of the control memory the microcode string is stored. The micro start address shown is created, the code of the user-defined macro instruction to be defined is set in the first parameter, and the definition macro instruction in which the address of the created area in the main memory is set in the second parameter is executed. . If the micro start address created in the main memory erroneously points to the microcode area corresponding to, for example, the system definition macro instruction in the control memory, that area is already used and is detected by the second checking means. Since the microcode is not transferred by the code transfer means, it is possible to prevent the already registered microcode in the control memory from being destroyed. When the same code as the system-defined macro instruction is erroneously specified as the first parameter, it is detected by the first checking means, and the second parameter is erroneously specified as the address of the area other than the microcode creation area in the main memory. In the case where is specified, the third check means detects that the microcode string does not exist, and the microcode transfer means does not transfer the microcode in either case, so that illegal registration can be prevented.

〔Example〕

 Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing an example of an information processing apparatus to which the present invention is applied. The main memory 1 has a word width of, for example, 32 bits and a capacity of 1 MW, and an instruction code having a fixed length of 32 bits, for example. Central processing unit 2 and 1 word is for example
Writable and readable control memory 3 with a width of 32 bits and a capacity of, for example, 64 KW and one word with a width of 16 bits and a capacity of, for example, 256 W
And a map memory (mapping memory) 6 capable of writing and reading, and an input / output device 8. The central processing unit 2 and the main memory 1 are connected by an address line 4-1, a control line 4-2 and a data line 4-3, and the central processing unit 2 and the control memory 3 are connected.
Are connected by an address line 5-1, a control line 5-2 and a data line 5-3, and the central processing unit 2 and the map memory 6 are connected by an address line.
7-1, control line 7-2 and data line 7-3 are connected.

FIG. 3 is a more detailed block diagram of FIG. 2, and the input / output device 8 in FIG. 2 is omitted. In FIG. 3, the main memory 1, the control memory 3, and the map memory 6 are the same as those shown in FIG. 2, and the other parts are the main elements included in the central processing unit 2 of FIG. Show. That is, 20 is an instruction register, 21 and 23 are selectors, 22 is a control storage address register, 24 is a control storage data register, and 25 is an operation unit such as a decoder or an ALU that is instructed by microcode. Logic circuit network to execute, 2 decoder, 27 instruction counter, 28 memory address register,
29 is a memory data register. The microinstruction read from the address of the main memory 1 designated by the memory address register 28 determined according to the content of the instruction counter 27 is stored in the instruction register 20 via the memory data register 29, and in the case of this embodiment, the higher order thereof. 8 bits are used as an address of the map memory 6, and the map memory 6 is accessed. The map memory 6 stores a micro head address indicating which address in the control memory 3 the micro code string corresponding to each macro instruction is headed, and the micro head address is stored in the control memory address register 22. And the control memory 3 is accessed. The microcode read from the control memory 3 is applied to the logic network 25 via the control memory data register 24. The logic network 25 sends various control signals to the outside in order to execute an operation according to the applied microcode. Also, the contents of the control memory address register 22 are updated and the next microcode is read. When the operation corresponding to one macro instruction is completed, the content of the instruction counter 27 is updated, the next macro instruction is read from the main memory 1, and the same operation as described above is repeated. Further, the logic circuit network 25 also performs operations such as updating the contents of the map memory 6 and the control memory 3.

FIG. 4 is a format example of a macro instruction for defining a user-defined macro instruction and its contents explanatory diagram. As shown in the figure, the definition macro instruction is an 8-bit instruction code 10-1.
, 8-bit first parameter 10-2 and 16-bit second parameter
It consists of parameters 10-3. The instruction code 10-1 is an 8-bit code indicating that the macro instruction is a defining macro instruction, the first parameter 10-2 indicates the code of the user-defined macro instruction to be defined, and the second parameter 10-2. -3 indicates an address on the main memory 1 in which the microcode string to be registered is stored. That is, when a user-defined macro instruction is newly defined as shown in FIG. 4, a plurality of microcodes to be registered at a certain address A3 to An on the main memory 1 are created, and their two words are written. A check pattern of a predetermined pattern indicating that a microcode is created in the main memory area is stored in the previous address A1, and the microcode size (the number of microcodes) and the microcode are stored in the address A2 one word before. And the start address (micro start address) of the control memory 3 for storing the above. The address A1 is set to the second parameter 10-3 in this case. Also,
The address of the map memory 6 is determined based on the first parameter 10-2, and the micro head address is transferred from the main memory 1 to this address. Further, the microcode stored in the addresses A3 to An is written after the microstart address of the control memory 3, and the size of the microcode is stored in the address of the micro start address-1 for later deletion.
Will be transferred.

Further, FIG. 5 shows a format example of a macro instruction for deleting a user-defined macro instruction. As shown in the figure, the delete macro instruction has an 8-bit instruction code 11-1 and an 8-bit first parameter 11-2, and the lower 16 bits are unused. The instruction code 11-1 is set to the instruction code indicating that the macro instruction is a deletion macro instruction, and the first parameter 11-2 is set to the code of the user-defined macro instruction to be deleted.

FIG. 1 is a flow chart of the processing when the definition macro instruction shown in FIG. 4 is executed by the central processing unit 2 under microprogram control, and FIG. 6 is the deletion macro instruction shown in FIG. It is a flow chart of the processing when it is executed by the microprogram control in the device 2, and the operation of the present embodiment will be described below with reference to each drawing.

(Definition of user-defined macro instruction) When the user tries to define a new macro instruction,
As shown in FIG. 4, a microcode string corresponding to a macro instruction to be defined at a certain address A3 to An in the main memory 1 is created, and at the address A2 one word before, the size of the microcode and those microcodes are generated. The start address (micro start address) of the control memory 3 for storing the code is stored, and a check code indicating that the micro code is created in the main storage area is created at the address A1 two words before. Then, from the input / output device 8 etc. of FIG.
The instruction code of the defining macro instruction is shown in the instruction code 10-1 shown in FIG. 4, the code of the macro instruction to be defined in the first parameter 10-2, and the address of the main memory 1 in the second parameter 10-3. Input the definition macro instruction with A set.

This definition macro instruction is the instruction register 20 shown in FIG.
And the upper 8 bit instruction code 10-1 is transferred to
It is added as an address to the map memory 6 via 21,
The map memory 6 is accessed. At the address corresponding to the instruction code 10-1 in the map memory 6, the start address of the microcode string corresponding to the defining macro instruction is stored in advance. Therefore, the start address is taken out and stored in the control storage address register 22. It is stored and the control memory 3 is accessed. As a result, the microcode read from the control memory 3 is applied to the logic network 25 via the control memory data register 24, and thereafter the microcode and a series of microcodes subsequently read from the control memory 3 are shown in FIG. The processing shown is executed by the logic circuit network 25 or the like.

First, the logic circuit network 25 checks whether the code of the user-defined macroinstruction of the first parameter 10-2 stored in the instruction register 20 is one of the codes open to the user (step). S1). For this check, for example, among the instruction codes expressed by a total of 8 bits, at least the upper bits of the code open to the user are “1”.
If it has to be, then it is checked whether those bits are all "1" s. Of course, it can be checked by other methods. When it is detected that the code not released to the user is defined as the code of the user-defined macro instruction, an instruction trap is generated and the user is notified (step S21).

When the instruction code is correct, the logic circuit network 25 selects the first parameter 10-2 read from the instruction register 20 as a selector.
It is given as an address to the map memory 6 via 21 and the contents are read (step S2), and it is checked whether all are "0" (step S3). The map memory 6 stores the micro head address indicating from which address of the control memory 3 the microcode string is stored corresponding to each macroinstruction as described above, and corresponds to the system definition macroinstruction. Some micro head address is already stored in the area and the area corresponding to the registered user-defined macro instruction. Therefore, if all are not "0", an instruction trap is generated as an illegal registration (step S21).

Next, in step S3, the contents of the map memory 6 are all "0".
If it is determined that the
MA the main memory address indicated by the second parameter 10-3 of 20
Then, this address MA is set in the memory address register 28 to read the contents of the address MA of the main memory 1 (step
S4). Then, it is determined whether the content is a predetermined check code (step S5), and if it is not the predetermined check code, an instruction trap is generated (step S21). If it is a predetermined check code, the address MA is incremented by 1 to read the contents of the main memory 1 (step S6), and the contents of the lower 16 bits (micro head address) of the first parameter 10
Write to the address of the map memory 6 corresponding to the value of -2 (step S7).

Next, the logic circuit network 25 sets the micro head address read in step S6 to .mu.a, reads the contents of the address of the control memory 3 in which .mu.a is -1 (step S8), and checks whether the contents are all "0". The determination is made (step S9). If it is not all "0", some significant information has already been set to that address and overwriting it will destroy the significant information. Therefore, the restoration process of step S20 is performed, and step S7 is performed. All the contents of map memory 6 written by
To generate an instruction trap (step S2
1). On the other hand, when it is determined that all are “0” in step S9,
The contents of the upper 16 bits (the size of the microcode) of the contents read in step S6 are written in the address μa of the control memory 3 (the current value is the micro start address -1) (step S10). Then, the size of the microcode is set to μS (step S11), and the process proceeds to step S12.

In step S12, the logic circuit network 25 reads the contents of the address of the control memory 3 in which μa is incremented by 1, and determines whether or not all are "0" (step S13). If it is not all "0", in order to prevent the destruction of the registered information, the process proceeds to step S20, the contents of the map memory 6 written in step S7 is restored to all "0", and the process of step S15 is performed. If so, all the addresses written in the control memory 3 in that process are restored to all "0", and an instruction trap is generated (step S21).

When it is determined in step S13 that all are "0", the logic circuit network 25 reads the contents of the address of the main memory 1 in which MA is incremented by 1 (step S14), and writes the contents to the address μa of the control memory 3 ( Step S15). This step S14, S15
By carrying out the process 1) once, one microcode is transferred from the main memory 1 to the control memory 3.

Next, the logic network 25 determines the size μS of the current microcode as −
If it is not equal to or less than 0, the process returns to step S12 and the above-mentioned processing is repeated to transfer all the microcodes stored in the main memory 1 to the control memory 3.

(Invalidation of Definition of User-Defined Macro Instruction) When the user intends to invalidate a macro instruction that has already been defined, the instruction code of the deletion macro instruction is added to the instruction code 11-1 shown in FIG. A deletion macro instruction in which the code of the macro instruction to be invalidated is set in the parameter 11-2 is input from the input / output device 8 shown in FIG.

This delete macro instruction is the instruction register 20 shown in FIG.
And the upper 8-bit instruction code 11-1 is transferred to
It is added as an address to the map memory 6 via 21,
The map memory 6 is accessed. At the address corresponding to the instruction code 11-1 in the map memory 6, the start address of the microcode sequence corresponding to the delete macro instruction is stored in advance, so that the start address is fetched and stored in the control storage address register 22. It is stored and the control memory 3 is accessed. As a result, the microcode read from the control memory 3 is added to the logic network 25 via the control memory data register 24, and the microcode and a series of microcodes subsequently read from the control memory 3 are shown in FIG. The processing shown is executed by the logic circuit network 25 or the like.

First, the logic circuit network 25 checks whether the code of the user-defined macroinstruction of the first parameter 11-22 stored in the instruction register 20 is one of the codes open to the user (step S30). ), When it is detected that the request is an invalid request for invalidating a code that has not been released to the user, an instruction trap is generated and the user is notified (step S37).

When the instruction code is correct, the logic circuit network 25 selects the first parameter 11-2 read from the instruction register 20 as a selector.
It is given as an address to the map memory 6 via 21 and the content (micro head address μa) is read (step
S31), the contents of the address (microcode size μS) of the control memory 3 minus μa is read (step S3
2). Then, the contents of the address of the control memory 3 in which μa is incremented by 1 are updated to all "0" (step S33), and one microcode is deleted. Next, μS is decremented by 1 (step S34), and if μS is not less than 0, the flow returns to step S33 to delete the next microcode. When μS is detected to be 0 in step S35, all the microcodes corresponding to the user-defined macro instruction requested to be invalidated this time have been deleted, so the first parameter 11- The contents of the address of the map memory 6 corresponding to 2 are changed to all "0" and the processing is terminated (step S3
6).

After the user-defined macro instruction and the information about the microcode string are deleted from the map memory 6 and the control memory 3 as described above, the user-defined macro instruction is transferred to the instruction register 20 and executed for some reason. If you try to do so, the output of the map memory 6 becomes all "0",
For example, the instruction trap is generated by the microcode stored in the address of all "0" s of the control memory 3.

〔The invention's effect〕

As described above, according to the present invention, it is possible to protect the system from the error of defining the same code as the system-defined macro instruction as the user-defined macro instruction by the first checking means, and control by the second checking means. This has an effect of preventing the microcode already registered in the memory from being destroyed.

Further, by providing the third checking means, it is possible to further prevent erroneous registration of illegal contents other than microcode in the control memory, and program runaway resulting from illegal contents being registered as microcode. Etc. can be prevented.

Therefore, the reliability of the system can be improved, and the user can safely perform the definition operation of the user-defined macro instruction.

[Brief description of drawings]

FIG. 1 is a flow chart showing an example of definition processing of a user-defined macro instruction, FIG. 2 is a block diagram of an information processing apparatus to which the present invention is applied, FIG. 3 is a more detailed block diagram of FIG. 2, and FIG. Is a diagram showing a format example of a definition macro instruction, FIG. 5 is a diagram showing a format example of a deletion macro instruction, and FIG. 6 is a flow chart showing an example of invalidation processing of a user-defined macro instruction. In the figure, 1 ... Main memory 2 ... Central processing unit 3 ... Writable and readable control memory 4-1,5-1,7-1 ... Address line 4-2,5-2,7-2 ... … Control line 4-3,5-3,7-3 …… Data line 6 …… Map memory 8 …… Input / output device

Claims (2)

[Claims] 1. In a microprogram control type information processing device having a rewritable control memory, a map memory for storing a start address of the control memory for storing a microcode string corresponding to each macro instruction will be defined. The user defined macro instruction code
In response to a defining macroinstruction having as a parameter a main memory address storing information including a microcode string corresponding to the user-defined macroinstruction to be defined as a second parameter, the first parameter First checking means for checking whether or not the code of the user-defined macro instruction shown is a code released as a user-defined macro instruction; and information stored in the address on the main memory indicated by the second parameter. Second check means for checking whether or not the area of the control memory corresponding to the micro start address of the inside is unused; and the second parameter according to the check results of the first and second check means. The microcode string is read from the indicated main memory address, and the control corresponding to the micro start address is read. Definition method of the user-defined macro instruction which is characterized by comprising a micro-code transfer means for sequentially storing the storage area. 2. A map memory for storing a start address of the control memory in which a microcode string corresponding to each macro instruction is stored in an information processing device of a microprogram control system having a rewritable control memory. The user defined macro instruction code
In response to a defining macroinstruction having as a parameter a main memory address storing information including a microcode string corresponding to the user-defined macroinstruction to be defined as a second parameter, the first parameter First checking means for checking whether or not the code of the user-defined macro instruction shown is a code released as a user-defined macro instruction; and information stored in the address on the main memory indicated by the second parameter. Second check means for checking whether the area of the control memory corresponding to the micro start address in the inside is unused, and the contents stored in the address on the main memory indicated by the second parameter are microcodes. Third check means for checking whether or not there is a check result of the first, second and third check means Accordingly, the microcode transfer means for reading the microcode string from the address on the main memory indicated by the second parameter and sequentially storing the microcode string in the area of the control memory corresponding to the micro head address is provided. The definition method of the user-defined macro instruction.