JPH0693235B2 - Microcomputer equipment - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a micro computer system for controlling a computer peripheral device that requires high-speed data transfer, and more specifically, to data (DMA) Direct Memory Acces
s) Controlled transfer equipment.

[Prior Art and Its Problems] A method of transferring memory data by DMA control is well known. The following three methods are known as methods of transferring data by DMA control in a microcomputer.

(1) Cycle steal transfer This is a method in which data transfer by the CPU and data transfer by the DMA control are alternately performed every one to several memory cycles. This method has the advantage that it has good immediate responsiveness to both data transfer by the CPU and data transfer by DMA control, but on the other hand, it has the processing time width required for data transfer by the CPU and the data transfer by DMA control. Even if the required processing time width is significantly different, the buses are used alternately, so the transfer with the larger amount of data (for example, DMA transfer) cannot be completed quickly. There is. Further, in this cycle steal transfer method, the connection between the CPU and the bus must be frequently disconnected, which causes a large loss.

(2) Burst transfer This is a method of transferring data collectively in a certain amount when DMA control is requested. This method uses D for continuous use of the bus for fairly long DMA transfers.
Although it has the advantage that MA transfer is efficient, it has a drawback that it is not suitable for a system that requires immediate response because data transfer using a CPU is interrupted for a considerably long time.

(3) Transfer by dual bus method This is a method in which the CPU bus and the DMA bus are completely separated to provide two buses, and data is transferred on each bus. This method has the advantage that the immediate response is good in both data transfer and DMA transfer using the CPU, but has the drawback that the device (hardware) becomes complicated and expensive. Further, when the CPU requires DMA system data, a bus switch for connecting and disconnecting two buses is required, which further complicates the device.

Therefore, it is an object of the present invention to provide a device capable of transferring a large amount of data by DMA control within a short time without substantially impairing the immediate response of the CPU.

[Means for Solving Problems] The present invention for achieving the above-mentioned object will be described with reference to the drawings illustrating an embodiment.
DMA transfer request signal generating means for generating a request signal (DRQ), interrupt signal generating means for generating an interrupt signal (INT), an interface (11) connected to an input / output device (7), and the interface 11 Bus connected to
15, a memory 13 connected to the bus 15, and the bus 15
CPU12 connected to the CPU15, the bus 15 and the DMA control circuit 14 connected to the CPU12, the CPU12, the DMA
The control circuit 14 accepts a bus release request signal (HRQ) indicating that the bus 15 is requested to use the bus 15 for data transfer, and the CPU 12 connects the CPU 1 to the bus 1
The second terminal 2 that outputs a bus release notification signal (HACK) indicating that the CPU 12 is released, and this CPU 12 is not operating (halt)
A third terminal 3 that outputs a halt signal (HALT) indicating that the state is in a state, and a fourth terminal 8 that receives the interrupt signal (INT) from the interrupt signal generating means.
The DMA control circuit 14 gives the first terminal 7 for receiving the DMA request signal connected to the DMA request signal generating means and the bus release request signal (HRQ) to the CPU 12. A second terminal 4 connected to the first terminal 1 of the CPU 12 and a third terminal 4 connected to the second terminal 2 of the CPU 12 for receiving the bus release notification signal (HACK). A terminal 5, a fourth terminal 6 for inputting a halt signal, which is connected to the third terminal 3 of the CPU 12 for receiving the halt signal (HALT), and the first terminal of the DMA control circuit 14. 7, the second terminal 4 and the fourth terminal 6 are connected, the halt signal (HALT) indicates a non-halt state, and the DMA request signal (DRQ) requests DMA transfer. Data is transferred in cycle steal mode in response to The data opening request signal sent to the second terminal 4 of the DMA control circuit 14, the DMA request signal together with the halt signal indicates that the halt status (DRQ) is DM to
A bus release request signal forming circuit for sending the bus release request signal to the second terminal 4 of the DMA control circuit 14 so as to continuously transfer data by DMA in response to requesting A transfer. 20 and the interrupt signal is input to the fourth terminal 8 of the CPU 12 while the signal is input to the first terminal 1 of the CPU 12 so as to perform data transfer by the DMA. In this case, the DMA control circuit 14 is configured to immediately return from the data transfer by the DMA to the data transfer by the cycle steal mode.

[Operation] In the above invention, the DMA control circuit can set both the cycle steal mode and the continuous DMA transfer mode. The continuous DMA transfer mode is not set unconditionally when a data transfer is requested, but is set only when the CPU is in a non-operation state (stop state or standby state). Therefore, the immediate responsiveness of the CPU is not degraded.

[Embodiment] Next, a microcomputer according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

The one-chip microcomputer 10 includes an I / O port 11 as an input and / or output interface, a CPU (central processing unit) 12 including a register unit, a calculation unit, and a control unit, and an R
It is composed of a memory 13 including AM and ROM, a DMA control circuit 14, and a bus 15 interconnecting these. The bus 15 includes a data bus, an address bus, and a control bus. An I / O device including a magnetic tape device, a display, a keyboard, etc., that is, an input / output device 17 is connected to the I / O port 11 by an I / O bus 16. In this embodiment, the input / output device 17 has an interrupt signal generating means for the CPU 12 and a DMA transfer request signal generating means for the DMA control circuit 14.

The CPU 12 can execute a predetermined calculation according to a program written in advance in a ROM provided in the memory 13. The first terminal 1 provided in the CPU 12 receives an operation stop request signal (hereinafter referred to as a hold request signal HRQ) required in the cycle steal mode. This hold request signal HR
Q is a signal requesting that the CPU 12 be disconnected from the bus 15 for DMA transfer. The second terminal 2 of the CPU 12 responds to the hold request signal by stopping the operation of the CPU 12, that is, disconnecting the CPU 12 from the bus 15 and opening the bus 15 for DMA transfer. Less than,
Hold / acknowledge signal HACK). The third terminal 3 of the CPU 12 is a terminal for outputting a stop signal HALT, that is, a standby (standby) signal for indicating that the CPU 12 is not executing the arithmetic processing. The CPU has a terminal 8 for receiving an interrupt request signal INT, and this interrupt signal terminal 8 is connected to an input / output device 17 including an interrupt signal generating means. The CPU12 is Z80C from zilog.
It is configured substantially the same as the PU. Also, CPU12 and D
The MA control circuit 14 of course has a built-in tri-state buffer connected to the bus 15, which can be in a high-level output state, a low-level output state, and a high-impedance state. It is released from the bus at.

The DMA control circuit 14 sets a mode in which the RAM data of the memory 13 is transferred to the input / output device 17 without using the CPU 12. The DMA control circuit 14 includes a memory 13 and an input / output device 17
The terminal 7 has a terminal 7 for receiving a DMA request signal (DRQ) requesting that data transfer between them be performed by DMA control.
It is connected to an input / output device 17 having a built-in RQ signal generating means. Further, the DMA control circuit 14 has a terminal 4 for outputting the above-mentioned hold request signal HRQ for requesting a DMA transfer, which is connected to the first terminal 1 of the CPU 12. The terminal 5 of the DMA control circuit 14 is a terminal for receiving the hold acknowledge signal HACK described above,
Is connected to the second terminal 2. The terminal 6 is a terminal that receives the above-described stop signal HALT, and is connected to the third terminal 3 of the CPU 12.

As shown in principle in FIG. 3, the DMA control circuit 14 includes a hold request signal (HRQ) forming circuit 20 and a circuit 22 for controlling read / write of the memory 13. Hold request signal (HRQ) forming circuit 20 has DRQ input terminal 7
It comprises an intermittent control signal (cycle steal mode control signal) forming circuit 23 and an OR gate 24 connected to the. One input terminal of the OR gate 24 is connected to the intermittent control signal forming circuit 23, the other input terminal is connected to the HALT input terminal 6, and the output terminal is connected to the HRQ output terminal 4. The intermittent control signal forming circuit 23 generates an intermittent signal (cycle steal mode control signal) while the DRQ signal requests DMA transfer. When the hold signal of the HALT input terminal 6 indicates the non-hold state (low level output), the intermittent signal is output from the OR gate 24, and the hold signal indicates the hold state (high level). A high level output (a signal requesting bus release for DMA transfer) is continuously output from the OR gate.

The R / W control circuit 22 is connected to the HACK input terminal 5 and the HALT input terminal 6, and executes the DMA control in response to the HACK signal indicating that the CPU 12 is released from the bus 15.

The CPU 12 and the DMA control circuit 14 have various terminals (not shown) other than the above-mentioned terminals, but these are well known and are not directly related to the method of the present invention. The description of these is omitted.

[Operation] Next, the data transfer operation in the microcomputer 10 will be described with reference to FIG. 2 schematically showing the states of the respective parts in FIG. Now, as shown in FIG. 2A, at time t1, the data transfer request signal DRQ of the DRQ input terminal 7 becomes a high level (logic 1) for requesting data transfer, and the third terminal 3 of the CPU 12 is stopped. When the signal HALT is at a low level (logic 0) indicating that the CPU 12 is operating, the DMA control circuit 14 responds to this and starts control for executing data transfer in the cycle steal mode. That is, the DMA control circuit 14 responds to the high level data transfer request signal DRQ shown in FIG. 2 (A) and outputs the high level (logic 1) hold request signal HRQ from the fourth terminal 4 shown in FIG. Output as shown in B).
High-level hold request signal HRQ is sent to CPU12
This is a signal requesting release of 15. CPU12 is 1 from time t1
Hold at the end of the machine cycle
The request signal HRQ is checked, and if it is high level, the bus 15 is released (disconnected), and the disconnection is notified to the DMA control circuit 14 by the high level hold acknowledge signal HACK. For convenience of illustration, FIG. 2 shows the hold acknowledge signal HACK by ignoring the machine cycle. The DMA control circuit 14 responds to the high level of the hold acknowledge signal HACK by the memory 13 and the input / output device 17
Starts control of DMA transfer of data between and. Since the data transfer is in cycle steal mode, t1 to t2
When the period (1 to several memory cycles) elapses, the hold request signal HRQ becomes low level (logical 0) at time t2, the CPU 12 is connected to the bus 15, and the data of the memory 13 under the control of the CPU 12 is controlled. Transfer is possible. This CP
Of course, when transferring data by U12, data transfer by DMA control is interrupted. The data transfer by the CPU 12 does not continue for a long time, and after a period of t2 to t3 (1 to several memory cycles) elapses, the transfer is switched to the DMA transfer again. As shown in Fig. 2 (F), DM is performed in the cycle steal mode during the period from t1 to t4.
The A transfer period and the CPU transfer period are arranged alternately.

As shown in FIG. 2 (D), when the stop signal HALT output from the CPU 12 becomes a high level (logic 1) state indicating stop at the time t4, the DMA control circuit 14 responds to this by performing the cycle steal mode control. Stop and shift to DMA control. That is,
In response to the data transfer request signal DRQ of FIG. 2 (A) being high level and the stop signal HALT of FIG. 2 (D) being high level, the DMA control circuit 14 causes the HRQ output terminal 4 to operate. Continuously outputs the high-level hold request signal HRQ from, and continuously disconnects the CPU 12 from the bus 15. This interrupts the cycle steal mode and allows continuous DMA
A transfer mode is obtained, and data transfer from the memory 13 to the input / output device 17 or vice versa is continuously performed. Therefore, a large amount of data can be transferred within a short time.

When a new processing request is generated from the outside and the interrupt request signal INT is generated at time t5 as shown in FIG. 2 (E), the CPU 12
In response to this, the low level stop signal HALT is generated as shown in FIG. 2 (D), and the DMA control circuit 12 ends the continuous DMA transfer in response to the low level stop signal HALT, and the cycle steal Switch to mode control. This allows the CPU12
Is connected to bus 15 according to cycle steal mode,
Perform desired calculations and controls.

As shown in FIG. 2A, during the period when the data transfer request signal DRQ is at the low level after time t6, it is not necessary to transfer the data from the memory 13 to the input / output device 17 or vice versa in the DMA control.
Bus 15 remains connected to CPU 12.

When the bus 15 is connected to the CPU 12 and the stop signal HALT is at the high level (the CPU 12 is in the stop or standby state), the data transfer request signal DRQ changes to the high level, and in synchronization therewith, t4 to t5 in FIG. Data transfer based on continuous DMA control with the same period (non-cycle steal mode transfer)
Will start.

This embodiment has the following advantages.

(1) Rather than always performing DMA transfer of data in cycle steal mode, the continuous DMA transfer state occurs when the stop signal HALT (standby signal) of the CPU 12 indicates the stop or standby state, so macroscopically see High-speed data transfer is possible. That is, in the case of the conventional cycle steal mode, intermittently during the period of t4 to t5 in FIG.
Although the CPU transfer period is involved, in this embodiment the CPU
It is a continuous DMA transfer period with no transfer period. Therefore, in the period of t4 to t5, it is possible to obtain a data transfer rate which is about double that of the conventional one.

(2) During the period from t4 to t5 in FIG.
Since the CPU 12 is continuously disconnected from the CPU 15, the CPU 12 is connected to the bus 15 without causing a switching loss.

(3) Since it immediately returns to the cycle steal mode in response to the interrupt request signal INT, the DMA control period t4 to t
Despite the provision of 5, the immediate responsiveness of the CPU 12 does not deteriorate.

(4) Compared with conventional burst transfer, DMA transfer, CPU
It is excellent in immediate responsiveness in any of the transfers.

(5) Compared with the conventional dual bus mode system, it has a single bus structure and is therefore superior in terms of downsizing and cost reduction.

[Modification] The present invention is not limited to the above-described embodiments, and the following modifications are possible, for example.

(1) The microcomputer 10 shown in FIG.
I / O port 11, CPU 12, memory 13, DMA control circuit 14, bus 1
Although the LSI includes 5, it may be a combination of these individual components. In this case, the Z12 CPU manufactured by zilog mentioned above can be used as the CPU 12.

(2) The memory 13 may be a combination of ROM and RAM, or may be only RAM.

(3) The interrupt signal (INT) may be generated from an external device other than the input / output device.

(4) From the external device to the DRQ input terminal 7 of the DMA control circuit 14
A DMA start signal and a DMA end signal are given, a flip-flop is built in the DMA control circuit 14, and this flip-flop
A signal indicating from the DMA start to the DMA end may be formed.

[Effects of the Invention] As is clear from the above, the present invention has the following effects.

(B) Data is not always DMA-transferred in the cycle steal mode, but it is continuously DMA-transferred when the CPU is in a non-operation state (halt state), which enables high-speed data transfer.

(B) When an interrupt signal (INT) is generated, it immediately returns to the cycle steal mode, so the immediate response of the CPU does not deteriorate despite the continuous data transfer period in the DMA mode.

(C) Even during the data transfer period by the CPU in the cycle steal mode, the data transfer state by the DMA can be immediately set as soon as the signal (HALT) indicating the non-operation state of the CPU is generated. It has excellent properties. Therefore, it is possible to provide a device having good immediate responsiveness for both the CPU and the DMA.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of the microcomputer according to the embodiment of the present invention, FIG. 2 is a waveform diagram showing the state of each part of FIG. 1 in principle, and FIG. 3 is the principle of the DMA control circuit. It is a block diagram shown in. 1 ... First terminal, 2 ... Second terminal, 3 ... Third terminal, 4 ... HRQ output terminal, 5 ... HACK input terminal, 6 ... H
ALT input terminal, 7 …… DRQ input terminal, 10 …… microcomputer, 11 …… I / O port, 12 …… CPU, 13 …… memory, 14 …… DMA control circuit, 15 …… bus, 16 …… I / O bus,
17 …… I / O device.

Claims (1)

[Claims] 1. A DMA transfer request signal generating means for generating a DMA request signal (DRQ) for requesting a DMA transfer of data, an interrupt signal generating means for generating an interrupt signal (INT), and an input / output device (7). Interface connected to (1
1), a bus (15) connected to the interface (11), a memory (13) connected to the bus (15), a CPU (12) connected to the bus (15), A bus (15) and a DMA control circuit (14) connected to the CPU (12), wherein the CPU (12) uses the bus (15) for the DMA control circuit (14) to transfer data. 1) for accepting a bus release request signal (HRQ) indicating that the right to use) is requested.
(1), a second terminal (2) that outputs a bus release notification signal (HACK) indicating that this CPU (12) is released from the bus (15), and this CPU (12) Action (hal
t) a third terminal (3) for outputting a halt signal (HALT) indicating that it is in a state, and a fourth terminal for receiving the interrupt signal (INT) from the interrupt signal generating means.
The DMA control circuit (14) has a first terminal (7) for receiving a DMA request signal connected to the DMA request signal generating means.
A second terminal (4) connected to the first terminal (1) of the CPU (12) to give the bus open request signal (HRQ) to the CPU (12); The second of the CPU (12) for accepting a notification signal (HACK)
A third terminal (5) connected to the terminal (2) of the CPU and the CPU (12) for receiving the halt signal (HALT).
A fourth terminal (6) for inputting a halt signal connected to the third terminal (3), and the first terminal (7) and the second terminal (7) of the DMA control circuit (14). 4) and the fourth
Connected to the terminal (6) of which indicates that the halt signal (HALT) is in a non-halt state and
The bus release request signal is sent to the second terminal (4) of the DMA control circuit (14) so as to transfer the data in the cycle steal mode in response to the request signal (DRQ) requesting the DMA transfer. To the DMA request signal (D
RQ) sends the bus release request signal to the second terminal (4) of the DMA control circuit (14) so that data is continuously transferred by DMA in response to requesting DMA transfer. And a bus release request signal forming circuit (20) for performing a data input by the DMA to the first terminal (1) of the CPU (12). The DMA control circuit (14) is configured to immediately return from the data transfer by the DMA to the data transfer by the cycle steal mode when the interrupt signal is input to the fourth terminal (8) of the CPU (12). A microcomputer device characterized by being present.