JPH0693244B2 - Information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial Field of Use B Outline of Invention C Conventional Technology D Problems to be Solved by the Invention E Means for Solving Problems F Action G Example G ₁ Description of Image Processing Device (Fig. 2) G ₂ Possible explanations of the memory control circuit (Figs. 3 and 4) G ₃ Description of an example of the memory control circuit according to the present invention (Fig. 1) H Effect of the invention A Industrial field The present invention relates to an information processing device such as a processing device, and more particularly to a technique of using the memory.

B Outline of the Invention The present invention uses a set of a plurality of memories as a memory, writes input data for a unit time into one of the memories, and reads from one of the remaining memories that are not written to process the data. In this device, when the data to be processed may be data of one unit time in a plurality of unit times, the memory idle as the memory is used as the auxiliary memory.

C Prior Art Various video image processing systems have been proposed (see, for example, JP-A-58-215813).

FIG. 6 shows an example of this video image processing system. That is, this is composed of an input / output unit (1), a memory unit (2), and a data processing unit (3) as shown in FIG.

The input / output unit (1), for example, A / D-converts a video signal from the video camera (4) to obtain digital image data, writes the digital image data in the memory unit (2), and processes from the memory unit (2). Read out the image data, and
A-converts and returns to analog video signal, which can be
The video image can be monitored by recording it in (5) or supplying it to the monitor receiver (6).

The data processing unit (3) gives an address to the memory unit (2), reads the stored image data, applies various processing to the image data, and writes the processed data into the memory unit (2) again. To do.

The memory unit (2) has a group of images, that is, a plurality of field memories or frame memories each having a capacity of one field or one frame.

Writing and reading from the input / output unit (1) to the memory unit (2) are performed in units of one field or one frame which is a unit of the image.

On the other hand, the data processing unit (3) reads out necessary data from the image data stored in the memory unit (2), processes it, and writes the processed data in the memory unit (2) again.

In this case, the memories of the memory unit (2) are usually used as a set of two sheets, and when one is in the data writing state, the other can read from the other.

D Problem to be Solved by the Invention By the way, in a processing apparatus in which a set of two memories is provided and processing can be performed continuously as described above, a group of processing targets to be actually processed, for example, a video In terms of signals, in the case where a field or frame signal is fetched and processed once in a plurality of times, one of the two memories is idle.

That is, for example, in the above-described image processing, in the case where one frame is written to a memory for a plurality of frames for processing, after writing one frame of video data to one memory, one frame is written to the other memory thereafter. Until the data is written, only the data from the one memory is read and processed, and the other memory is idle.

E Means for Solving Problems The present invention is intended to improve the utilization efficiency of a memory, and the present invention has a memory section having a set of a plurality of sheets of memory, and a data processing section. Input data for one unit time is sequentially fetched from one of the plurality of memories and processed within a plurality of unit time every time, and a control signal including an address signal and a write control signal is output from the data processing unit. The write control signal from the data processing unit is supplied to the memory unit, and the memory in which the input data is not written or the memory in which the input data is not read by the address from the data processing unit is used. It is used as an auxiliary memory for the above processing by the included control signal.

[Action]

The idle memory is controlled by the data processing unit, and the control signal such as the write control signal from this data processing unit writes the data from this data processing unit to this idle memory, and It is read out and used as a processing aid.

G Embodiment G ₁ Description of Image Processing Device FIG. 2 shows an embodiment in which the device of the present invention is applied to video image processing as in the former case. The video image processing apparatus of this example realizes particularly high speed data processing.

That is, in this example, the data processing unit is mainly a processor system that calculates pixel values (hereinafter referred to as PIP) (30A) and a processor system that manages data flow management such as address management and timing of processing (hereinafter (PVP) (30
B) and divide.

In the conventional data processing section, the processing time that is the sum of the processing times of both is required, whereas if it is divided in this way, the processing time of the larger one of the two will be sufficient (Japanese Patent Laid-Open Publication No. Sho.
58-215813). Therefore, in the case of this example, high-speed processing that enables video data processing to be performed in real time can be performed.

Further, in the figure, (10) is an input / output unit (hereinafter referred to as IOC), (20) is a memory unit (hereinafter referred to as VIM), which is an input image memory (VIMIN) (20A) and an output image memory (VIA).
MOUT) (20B). Reference numeral (40) is a processor (hereinafter referred to as TC) that controls execution and stop of processing.

The IOC (10) A / D-converts the video signal from the video camera or VTR, writes it as an image image in the input image memory (20A), and outputs the processed image from the output image memory (20B) as described above. Read, D / A convert, and output to a monitor.

In this case, the signal that can be input / output to / from the IOC (10) is an NTSC type or R, G, B type video signal, and that type is designated by the TC (40).

Further, one pixel is, for example, 8-bit data.

VIM (20) has multiple frame memories, eg 12 756
× 512 bytes of frame memory,
In the case of this example, the usage of these 12 frame memories is not fixed, and can be freely set to the input image memory (20A) and the output image memory (20B) according to the processing purpose or the processing target image. It is made available for assignment.

In addition, the memories are used as a set of two, and when one is in the write state, the other can be read from, and the processing from the outside of the VIM (20) by the IOC (10) and the PI
The internal processing of VIM (20) by P (30A) and PVP (30B) can be performed in parallel. In this case, multiple frame memories of this VIM (20)
The control mode signal, which is under control of (10) or PVP (30B), is generated from IOC (10), and VIM
(20) is being supplied.

Further, the input / output unit (10) generates a role mode signal PM indicating which of the latest input data is stored in the memory set of two sheets.

The PIP (30A) and PVP (30B) basically have the same architecture, and are composed of independent processors consisting of a control unit, an arithmetic unit, a memory unit, and an input / output port, each of which has a multiprocessor configuration including a plurality of unit processors. , A parallel processing method is mainly used to speed up the processing.

The PIP (30A) has, for example, 60 PIP processors and several sub processors, and processes image data from the VIM (20) or internally generates image data. This PIP (30A)
The clock of is supplied from TC (40).

PVP (30B) has about 30 processors, VIM (20)
Allocation and collection of pixel data from PIP (30A)
Controls the flow of image data inside the VIM (20).

That is, the PVP (30B) generates a control signal including address data to the VIM (20), a write selection signal, an output selection signal and a memory write signal, and outputs these control signals to VI.
In addition to supplying to M (20), I / O control signals of PIP (30A) and other control signals are generated, and these are supplied to PIP (30A).

The input image memory (20
Not only when processing only the data from one frame in (A) and writing the processed data to the output image memory (20B), but using data that spans multiple frames from multiple frame memories. It may also be processed.

The standard number of arithmetic digits in PIP (30A) and PVP (30B) is 16 bits, and the arithmetic processing of image data processing is such that processing of one frame of image data is possible within one frame, that is, real-time processing. Is possible. However, there are some processes that require a processing time of one frame or more.

In this case, the image data processing by PIP (30A) and PVP (30B) is performed in synchronization with the frame. Therefore, PVP (3
0B) is supplied with the processing start timing signal PS (which becomes low level when the processing is started) synchronized with the frame from the IOC (10). On the other hand, from the PVP (30B), a signal OK indicating that one process is completed is supplied to the IOC (10).

Signal PS is real-time processing (1 frame of data is 1/30
Processing in seconds) is obtained at the beginning of each frame, otherwise it is obtained at the beginning of the next frame after the signal OK and at the beginning of the frame specified by the user.

The signal OK is output from the core processor of the PVP (30B), which controls the timing of the processing system, of the PVP (30B) processor when the processing is completed.

That is, in the core processor of this PVP (30B), IOC
It is detected programmatically that the processing start timing signal PS from (10) has become low level. And the signal PS
When this processor starts to go low, this processor starts running and the other processors in the PVP (30B) and the PIP
For (30B), a timing signal TS is output by a program, an address is supplied to VIM (20), image data is read from VIM (20), and processing is performed by PIP (30A).

In the case of this example, the following three modes can be selected as the image data processing.

One frame is fetched once every N frames for processing. Especially, if N = 1, real-time processing is performed.

The next frame at the time when the previous processing is finished is automatically captured and processed.

The next frame at the time when the user gives an instruction with a button or the like is fetched and processed.

G ₂ Description of possible memory control circuits By the way, when controlling a pair of memories,
Control signals such as addresses and write / read control signals must be sent to the memory section (20) so that the control by the input / output unit (10) and the control by the PVP (30B) do not conflict with each other. . It is not easy to do this correctly, but if you do as in Fig. 3,
IOC (10) and PVP that the image memory is a set of 2 sheets
(30B) can both forget and control,
Control becomes very simple.

In the figure, (201) and (202) are a set of two memories. Digital image data A / D converted by the IOC (10) or digital image data processed by the PIP (30A) is supplied to the input end (203), and this input end (20
Image data through 3) is stored in two frame memories (201)
And (202) data input terminals.

Further, (204) is an output terminal, and the memories (201) and (202)
The image data read out is obtained in this, and this is PI
Supplied to P (30A) for processing, or
It is supplied to the IOC (10), D / A converted, and returned to an analog video signal.

(205) and (206) are the memories (201) and (20), respectively.
A selector for selecting the address signal and control signal for 2). Control signals such as address signal and write / read control signal are supplied from the IOC (10) to their respective A-side input terminals, and from the PVP (30B). Control signals such as address signals and write / read control signals are supplied to the respective B-side input terminals.

Further, the dominant mode signal CM from the IOC (10) is supplied as it is to the select terminal of the selector (205), and its polarity is inverted by the inverter (207) and supplied to the select terminal of the selector (06).

In this case, the selectors (205) and (206) derive the signal supplied to the A side input terminal as an output when the select signal supplied to the select terminal is "0", and output the signal as B when it is "1". The signal supplied to the side input terminal is derived.

Therefore, when the control mode signal CM is "0", the control signal such as the address signal from the IOC (10) and the write / read control signal is sent from the selector (205) to the memory (20).
1), the memory (201) is controlled by the IOC (10), the input image memory is in a mode for writing input data, and the output image memory is in a mode for reading processed data.

On the other hand, the select signal of the selector (206) is the inverter (207).
Therefore, since it is “1”, PVP is output from this selector (206).
Control signals such as address signals and write / read control signals from (30B) are supplied to the memory (202), and this memory (202) is under the control of the PVP (30B), and data is read from the input image memory. PIP (30A)
And a mode for writing the processed data to the output image memory.

When the dominant mode signal CM is "1", the selectors (205) and (206) make opposite selections, so that the memory (201) is PVP.
The memory (202) will be dominated by (30B) and the IOC (10) will be dominated by memory (202).

However, the memory control method of FIG. 3 cannot eliminate the inconvenience that one of the memories is idle in the mode in which the image data of one frame is captured once every N frames and processed.

That is, for example, when the memories (201) and (202) are the memories of the input image memory (20A), the control mode is as shown in FIG.

In the figure, I is the IOC (10) control, P, is PVP (30
B) indicates that it is the control, and indicates the memory that contains the latest input data. That is, one frame of input data to be processed is written in the I memory,
This will be read out and used for processing.
P without a circle is a memory containing already processed data, which means that it is idle.

G ₃ Description of an example of a memory control circuit according to the present invention FIG. 1 is an example of a memory control circuit according to the present invention, which is an example when applied to the image processing apparatus. It is supposed to control the input image memory (20A) consisting of memory.

That is, (301) and (302) are a set of frame memories, and the image data from the input section (10I) of the IOC (10) and its memory address signal, the processed image data from the PIP (30A), and The memory address signal from the PVP (30B) is selected by the selectors (303) and (304) and supplied to these memories (301) and (302).
In this example, the dominant mode signal CM ₁ of the memory (301) and the dominant mode signal CM of the memory (302) are input from the input section (10I).
₂ is obtained, and the role mode signal PM for the memories (301) (302) is obtained.

Dominant mode signals CM ₁ and CM ₂ are stored in the memory (301), respectively.
And (302) are signals indicating whether the IOC (10) is in control or the PVP (30B) is in control, and the role mode signal PM is a signal indicating in which memory the first input data is stored.
In other words, in the mode diagram shown in FIG. 4, it is the dominant mode signals CM ₁ and CM ₂ that indicate whether each memory is I, P or, and which memory is Shown is the role mode signal.

In this example, the dominant mode signals CM ₁ and CM ₂ are “1” for I, “0” for P, and the role mode signals
In the PM, the memory (301) is set to "1" and the memory (302) is set to "0".

Write / read control signal W from the input section (10I)
EI is obtained.

On the other hand, from the PVP (30B), in addition to the address signal, output selection signal OS, write selection signal WS, write / read control signal
WEP is obtained.

The output selection signal OS is a signal for reading from the memory of P or from the memory of P, and is "0" in the former case and "1" in the latter case.

The write selection signal WS is a signal that determines whether to write to the memory of P or the memory of P, and is “0” in the former case,
In the latter case, it becomes "1".

This is “1” for the write / read control signals WEP and WEI.
When the memory is written, the memory (301)
And (302) are in a write state when the control input terminal WE is "0".

Dominance mode signal CM ₁ is sent to the selector (303)
CM ₂ is supplied to each selector (304).

Therefore, when the memory (301) or (302) is in the dominant mode I of the IOC (10), the dominant mode signal CM ₁ or CM ₂
Is "1", the input data from the input unit (10I) and the address signal are supplied from the selector (303) or (304) to the memory (301) or (302). At this time, if the write / read control signal WEI is “1”, the memory (301)
Is controlled by IOC (10), the signal CM ₁ is “1”, so the output of the NAND gate (305) becomes “0”, and the output of the AND gate (309) also becomes “0”. , The control input terminal WE of the memory (301) becomes "0", and the memory (301) is in the writing state. Meanwhile, memory (302)
There the output of the NAND gate (306) because when a IOC (10) dominates the signal CM ₂ is "1" becomes "0", the output also becomes "0" in this order AND gate (310), the memory The control input terminal WE of (302) becomes "0", the memory (302) becomes writable, and the input data is written in accordance with the address signal.

Next, when the memory (301) or (302) is in the dominant mode P of the PVP (30B), the dominant mode signal CM ₁ or CM ₂ is “0”, so the selector (303) or (304) Is PIP
The data processed in (30A) and the address signal from the PVP (30B) are supplied to the input terminals of these memories (301) and (302).

On the other hand, the role mode signal PM is directly supplied to one input terminal A of the selector (311) and the inverter (312).
The polarity is inverted by and is supplied to the other input terminal B of this selector (311). Then, the output selection signal OS from the PVP (30B) is supplied as the selection signal of the selector (311). The output OE of this selector (311) is the memory (302)
Is supplied to the output enable terminal of the memory (301) through the inverter (313), and the output (OE) of the memory (301) enables the output (OE) of the memory (301). 302) is in the output enable state.

When the role mode signal PM is “1”, the memory (30
1) is, but at this time, the output selection signal OS is "0"
If so, the output of the selector (311) becomes "1", and the memory (301) is in the output enable state. That is,
Is read from the memory (301).

On the other hand, at this time, if the output selection signal OS is "1", the output of the selector (311) becomes "0", and the memory (302) that is P
Becomes the output enable state.

On the contrary, when the role mode signal PM is “0”, the memory (302) is, but if the output selection signal OS is “1” at this time, the output OE of the selector (311) is “0”. , The memory (302) is in the output enable state, and if the output selection signal OS is “0”, the memory (301) in P is similarly in the output enable state.

At this time, write / read control signal from PVP (30B)
If WEP is "0", NAND gates (307) and (30
Both outputs of 8) become "1". On the other hand, since the dominant mode signals CM ₁ and CM ₂ are “0” in PVP (30B) dominant,
The outputs of the NAND gates (305) and (306) are both "1".
become. Therefore, the outputs of the AND gates (309) and (310) are both "1", and the memories (301) and (302) are in the read state. However, as described above, the memory whose output is enabled is selected by the output selection signal OS, and the selector (303) is selected from the enabled memories.
Alternatively, the image data is read according to the address signal from the PVP (30B) through (304) and supplied to the PIP (30A).

In other words, the role mode signal indicates which memory is used, and the output selection signal OS determines which memory to read from, the memory of P or the memory of P.

Here, the mode to read from the memory is the latest data.
This is the read mode for processing with PIP (30A), and P
The memory is read from the memory when the frame data after the previous processing is read and used as described later, or the mode in which the data being processed is written as the auxiliary memory is read as described later.

Next, if the write / read control signal WEP from the PVP (30B) is "1", the output of the NAND gates (307) and (308) to which this signal WEP is supplied to one input terminal is the other input terminal. "0" or "1" depending on the signal supplied to
become.

The outputs of the selector (314) are supplied to the other input ends of the NAND gates (307) and (308) as they are to the NAND gate (307) and to the NAND gate (308) via the inverter (315). Then, the role mode signal PM is directly supplied to one input terminal A of the selector (314),
A signal obtained by inverting the polarity of the role mode signal PM from the inverter (312) is supplied to the other input terminal B. further,
The write selection signal WS from PVP (30B) is applied to this selector (31
It is supplied to the select terminal of 4).

When the write selection signal WS is “0”, the selector (31
From 4), the role mode signal PM of the input terminal A can be obtained,
When the role mode signal PM is “1” and the memory (301) is “0”, the output of the NAND gate (307) becomes “0”, and thus the output of the AND gate (309) becomes “0”. The memory (301) is in a writing state. When the role mode signal PM is "0" and the memory (302) is "0", the output of the NAND gate (308) becomes "0" and the output of the AND gate (310) becomes "0". 302) becomes the writing state.

That is, when the write selection signal WS is "0", writing can be performed to the memory, and the image data from the PIP (30A) is written to the memory by the address signal from the PVP (30B).

This is a mode used when it is desired to use the one obtained by processing the frame data to be processed in the processing of the next frame data, and the memory in the continuous mode in the mode diagram of FIG. Make sure to write the processed data at the end of.

On the other hand, when the write selection signal WS is “1”, the selector (31
Since the polarity reversal signal of the role mode signal PM is obtained from 4), the output of the NAND gate (308) is "0" when the signal PM of the memory (301) is "1", and therefore the AND gate (310). ) Becomes “0” and the memory is P (30
2) is in the write state. Similarly, when the signal PM for the memory (302) is "0", the outputs of the NAND gate (307) and the AND gate (309) are "0", and the memory (301) which is P is in the write state.

That is, when the write selection signal WS is "1", writing can be performed in the memory P, and the image data from PIP (30A) is written in the memory by the address signal from PVP (30B).

The memory in P mode is the idle memory,
The image data processed by PIP (30A) is temporarily written in this memory, and it is also used as an auxiliary memory such that it is read out as described above, processed, written, and read out. .

Although the memory control of the input image memory (20A) has been described above, the dominant mode of the output image memory (20B) is considered as shown in FIG. 5, one of which is the IOC (1
When 0) control, the other becomes PVP (30B) control, and there is no mode.

In this output image memory (20B), I is the mode in which the final output data is read by being controlled by the IOC (10), and P
Is a mode in which data after PIP (30A) processing can be appropriately written as an auxiliary memory or a mode in which final data is written in the memory.

Therefore, the output image memory (20B) can be controlled in the same manner as the input image memory (20B) except for the mode other than the mode, and the idle memory can be appropriately used as the auxiliary memory.

As described above, in the example of FIG. 1, memory control is performed according to various mode concepts, so IOC (10) and PVP (30
B) and PIP (30A) can output control signals simply and clearly without being aware of each other.

Although the case where the information signal is the image data has been described above, the present invention is of course applicable to the case where the information signal other than the image data is processed every unit time.

H Effect of the Invention According to the present invention, in a processing device that performs continuous processing using a memory that uses two or more sheets as a set, the idle memory is used as an auxiliary memory, so that the memory usage efficiency is improved. As it goes up, more complicated processing can be performed without increasing the memory.

[Brief description of drawings]

1 is a block diagram of an example of a main part of the present invention, FIG. 2 is a block diagram of an example of an image processing apparatus to which the present invention is applied, FIG. 3 is a block diagram of an example of a memory control circuit, and FIG. 5 and 6 are diagrams for explaining the memory control state, and FIG. 6 is a block diagram of an example of the image processing apparatus. (10) is an input / output system, (20) is a memory section, (301) and (3
02) is a set of frame memories, and (30A) and (30B) are processors constituting a data processing unit.

Claims (1)

[Claims] 1. A memory section having a set of a plurality of memories,
A data processing unit, which sequentially fetches input data for one unit time every one unit time into one of the plurality of memories and processes the data within a plurality of unit time. A control signal including an address signal and a write control signal is supplied to the memory section, and the memory in which the input data is not written or the input data is not read by an address from the data processing section is the memory. An information processing apparatus adapted to be used as an auxiliary memory for the above processing by a control signal including the write control signal from the data processing unit.