JPH0693310B2 - Data playback system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a frame structure in which recording data of one sector has a plurality of data frames separated by a frame synchronization signal with a gap of a predetermined interval from a preformatted area. The present invention relates to a data reproducing method capable of surely reproducing the data at the head of a data frame in a recording device having a data recording format formed in the above.

[Prior Art] Although an apparatus using a magnetic recording medium such as a magnetic tape or a magnetic disk is widely used as an auxiliary storage device of a computer system, in recent years, the recording density is remarkably higher than those of these magnetic recording media. There is a proposal to use an optical recording medium that can be used (for example, an optical disk) as an auxiliary recording device.

For example, in the case of an optical disc, the diameter of 1
2 μm pits (small holes) on the surface recording track
to record data by forming in μm order period (interval), the storage capacity is 10 ¹¹ per sheet in a diameter of about 30cm
It is about 10 ¹² bits.

In general, the access speed of the auxiliary storage device is much slower than that of the main storage device, so that data is recorded in a continuous area in blocks of a certain amount.

At that time, a predetermined block of data is configured in a sector so that reading and writing of data can be surely performed in a short time.
An address (sector address) is assigned to each sector for identification.

6 (a) and 6 (b) show an example of a data recording format in a track of an optical disc.

In the same figure (a), in the track TR, a plurality of sectors SC, each consisting of a pre-formatted area PF, a data area DF, and a gap GP1 separating the pre-formatted area PF and the data area DF, are separated from each other by a gap GP2. Is set automatically.

The pre-format area PF is divided into tracks T in advance by separating the data area DF and the gap GP2 by the number of bits.
Formed in R.

In addition, as shown in FIG.
PF is a sync signal for matching the circuit conditions, that is, a preamble composed of a bit period signal BS for synchronizing the bit clock of the data recording / reproducing circuit with the generation timing of the recording data, and a self-amble for detecting this preformat area PF. The sector synchronization signal SS is composed of a bit string (pattern) having a sharp correlation, and the sector address SA for identifying the sector SC.

As the bit synchronization signal BS forming the preamble, a bit clock circuit (described later) for extracting the bit clock and the reproduction data based on the reproduction signal from the optical pickup unit is used.
A signal that can lock a PLL (Phase Locked Loop) circuit appropriately is used. For example, a signal that changes the state of the read signal at the minimum inversion cycle (that is, the recording state on the optical disc is the repetition of the minimum pit length "010101 ...
...)).

Further, the data area DF includes a plurality of data having a frame structure with a frame synchronization signal FS and a preamble (bit synchronization signal B added at the beginning of these data.
S). The number of bits of the preamble in the data area DF is smaller than that of the preamble in the preformat area PF.
Has a sharp pattern of autocorrelation similar to the sector synchronization signal SS.

Preamble BS of the pre-formatted area PF described above, sector synchronization signal SS, sector address SA, gaps GP1, GP
2, and the preamble BS and the frame synchronization signal FS of the data area DF are recorded on the optical disc in an unmodulated state,
The frame data of the data area DF is recorded in a state of being subjected to a predetermined modulation. Further, as shown in FIG. 8, such a pre-formatted area PF is formed when the optical disc 1 is manufactured, and a portion corresponding to the data area DF is a guide groove for guiding the optical pickup. It is formed in a certain data groove DG.

In this way, the recording track TR having an extremely fine structure is formed on the optical disc, and the preformat area PF including the data pits having a further fine structure is formed on the recording track TR. Also, these recording tracks TR
The pits forming the pre-formatted area PF are directly formed on the base material of the optical disc by transferring the master block formed by reversing the concavo-convex state.

Now, FIG. 8 shows a conventional example of a data reproducing circuit for reproducing data recorded on an optical disc in such a recording format.

In the figure, the optical pickup 2 is subjected to tracking control and focusing control so that the optical pickup 2 is traced on the recording track of the optical disc 1 rotating in the direction of the arrow, and reproduction data output from the optical pickup 2 is output. IND is added to the address discrimination circuit 4 and the bit synchronization circuit 5. The optical pickup driving section 3 also controls the positioning of the optical pickup 2, and its command is given from the address discrimination circuit 4.

The address discrimination circuit 4 detects the sector synchronization signal SS in synchronization with the preamble of the preformat area PF based on the input reproduction data IND, and detects the sector address SA based on the detection timing. Then, when the detected sector address SA matches the target sector address OS given from the control unit (not shown), the sector detection signal SDD is output, and when it does not match, the optical pickup drive corresponding to the difference is output. A movement command is output to the unit 3 to move the optical pickup 2 to the target sector. The sector detection signal SDD output from the address discrimination circuit 4 includes a frame synchronization detection circuit 6 for detecting the frame synchronization signal FS of the data area DF, a demodulation circuit 7 for demodulating recorded data into original data, and , An error correction circuit 8 for detecting and correcting an error contained in the demodulated data.

The bit synchronization circuit 5 outputs a PLL clock signal PCL that is phase-synchronized with the state change (significant data) of the reproduction data IND.
It comprises a PLL circuit and a data sample circuit for sampling the reproduction data IND and separating the read data RD in synchronization with the PLL clock signal PCL. The PLL clock signal PCL is applied to the frame synchronization detection circuit 6, the demodulation circuit 7 and the error correction circuit 8, respectively, and the read data RD is applied to the frame synchronization detection circuit 6 and the demodulation circuit 7, respectively. Here, the frequency of the PLL clock signal PCL is set to several times (usually a multiple of 2) of the bit synchronization signal BS so that the read data RD can be appropriately separated from the reproduced data IND.

The frame synchronization detection circuit 6 starts counting the PLL clock signal PCL and pattern matching between the read data RD having a predetermined number of bits and the frame synchronization signal FS in synchronization with the input timing of the sector detection signal SDD, and the count value is a predetermined value. Then, the prediction function is generated to detect the frame synchronization signal FS, and the frame detection signal FDD is generated in correspondence with the detection timing of the frame synchronization signal FS. This frame detection signal FDD
Are added to the demodulation circuit 7.

The demodulation circuit 7 receives the sector detection signal from the address discrimination circuit 4.
The operation is started based on the timing to which SDD is added, and the read data RD input based on the reception timing of the frame detection signal FDD is demodulated to the original data DAT,
This data DAT is output to the error correction circuit 8.

The error correction circuit 8 starts its operation at the timing when the sector detection signal SDD is added from the address discrimination circuit 4, and performs a predetermined error detection and correction process based on one sector of the data DAT added from the demodulation circuit 7. And data DA
When an error in T is detected, it is corrected and the corrected data CDT is output to the next stage circuit.

Therefore, first, when the sector synchronization signal SS in the pre-formatted area PF is detected and the sector address SA is discriminated, and when it coincides with the target sector address OS,
The sector detection signal SDD is output and the frame synchronization detection circuit 6, the demodulation circuit 7 and the error correction circuit 8 start operating.

When the frame synchronization detection circuit 6 detects the frame synchronization signal FS in the data area DF and outputs the frame detection signal FDD, the demodulation circuit 7 demodulates the read data RD and outputs the data DAT to the error correction circuit 8. When the demodulation of the read data DAT for one sector is completed, the error correction circuit 8 outputs the error corrected data CDT to the next stage device.

In this way, the recording data for one sector is read and output.

However, in such a conventional device, the following inconveniences have occurred.

That is, the bit synchronization circuit 5 detects the rising edge and the falling edge of the reproduced data IND every time a change (significant data) appears, and performs phase synchronization so that the phase of the PLL clock signal PCL coincides with the detection timing. Also, since the portion of the gap GP2 appears in the reproduction data IND immediately after the sector detection signal SDD is output until the bit synchronization signal BS is input, the state does not change. In this state, the PLL circuit self-runs and the PLL clock signal PCL is output asynchronously with the reproduction data IND.

On the other hand, the frame synchronization detection circuit 6 generates a prediction function based on the count value of the PLL clock signal PCL, but when it detects the first frame synchronization signal FS of the data area DF, it is output from the address determination circuit 4. Sector detection signal SDD is PLL
Since it becomes the starting point for counting the clock signal PCL, the gap GP2
PLL clock signal PCL when detecting
Then, the prediction function is generated in synchronization with the timing at which the count value corresponding to the total of the PLL clock signals PCL in the state where the bit synchronization signal BS is detected and phase-locked with this is detected. In addition, when the first frame synchronization signal FS is detected, the prediction function is generated in synchronization with the count value of the PLL clock signal PCL that becomes the value corresponding to the length of the frame data thereafter. When the signal FS is detected, the counting of the PLL clock signal PCL for detecting the subsequent frame synchronization signal FS is started with the detection timing as a starting point.

However, when the gap GP2 of the optical disc 1 is scratched or the like, noise is generated in the reproduction data IND, and the bit synchronization circuit 5 acts so as to be phase-synchronized with this noise.
When the PLL clock signal PCL advances and noise frequently occurs, the phase may advance by one cycle or more.

Further, the input signal at the optical pickup 2 includes a DC component because it corresponds to the reflected light level from the optical disc 1, but the output signal (reproduction data IND) needs to be in a state in which this DC component is removed. Therefore, the input signal is passed through an AC coupling circuit to remove such DC component, and in that state, it is compared with a predetermined threshold level to reproduce the binary data reproduction data IN.
Waveform is shaped to D.

Now, when the optical pickup 2 moves to a state where the light receiving level fluctuates by detecting the bit synchronization signal BS of the data area DF from the state where the light receiving level is constant by detecting the gap GP2, the optical system of the optical pickup 2 and Due to the time constant of the signal processing system such as the AC coupling circuit, there is a certain amount of time from immediately after the detection of the bit synchronization signal BS until the center level of the input signal of the comparator that shapes the waveform of the reproduction data IND reaches a predetermined value ( Hereinafter referred to as pull-in time).

Therefore, during this pull-in time period (hereinafter referred to as the pull-in period), the maximum value of the input signal of the comparator becomes smaller than the threshold level in the first part,
Alternatively, the minimum value of the input signal may become larger than the threshold level and the state of the reproduction data IND may not change. Then, in the subsequent pull-in period, the central level of the input signal of the comparator gradually approaches the predetermined value, so the timing of the rising edge of the reproduction data IND becomes later than the timing other than the pull-in period and the falling edge of the reproduction data IND. Timing becomes earlier than the timing other than the pull-in period, and as a result, the playback data IND
Duty becomes smaller.

In this way, playback data IN
When the disturbance of D occurs and the disturbance of the reproduction data IND affects the operation of the PLL circuit of the bit synchronization circuit, the frequency of the PLL clock signal PCL may fluctuate significantly.

In this way, during the period from the time when the address discrimination circuit 4 detects the target address and outputs the sector detection signal SDD to the first part of the data area DF, that is, the period in which the gap GP2 and the pull-in period are combined, the reproduction data IND Is in an unstable state, it is output from the bit synchronization circuit 5.
The PLL clock signal PCL becomes unstable, and as a result, the timing at which the frame synchronization detection circuit 6 generates a prediction function may be greatly deviated (see FIGS. 9A to 9C), and the first of the data area DF There may be a problem that the frame synchronization signal FS of 1 cannot be detected.

[Object] The present invention has been made in order to solve the above-mentioned inconveniences of the prior art, and provides a data reproducing system capable of preventing the disturbance of the basic clock when the first part of the preformatted area is reproduced. With the goal.

[Structure] According to the present invention, when the target sector is detected, the bit synchronization circuit is self-propelled without applying the reproduction signal from the storage medium to the bit synchronization circuit for a predetermined period from the time of detection, whereby the gap And the adverse effects of the pull-in period of the optical pickup are eliminated.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a data reproducing apparatus according to an embodiment of the present invention. In the figure, the same parts as those in FIG. 8 are designated by the same reference numerals and the description thereof will be omitted.

In the figure, the counter 10 outputs a PLL signal from the bit synchronization circuit 11 when the sector detection signal SDD is output from the address discrimination circuit 4 when the sector address SA detected from the reproduction data IND matches the target sector address OS. Counting of the clock signal PCL is started, and when the count value reaches a predetermined value, a start pulse PST is output to the bit synchronization circuit 11.
The set value of the counter 10 is the reproduction data output from the optical pickup 2 in the first part of the data area DF after the address detection signal SDD is output from the address discrimination circuit 4.
It is a value corresponding to the count value of the PLL clock signal PCL output from the bit synchronization circuit 11 in the free-running state until IND stabilizes.

The bit synchronization circuit 11 is a PLL that is phase-synchronized with the reproduction data IND.
A PLL circuit that outputs a clock signal PCL and a data sample circuit that samples the reproduction data IND and separates the read data RD in synchronization with the PLL clock signal PCL. Also,
The PLL circuit reproduces the reproduction data I from the time when the address detection signal SDD is applied to the time when the start pulse PST is applied.
It runs on its own without phase synchronization with ND.

Therefore, the optical pickup 2 is positioned in the target sector by the optical pickup drive unit 3, the sector address SA of the target sector is detected from the reproduction data IND output from the optical pickup 2, and the sector discriminating circuit 4 outputs the sector detection signal SDD. Then (see FIG. 2 (a)),
While the PLL circuit of the bit synchronization circuit 11 becomes free-running (see (d) in the figure), the counter 10 causes the PLL clock signal PCL
Start counting.

The counter 10 outputs a start pulse PST when the count value of the PLL clock signal PCL reaches a predetermined value (see FIG. 2 (c)). As a result, the PLL circuit of the bit synchronization circuit 11 starts operating, the PLL clock signal PCL is phase-locked with the reproduction data IND, and the state is held (lock state).

Further, when the bit synchronization signal BS appears in the reproduction data IND, the bit synchronization circuit 11 first samples the bit synchronization signal BS with the PLL clock signal PCL in the free-running state and outputs the read data RD. , Start pulse
After the PST is output, the bit synchronizing signal BS is sampled by the PLL clock signal PCL locked to the bit synchronizing signal BS and the read data RD is output.

In this way, the bit synchronization circuit 11 outputs the PLL clock signal PCL in the free-running state and reproduces it when the reproduction data IND output from the optical pickup 2 is unstable in the first part of the data area DF. When the data IND becomes stable, it outputs the PLL clock signal PCL that is in phase with the reproduction data IND.

As a result, the frame sync detection circuit 6 has a gap GP2.
Since the PLL clock signal PCL in a state in which the influence of the pull-in period of the optical pickup 2 is removed is added, a prediction function for detecting the frame synchronization signal FS can be generated at an appropriate timing (see FIG. (See e)), the frame synchronization signal FS appearing in the reproduction data IND can be reliably detected.

FIG. 3 shows an example of the bit synchronization circuit 11.

In the figure, reproduction data IND (see FIG. 4 (a)) added from the optical pickup 2 detects the rising edge and the falling edge of the reproduction data IND and detects an edge detection pulse.
Edge detection circuit 31 for outputting EDP (see FIG. 4 (b))
And PLL clock signal PCL (see FIG. 4 (e); described later)
Is added to the data sampling circuit 32 that holds the level state at the rising timing of and outputs as the read data RD. The edge detection pulse EDP is set to the trigger input end of the reference pulse generator 33 and the comparison pulse generator 34. It is added to the input end.

The reference pulse generator 33 generates a reference pulse TP (see FIG. 4 (c)) having the same waveform as the PLL clock signal PCL in synchronization with the rising timing of the edge detection pulse EDP. Is output to the reference phase input terminal of the phase comparator 35. Further, the PLL clock signal PCL is added to the reset input terminal of the comparison pulse generator 34, and the comparison pulse generator 34 rises at the rising edge of the reference pulse TP and falls at the falling edge of the PLL clock signal PCL. Comparison pulse HP (See Fig. 4 (d))
And the comparison pulse HP is applied to the comparison phase input of the phase comparator 34.

The phase comparator 35 detects the reproduction data IN from the timing of the falling edge of the reference pulse TP and the falling edge of the comparison pulse HP.
The phase error between D and the PLL clock signal PCL is detected. When the reference pulse TP falls first, the up / down signal UD output to the up / down counter 36 is set to the logic level H, When the reference pulse TP later falls, the up / down signal UD is set to the logic level L.

The up-down counter 36 counts up the clock signal MCK applied from the oscillator 37 when the up-down signal UD is at the logic level H, and down-clocks the clock signal MCK when the up-down signal UD is at the logic level L. To count. When counting up, a carry signal is issued every time the count value reaches a preset K.
When outputting CY and counting down, the count value is 0.
Each time, the count value is preset to K and the borrow signal BR is output.

These carry signal CY and borrow signal BR are respectively the increment input terminals of the incrementer decrementer 38.
Added to INC and Declimen input terminal DEC.

The incrementer decrementer 38 forms a clock signal CCK (see FIG. 5 (d)) obtained by dividing the clock signal MCK (see FIG. 5 (a)) applied from the oscillator 37 by half. , When the carry signal CY (see FIG. 5 (b)) is added, the timing of the clock signal CCK is advanced by 1/2 cycle at a predetermined timing from the fall (that is, a pulse is added; in FIG. 5 (d)). When the borrow signal BR (see FIG. 5 (c)) is added, the timing of the clock signal CCK is sent by 1/2 cycle at a predetermined timing from the fall (that is, the pulse is removed; Figure 5 (d)
Part B).

The clock signal CCK is added to the frequency divider 39, divided into 1 / N, and output as the PLL clock signal PCL. In addition,
The frequency of the PLL clock signal PCL output from the frequency divider 39 is a times the bit rate frequency of the data area FD (a is 2
The frequency of the clock signal MCK output from the oscillator 37 is set to 2aN times the bit rate frequency of the data area FD.

In this way, the reproduction data IND and the PLL clock signal PCL
Edge detection circuit 31, reference pulse generator 33, comparison pulse generator 34, phase comparator 35, so that there is no phase difference with
The PLL circuit including the up / down counter 36, the oscillator 37, the incrementer / decrementer 38, and the frequency divider 39 operates, and the PLL clock signal PCL is locked to the reproduction data IND.

As a result, the data sampling circuit 32
IND is sampled properly and read data RD is output. Further, the PLL clock signal PCL is output to the reading unit or the like as a bit clock.

The output signal ENB of the D-latch circuit 40 is applied to the enable input terminal of the up-down counter 36, and when the output signal ENB is at the logic level H, the above-mentioned up-counting and down-counting are executed. However, when the output signal ENB enable is at the logic level L, the above-mentioned up-counting and down-counting are not executed.

As described above, when the up / down counter 36 does not perform up-counting or down-counting, the increment / decrementer 38 does not output the carry signal CY and the borrow signal BR. Only the operation of dividing the signal MCK by 1/2 is executed, and the PLL circuit becomes free-running. In this free-running state, the PLL clock signal PCL is
The state is synchronized only with the operating state of the oscillator 37 which is the reference inside the PLL circuit.

This D latch circuit 40 outputs its output signal ENB at the falling edge of the address detection signal SDD output from the address discrimination circuit 4.
Becomes a logic L level, and then the output signal ENB becomes a logic H level at the rising edge of the start pulse PST output from the counter 10.

Therefore, the address discrimination circuit 4 outputs the address detection signal SD
During the period from when D is output until the counter 10 outputs the start pulse PST, the PLL clock signal P
In the period after CL is generated, the PLL circuit executes the phase synchronization operation and locks the playback data IND.
Generates clock signal PCL.

As described above, according to the present embodiment, the influence of the gap GP2 between the pre-formatted area PF and the data area DF and the influence of the unstable operation of the optical pickup 2 in the first part of the data area DF are removed. PLL clock signal P
Since CL can be obtained, the first frame synchronization signal FS of the gater area DF can be properly detected.

In the above-described embodiment, the preformatted area is formed by the preamble, the sector synchronization signal, and the sector address, but the present invention can be applied to other than this signal format.

Further, in the above-described embodiments, the present invention is applied to the data reproducing device of the optical disk device, but the present invention can also be applied to a storage device that stores data in the same signal format.

[Effect] As described above, according to the present invention, when the target sector is detected, the bit synchronization circuit is operated without applying the reproduction signal from the storage medium to the bit synchronization circuit for a predetermined period from the detection time. Since the adverse effect of the gap and the pull-in period of the optical pickup is eliminated by self-propelling, there is an effect that the disturbance of the basic clock at the time of reproducing the first part of the preformatted area can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing a data reproducing apparatus according to an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of the apparatus shown in FIG. 1, and FIG. 3 is a bit synchronizing circuit. FIG. 4 is a block diagram showing an example, FIG. 4 is a waveform diagram for explaining the operation of the circuit shown in FIG. 3, and FIG. 5 is a waveform diagram for explaining the operation of the circuit shown in FIG. 6 (a) is a signal arrangement diagram showing an example of the recording format of the optical disc, FIG. 6 (b) is a signal arrangement diagram showing the sector format, and FIG. 7 is a schematic diagram showing the state of data on the optical disc. , 8th
FIG. 9 is a block diagram showing a conventional example of a data reproducing device, ninth.
The figure is a waveform diagram for explaining the operation of the apparatus shown in FIG. 1 ... Optical disc, 2 ... Optical pickup, 4 ... Address discrimination circuit, 6 ... Frame synchronization detection circuit, 7 ... Demodulation circuit, 8 ... Error correction circuit, 10 ... Counter, 11 ...
Bit synchronization circuit, 31 …… Edge detection circuit, 32 …… Data sampling circuit, 33 …… Reference pulse generator, 34 …… Comparison pulse generator, 35 …… Phase comparator, 36 …… Up-down counter, 37… … Oscillator, 38 …… Incrementer / decrementer, 39 …… Divider, 40 …… D latch circuit.

Claims (2)

[Claims] 1. A plurality of data frames separated by a preamble for matching circuit conditions and a frame sync signal having a sharp autocorrelation for arranging a gap at a predetermined interval with a preformatted area indicating the start of a sector. In the data reproducing method for reproducing the data recorded on the storage medium in the selected format, bit synchronization for reproducing the basic clock based on the preamble in the data frame for a predetermined period after detecting the preformat. A data reproducing method characterized in that the bit synchronizing circuit is self-propelled without supplying a reproducing signal from the storage medium to the circuit. 2. The phase synchronizing circuit according to claim 1, wherein the bit synchronizing circuit generates a bit clock of a predetermined frequency that is phase-synchronized with the reproduction signal, and the reproduction is performed in synchronization with the bit clock. A data reproducing system characterized by comprising a data sampling circuit for sampling a signal, and the self-running phase synchronizing circuit independently generating the bit clock.