JPH069381B2 - Scan line position controller - Google Patents

Description

The present invention relates to a scan line position control device, and more particularly to a CR.
The present invention relates to a scanning line position control device for controlling a position of a scanning line of a CRT monitor image receiver to obtain an image of the highest possible quality when a hard copy is obtained by capturing an image projected on a T monitor image receiver.

In order to save the image displayed on the CRT monitor receiver, for example, this image is captured by a camera to obtain a hard copy. In this case, the image is not displayed between the scan lines on the image of the CRT monitor receiver, and therefore, when the image thus displayed is photographed, the scan line is displayed on the hard copy. The contrast between the scanning line and the scanning line appears extremely conspicuously, and there is a problem that a good quality hard copy cannot be obtained.

In order to eliminate such inconvenience, a CRT has been conventionally used.
A method of superimposing a minute vibration wave on the vertical synchronizing signal of the monitor or sequentially delaying the vertical synchronizing signal is adopted. However, in the former case, it is necessary to superimpose a high-frequency micro-oscillation wave on the vertical synchronizing signal to the extent that image information is not lost,
This superposition has a problem that requires high technology. In the case of implementing the latter method, a monostable multivibrator is used for delaying the vertical synchronizing signal. That is, although this signal delay time is set by the time constant circuit of the capacitance and the resistance, there has been a problem that a stable delay time cannot always be obtained due to a temperature change or the like. Further, in the case of the interlaced display system of the signal, it is impossible to erase the scan lines if the scan lines of the even fields are not accurately located in the middle between the scan lines of the odd fields.

The present invention has been made to overcome the above-described inconvenience, and a plurality of scanning lines synchronized with a horizontal synchronizing signal in a composite television signal can be apparently inserted in one scanning period, Another object of the present invention is to provide a scanning line position control device having a simple structure.

According to the present invention, the object is to set the maximum number of scanning lines to be inserted in one scanning line interval to N, and to determine the frequency of the horizontal synchronizing signal.
_{When h} is set, a signal having a frequency N _h synchronized with the horizontal synchronizing signal is generated, while a counter having a preset value corresponding to a value obtained by dividing the vertical synchronizing signal by N is used to count the signal having the frequency N _h. However, it is achieved by triggering the vertical deflection circuit by the carry output of the counter.
As a result, the vertical sync signal is shifted by 1 / N _h
A maximum of N scanning lines can be apparently inserted within the scanning line interval.

To achieve the above object, the present invention is synchronized with a horizontal sync signal separated from a composite video signal and Nh (N is 2).
The above integer, h is the frequency of the horizontal synchronizing signal) signal generating means including a PLL circuit, a first N-ary counter for counting the vertical synchronizing signals separated from the composite video signal, and the signal generating means A second N-ary counter for counting the output of the first N-ary counter and data corresponding to the count value of the first N-ary counter, and the generated data is preset in the preset second N-ary counter in synchronization with the vertical synchronization signal. A multi-interlace setting device, which comprises a data generating means, uses the carry signal of the preset second N-ary counter as a trigger input signal of a vertical deflection circuit, and triggers at the first carry exceeding a sawtooth voltage oscillation start limit. It is characterized by being provided.

Next, preferred embodiments of the scanning line position control device according to the present invention will be described, and will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. The composite television signal applied to the input terminal 10 is supplied to the sync separation circuit 12 and separated from the sync signal. The separated sync signal is supplied to the horizontal sync separation circuit 14 to separate the horizontal sync signal, and the separated sync signal is supplied to the vertical sync separation circuit 16 to separate the vertical sync signal.
The separated horizontal synchronizing signal is amplified by an amplifier 18 and then supplied to a frequency automatic pull-in circuit 20 which produces an output having a frequency of N _h which is phase-locked with the horizontal synchronizing signal.

The pull-in circuit 20 is for alternately removing the equalizing pulse and the cutting pulse to make the synchronization of the equalizing pulse and the cutting pulse a horizontal synchronizing signal. That is, the pull-in circuit 20 is an equalizing pulse removing circuit 22 composed of a monostable multivibrator which is triggered by a horizontal synchronizing signal to generate an output having a pulse width of 3 / 4H, and an output signal frequency of the equalizing pulse removing circuit 22 is set to a voltage. To a frequency-voltage converter 24, gate circuits 26 and 28 that are controlled to open / close by the vertical sync signal separated by the vertical sync separation circuit 16, and the output phase of the monostable multivibrator 22 via the gate circuit 26 and the gate circuit. A phase comparator 30 for comparing the output phase of a frequency divider 38 described later via 28, a loop filter 32 for smoothing the output of the phase comparator 30,
A DC amplifier 34 for amplifying the output of the loop filter 32,
A voltage controlled oscillator 36 to which the output voltage of the DC amplifier 34 is applied as a control voltage and a frequency divider 38 for dividing the output frequency of the voltage controlled oscillator 36 by N are provided. In this case, the output pulse width of the monostable multivibrator 22 is corrected by the output of the frequency-voltage converter 24, and the frequency-voltage converter 24
The offset voltage related to the output voltage of the DC voltage is applied to the output of the DC amplifier 34. The output of the frequency divider 38 is applied to the horizontal deflection circuit 40 and triggers the horizontal deflection circuit 40. Here, the free-running oscillation frequency of the voltage controlled oscillator 36 is set to N _h .

On the other hand, the output of the voltage controlled oscillator 36 is supplied to the interlace setting device 44 that shifts the leading edge of the vertical synchronizing signal in units of cycle 1 / N _h , and the output of the interlace setting device 44 is amplified by the amplifier 46, This vertical deflection circuit is supplied to the vertical deflection circuit 48.
Trigger 48.

The interlace setter 44 counts the vertical sync signals separated by the vertical sync separation circuit 16 as shown in FIG. 2 if, for example, the case of apparently inserting eight scanning lines is shown.
And ary counter 44a, and 2 ^{0, 2} 1, ^{2 2,} and 2 ³ and the code setter 44b for setting each digit of the preset octal counter 44c counts the output of the voltage controlled oscillator 36, "0
7 "(decimal) data is stored and octal counter 44
The ROM 44d is configured to read setting data by using the output of a and the output of the code setting device 44b as a read address and preset the read data in the octal counter 44c.

The scanning line position control device according to the present invention is basically constructed as described above. Next, its operation and effect will be described.

First, the horizontal sync signal separated by the sync separation circuit 12 and the horizontal sync separation circuit 14 is amplified by the amplifier 18, the monostable multivibrator 22 is triggered by the trailing edge of the horizontal sync signal, and its output pulse is shown in FIG. The waveform is as shown in b). It should be noted that FIG. 3 (a) shows a synchronizing signal in a section near the vertical retrace line period in the composite television signal. As is clear from FIG. 3 (b), every other equalizing pulse and cutting pulse are removed and the interval becomes 1H. This is because the output pulse width of the monostable multivibrator 22 is set to 3 / 4H, and even if the position of the equalizing pulse or / and the cutting pulse is deviated, it is within 1/2 to 3/4 period. As long as there is, every other equalizing pulse and cutting pulse will be removed.

The frequency of the output signal of the monostable multivibrator 22 is converted into a voltage by the frequency-voltage converter 24 as shown in FIG. 3 (c). This voltage is fed back to the monostable multivibrator 22 to control the output pulse width of the monostable multivibrator 22.
The output pulse width of is controlled to 3 / 4H.

On the other hand, the vertical signal separated by the vertical sync separation circuit 16 is as shown in FIG. 3 (d), and the vertical sync signal period (low potential period in FIG. 3 (d)) shown in FIG. 3 (d). ) Except that the gates of the gate circuits 26 and 28 are controlled to be in the open state, and the output of the monostable multivibrator and the output of the frequency divider 38 are phase-compared in the phase comparator 30.
This phase comparison output is as shown in FIG. 3 (e). This phase comparison output is smoothed by the loop filter 32,
The output of the loop filter 32 is as shown in FIG. The output of the loop filter 32 is amplified by the DC amplifier 34. In this case, the output voltage of the frequency-voltage converter 24 is applied to the DC amplifier 34, and the output of the DC amplifier 34 is the frequency-voltage converter 24. Offset with the output voltage of the. This offset voltage is in a state depending on the frequency of the input synchronizing signal. In addition, the output of the DC amplifier 34 is corrected by the output of the loop filter 32 from the offset voltage.

On the other hand, the output voltage of the DC amplifier 34 is input to the voltage controlled oscillator 36. Therefore, the output frequency of the voltage controlled oscillator 36 also depends on the frequency of the horizontal synchronizing signal supplied to the input terminal 10, and becomes the frequency corrected by the phase difference between both inputs input to the phase comparator 30, and FIG. Frequency N _h shown in (g)
Is output from the voltage controlled oscillator 36.

The output from the voltage controlled oscillator 36 is divided by N by the frequency divider 38. Therefore, from the frequency divider 38, the phase synchronizing with the horizontal synchronizing signal in the synchronizing signal supplied to the input terminal 10 is shown in FIG.
The signal shown in is obtained, and this signal triggers the horizontal deflection circuit 40. Further, the output of the frequency divider 38 is supplied to the phase comparator 30 via the gate circuit 28.

Furthermore, the output of the voltage controlled oscillator 36 is input to the interlace setter 44.

On the other hand, the vertical sync signal separated by the vertical sync separation circuit 16 is an octal counter which constitutes the interlace setter
The ROM 44d is addressed by the count value 44a and the count value. Furthermore, code setter 44b
Even if the address of the ROM 44d is specified by the setting output of the ROM 44d, the count value of the octal counter 44a and the setting output of the code setter 44b are read, and the data read from the ROM 44d as an address is preset octal in synchronization with the vertical synchronizing signal. It is preset in the counter 44c. The output from the voltage controlled oscillator 36 is counted by the preset octal counter 44c.

Therefore, the preset octal counter 44c is preset with a preset value stored in the ROM 44d, for example, (1, 1, 1) in synchronization with the vertical synchronizing signal. Therefore, when the voltage controlled oscillator 36 outputs two pulses having a frequency of 8 _h with reference to the leading edge of the vertical synchronizing signal, a carry signal is output as shown in FIG. 4 (d-1). The carry signal output from the preset counter 44c is amplified and the vertical deflection circuit 48 is triggered by the carry signal. 4 (a) shows the horizontal synchronizing signal, FIG. 4 (b) shows the output signal of the voltage controlled oscillator 36, FIG. 4 (c) shows the vertical synchronizing signal, and FIG. In (d-1), ... (d-8), "9" indicates a carry signal.

When the next vertical sync signal is supplied subsequently, the counter
The output of 44a changes and the preset value "11
0 "is output and is preset in the preset counter 44c. Therefore, when three pulses of frequency 8 _h are output from the voltage controlled oscillator 36 with reference to the leading edge of the vertical synchronizing signal, the carry signal is generated as shown in FIG. Similarly, the preset value is set to "-1" every time the vertical synchronizing signal is supplied, and the voltage-controlled oscillator 36 until the carry output is generated. Output pulse number is "+1"
As a result, a carry output is generated as shown in Fig. 4 (d-3), ... (d-7). As a result, the vertical synchronizing signals are shifted by 8 _h , and apparently eight scanning lines are inserted between one scanning line.

The preset counter 44c generates a carry when the maximum number of output pulses from the voltage controlled oscillator 36 is counted based on the preset value. During this carry, the vertical deflection circuit 48c
The sawtooth oscillator is not triggered by a carry that is first exceeded by the carry start limit of the sawtooth oscillator constituting the above, and is output until the carry that exceeds the start of oscillation limit. Therefore, there is no problem even if the preset counter 44c causes a carry when counting the maximum eight output pulses from the voltage controlled oscillator 36 based on the preset value.

Although the above description exemplifies the case where eight scanning lines are inserted between one scanning line, the number can be changed by changing the preset value of the preset counter. Further, the preset value is changed by setting the code setter 44b or by changing the contents stored in the ROM 44d.

Further, instead of the ROM 44d, the preset data generating means constituted by the multiplexers 50a to 50c and the OR gate 50d as shown in FIG. 5 can be used to operate in the same manner as in the case shown in FIG.

As described above, according to the present invention, the data corresponding to the output data of the N-ary counter counting the vertical synchronization signal is preset in the preset N-ary counter in synchronization with the vertical synchronization signal, and the preset N-ary counter is used. Frequency N
_{Since the} vertical deflection circuit is triggered by the carry output of the preset N-ary counter by counting the signal of _h , the vertical synchronizing signal is shifted by 1 / N _h unit and the vertical synchronizing signal position is controlled. As a result, a maximum of N scanning lines can be apparently inserted between one scanning line, and the raster erase effect can be obtained.

Although the present invention has been described with reference to the preferred embodiment, the present invention is not limited to this embodiment,
It goes without saying that various improvements and design changes can be made without departing from the scope of the present invention.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention,
2 and 5 are block diagrams showing a configuration example of an interlace setting device in one embodiment of the present invention, and FIGS. 3 and 4 are waveform charts for explaining the operation of one embodiment of the present invention. . 10 …… input terminal, 12 …… sync separation circuit 14 …… horizontal sync separation circuit, 16 …… vertical sync separation circuit 18 …… amplifier, 20 …… pull-in circuit 22 …… monostable multivibrator 24 …… frequency-voltage Converter, 26, 28 Gate circuit 30 Phase detector 32 Loop filter 34 DC amplifier 36 Voltage controlled oscillator 38 Frequency divider 40 Horizontal deflection circuit 42 Divider, 44 …… Interlace setter 46 …… Amplifier, 48 …… Vertical deflection circuit

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Claims (3)

[Claims] 1. A signal generating means comprising a PLL circuit which is synchronized with a horizontal synchronizing signal separated from a composite video signal and generates a signal of Nh (N is an integer of 2 or more, h is a frequency of the horizontal synchronizing signal), A first N-ary counter for counting the vertical synchronizing signals separated from the composite video signal, a preset second N-ary counter for counting the output of the signal generating means, and data corresponding to the count value of the first N-ary counter are generated. And data generating means for presetting the generated data to the preset second N-ary counter in synchronization with the vertical synchronizing signal, and using the carry signal of the preset second N-ary counter as a trigger input signal of the vertical deflection circuit, A scanning having a multi-interlace setter that triggers at the first carry that exceeds the sawtooth voltage oscillation start limit, and Position control device. 2. A scanning line position control apparatus according to claim 1, wherein the data generating means comprises a read only memory (ROM). 3. A scanning line position control apparatus according to claim 1, wherein the data generating means comprises at least one multiplexer and logic means.