JPH0695107B2 - Tone signal level detector - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a tone signal level detection device applied to level measurement and reception detection of a single frequency tone signal.

(Prior Art) The level detection function of a single frequency tone signal is widely applied to level measurement such as a selective level meter and reception detection in a tone signal transmission system. In order to remove the influence of noise and distortion, it is customary to provide some kind of band limiting function. That is, as a tone signal level detecting device having a band limiting function, a bandpass filter having a frequency of a desired tone signal as a center frequency is constituted by an active filter, a switched capacitor filter, a digital filter or the like. A method of rectifying a filter output to detect a level is known.

However, among these filters, the active filter needs to be individually installed for each frequency to be used, so that the circuit scale increases in proportion to the type of frequency used. In addition, since the switched capacitor filter has an LSI configuration, development costs are high. Further, a digital filter requires high-speed iterative processing of multiplication and addition, and generally uses a signal processor, but at present, it is difficult to reduce the size and power consumption and is expensive.

As another method for detecting the tone signal level, a method based on the correlation between the desired tone signal and the input signal (correlation detection method) is known, but generally, the correlation calculation is performed by the multiplication and addition as in the case of the digital filter. Since it requires repetitive processing, there are also problems in size, power consumption, and cost.

(Object of the Invention) An object of the present invention is to solve the problems of these conventional devices, to realize correlation detection without using a multiplication process, to reduce the circuit scale and power consumption, and to set the parameters of the desired tone frequency. It is an object to provide a tone signal level detection device which is easy and most of the device can be softwareized by one single chip microcomputer.

(Structure and Operation of the Invention) FIG. 1 shows an example of the structure of a tone signal level detecting apparatus embodying the present invention. In the figure, reference numeral 1 is an oscillator (OSC) that generates a rectangular wave having a frequency eight times the desired tone frequency (f ₀ ), and its period is τ. 21 and 22 are 1/2 dividers, which divide the output of oscillator 1 and divider 21 into 1/2.
Divide. Reference symbol a is an input signal, which generally includes an unwanted signal and noise together with the desired tone signal f ₀ . 3 inputs the input signal a to each other It is a distributor that obtains two outputs having a ratio of, and can be easily configured by using an amplifier and an attenuator. An analog switch 4 switches one of the two outputs of the distributor 3 according to the binary states "L" and "H" of the output of the 1/2 frequency divider 21.

Reference numeral 5 is an A / D converter that outputs the output of the analog switch 4 to the oscillator 1
Are converted into a series of digital numerical values at the output timing of. 61, 62, 63 are delay circuits composed of shift registers for parallel information, which are continuously connected to the output of the A / D converter 5 in the order of 63, 62, 61 and A / D converted at the timing of the output of the oscillator 1. The digital values thus obtained are sequentially delayed and shifted. Therefore,
Outputs A _i , A _{i + 1} , A of the delay circuits 61, 62, 63 and the A / D converter 5
_{i + 2} and A _{i + 3} are time iτ, (i + 1) τ, and (i +
2) Time series number i, i + 1, i + corresponding to τ, (i + 3) τ
2, i + 3 (i is an arbitrary integer, τ is the time interval between adjacent series), and the digitized series value of the output of the analog switch 4 is given, and the corresponding input signal a
The sequence values of A _i , a _{i + 1} , a _{i + 2} , and a _{i + 3} (hereinafter referred to as the input sequence) are set, and the initial switching state of the analog switch 4 is the one of the level of the distributor 3 which is larger. When the output is selected, the operation of the 1/2 divider 21 Will be established respectively. Reference numerals 71 and 72 _denote combiners composed of a digital adder, a complement converter, etc., and 71 has the same polarity (indicated by) between A _i and A _{i + 1,} and
A value obtained by adding _{i + 3} with the opposite polarity (indicated by) from A _i and A _{i + 1.}
X, and 72 outputs a value ΔY obtained by adding A _{i + 1} , A _{i + 2} , and A _{i + 3} all with the same polarity (displayed by all). 81,82
Is a subtracter which uses the outputs of the combiners 71 and 72 as positive input (indicated by +), and 91 and 92 are delay circuits similar to 61, 62 and 63, both of which are 1/2 dividers. The outputs of the subtracters 81 and 82 are delayed and shifted at the timing of the output of 22, respectively, and the outputs X and Y are fed back to the negative inputs (indicated by −) of the subtractors 81 and 82, respectively. Reference numeral 10 is a level calculation circuit, which inputs the X and Y, and is a value proportional to the square root of the sum of squares thereof, (N is the number of input coefficients, which is a multiple of 8) is output to the outside as a tone signal level detection value Z, and a microcomputer with X and Y as parallel inputs or X and Y as address inputs ROM (Read Only Memor
It can be easily realized by using y). The delay circuits 91 and 92 are initialized to a neutral value (usually 0) by a reset signal (not shown) from the outside every time the tone signal level detection value Z is calculated (N input sequences). Shall be realized.

Next, another example of the configuration of the present invention is shown in FIG.

The input and output of FIG. 2 and all the constituent elements are exactly the same as those of FIG. 1, but in FIG. 2, the initial switching state of the analog switch 4 selects the output of the distributor 3 having the smaller level. State, and the combiner 71 determines that A _{i + 2} and A _{i + 3}
With the same polarity and A _i with A _{i + 2} and A _{i + 3} having a different polarity and ΔX, and the combiner 72 sets A _i , A _{i + 1} and A _{i + 2} to the same polarity. The added value is set to ΔY, and the like is different from the configuration example of FIG. Therefore, in this case, the operation of the frequency divider 21 Will be established respectively.

Next, the operation and performance of the tone signal level detecting device of the present invention, the configuration of which is shown in FIGS. 1 and 2, will be described with reference to FIG.
This will be described with reference to FIG.

FIG. 3 is an array of weighting factors in equivalent combination of the input sequences a _i , a _{i + 1} , a _{i + 2} , a _{i + 3} by the combiners 71 and 72 shown in FIGS. 1 and 2. FIG. 3A shows the case of the combiner 71, and FIG. 3B shows the case of the combiner 72. In each case, the vertical axis represents the weighting factor and the horizontal axis represents the sequence number i + k (k is an integer value) in the configuration example of FIG. 1, and the sequence number in the configuration example of FIG. ) Is attached.

First, in the configuration example of FIG. 1, the outputs ΔX, Δ of the combiners 71, 72 are
When Y is expressed as the positive polarity side of its input, and Therefore, the weighting factors at sequence numbers i, i + 1, i + 2, i + 3 are, respectively, as shown in FIG. and Becomes Further, in the configuration example of FIG. 2, if the same polarity side of the input of the synthesizer 71 is represented as a negative electrode and the same polarity side of the input of the synthesizer 72 is represented as a positive electrode, the outputs ΔX and ΔY are respectively Therefore, the weighting factors at the sequence numbers i, i + 1, i + 2, i + 3 are, as shown corresponding to the sequence numbers with () in FIG. and Becomes

As shown by the broken line in FIG. 3, the above series of weighting coefficients are values obtained by sampling half cycles of two sine waves having a phase difference of 90 ° with each other at a rate of eight times one cycle, I.e. It can be seen that it matches.

On the other hand, the output timing of the oscillator 1 shown in FIGS.
Since the frequency is divided into 1/4 by the 1/2 dividers 21 and 22 and supplied to the delay circuits 91 and 92, the outputs ΔX and ΔY of the combiners 71 and 72 are A / D.
Sequence value of 4 pieces by converter 5 and delay circuits 61, 62, 63
Each time A _i , A _{i + 1} , A _{i + 2} , A _{i + 3} is obtained (that is, every period 4τ), it is substantially taken into the subtracters 81 and 82, respectively. Therefore, A _i is the (i + 4j) th (j is an integer)
ΔX _{i + 4j} , ΔY _{i + 4j}
Let's find out the relationship with the input sequence.

First, in the configuration of FIG. Further, in the configuration of FIG. Will be established respectively. The values of ΔX and ΔY are
It is taken into the positive input of the subtracters 81 and 82 of FIGS.
Since the outputs X and Y of the delay circuits 91 and 92 are integrated with respect to the inverted values of the polarities in every cycle 4τ, the delay circuits 91 and 92 have respective N input sequences when they are obtained in the device. The absolute values | X | and | Y | of the output values X and Y are expressed by the following equations in both the configuration examples of FIGS. 1 and 2.

Here, in the configuration example of FIG. 1, from equations (2-1) and (2-2) Therefore, the following equation is obtained from the equations (3-1) and (4-1).

Similarly, from equations (3-2) and (4-2) To get

From the same consideration, in the configuration example of FIG. 2, (2-3),
From the equations (2-4), (3-1), and (3-2), the following equation is obtained as | X |, | Y |.

The above | X | and | Y | equations are the same as the configuration example ((5-1), (5-
2)) and the configuration example of FIG. 2 ((5-3), (5-4))
Both have the same frequency as the desired tone signal, and are two sine waves that are orthogonal to each other, N input sequences, and a digital correlation calculation expression, and since correlation detection is realized, the above | Tone signal level detection value Z obtained by substituting X |, | Y | into equation (1) (where X ² = | X | ² , Y ² = | Y | ² )
Indicates the absolute value of the amplitude when only the desired tone is input.

Equivalent band limitation characteristics based on the above correlation detection are expressed as H (Δ
_{f / f o) (f o} : desired tone frequencies, Delta] f: putting a deviation) between the frequency and f _o of the input signal, H (Δf / f _o) is expressed by the following equation.

This band limiting characteristic is shown in FIG.

The horizontal axis of Fig. 4 is the normalized frequency deviation Δf / f _o , and the vertical axis is (6).
The value of the formula, that is, the amount of attenuation, is expressed in logarithmic value (dB). The broken line, solid line, and alternate long and short dash line in FIG. 4 are the number of input sequences N = 10, respectively.
It has characteristics corresponding to 0,200 and 400, but both are N ×
_{π / 8 × Δf / f o} = ± mπ (m is a natural number) to satisfy the Δf / f _o
The band filtering characteristic is shown with the point of as an attenuation pole, and it can be seen that the band selectivity becomes steeper as N increases (that is, the number of observed samples increases).

Since the device of the present invention is based on digital processing using the output of the oscillator 1 as a sampling clock, in order to avoid the influence of so-called image frequency components, an analog filter (not shown) is applied to the input signal in advance. ) Is used to remove the image frequency component, but the image frequency component is (8K ± 1) f
_Since (K is a natural number), there are few restrictions on the design of the analog filter.

(Effects of the Invention) In the tone signal level detection device of the present invention, performance is stabilized by digital processing, and the parameter corresponding to the frequency of the desired tone signal is the oscillation frequency for processing (the desired tone signal 8 times the frequency) and the number of input sequences required for one detection, which is 1 compared to the system using both normal analog and digital filters.
Very few required parameters per tone signal.
Furthermore, in order to realize this, since multiplication processing is not required, the circuit scale is small and it is possible to support high-speed processing, and it is possible to implement a dedicated IC or software using a single microcomputer, etc. There are many advantages.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a tone signal level detecting apparatus embodying the present invention, and FIG. 2 is a block diagram showing another configuration example of a tone signal level detecting apparatus embodying the present invention. FIG. 4 is an explanatory view showing an array of weighting coefficients in the equivalent combination of the input sequences by the combiners 71 and 72 in FIGS. 1 and 2, and FIG. 4 is an equivalent view based on the correlation detection by the device of the present invention. It is a band limitation characteristic view. 1 …… Oscillator, 21,22 …… 1/2 divider, 3 …… Distributor, 4
...... Analog switch, 5 …… A / D converter, 61,62,63,9
1,92 ... delay circuit, 71,72 ... combiner, 81, 82 ... subtractor, 10 ... level arithmetic circuit, a ... input signal, A _i , A _{i + 1} , A _{i + 2} , A _{i + 3} ... Outputs of delay circuits 61, 62, 63 and A / D converter 5, ΔX ... Output of combiner 71, Δ
Y ... Output of synthesizer 72, X ... Output of delay circuit 91, Y ...
... output of delay circuit 92, Z ... tone signal level detection value.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hitoshi Otachi 1-1-6 Uchiyuki-cho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation Examiner Nobuhiro Higuchi (56) References JP 54-79687 (JP, JP, 79687) A)

Claims (2)

[Claims] 1. An oscillator that generates a rectangular wave having a frequency eight times the tone frequency to be detected, a first frequency divider that divides the rectangular wave by half, and outputs of the first frequency divider. A second divider that divides the A distributor that distributes to two outputs having a ratio of, an analog switch that inputs the two outputs of the distributor and switches and outputs one of them according to the binary state of the output of the first frequency divider, and the analog The output value of the switch is sequentially converted into a series of digital numerical values at the output timing of the oscillator.
The A / D converter and the output of the A / D converter are cascade-connected, and the digital numerical value is sequentially delayed and shifted at the timing of the output of the oscillator, and three digital numerical values arranged in order from the past to the present direction. A first, a second and a third delay circuit for respectively outputting a sequence, the first, second and third delay circuits and the A /
First and second combiners for adding and subtracting three of the respective outputs of the D converter and positive and negative inputs of the outputs of the first and second combiners, respectively. First
The outputs of the first and second subtractors are delayed and shifted at the output timings of the first and second subtractors and the second 1/2 divider, respectively, and the negative electrodes of the first and second subtractors are shifted. Of the fourth and fifth delay circuits, which are fed back to the input and are reset once each time a digital sequence of multiples of 8 is obtained by the A / D converter. Input outputs X and Y And a level calculation circuit for outputting a value proportional to the level detection value to the outside, and the initial state of the input switching of the analog switch is such that the output of the distributor having the higher level is selected. , The outputs of the first and second delay circuits have the same polarity and the outputs of the A / D converter have the opposite polarity to the first combiner, and are input to the second combiner. Is the second and third
The tone signal level detecting device is configured so that the output of the delay circuit and the output of the A / D converter are all input with the same polarity. 2. An oscillator that generates a rectangular wave having a frequency eight times the tone frequency to be detected, a first frequency divider that divides the rectangular wave by half, and outputs of the first frequency divider. A second divider that divides the A distributor that distributes to two outputs having a ratio of, an analog switch that inputs the two outputs of the distributor and switches and outputs one of them according to the binary state of the output of the first frequency divider, and the analog The output value of the switch is sequentially converted into a series of digital numerical values at the output timing of the oscillator.
The A / D converter and the output of the A / D converter are cascade-connected, and the digital numerical value is sequentially delayed and shifted at the timing of the output of the oscillator, and three digital numerical values arranged in order from the past to the present direction. A first, a second and a third delay circuit for respectively outputting a sequence, the first, second and third delay circuits and the A /
First and second combiners for adding and subtracting three of the respective outputs of the D converter and positive and negative inputs of the outputs of the first and second combiners, respectively. First
The outputs of the first and second subtractors are delayed and shifted at the output timings of the first and second subtractors and the second 1/2 divider, respectively, and the negative electrodes of the first and second subtractors are shifted. Of the fourth and fifth delay circuits, which are fed back to the input and are reset once each time a digital sequence of multiples of 8 is obtained by the A / D converter. Input outputs X and Y And a level calculation circuit for outputting a value proportional to the level detection value to the outside, and the initial state of the input switching of the analog switch is a state in which the output with the smaller level of the distributor is selected. , The output of the third delay circuit and the output of the A / D converter are input to the first synthesizer with the same polarity and the output of the first delay circuit is input with the opposite polarity, A tone signal level detecting device characterized in that the first, second, and third outputs are all input to the second combiner with the same polarity.