JPH0695133B2 - IC test system - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC test system, and more specifically, to a digital test section for performing a digital signal system test on an IC to be tested and a test section for this digital test section. In an IC test system including a main controller for controlling, a predetermined digital pattern can be continuously switched and generated without generating a dummy cycle from a digital test section.

(Prior Art) FIG. 5 is a block diagram showing an example of a system used for testing an LSI in which an analog signal system and a digital signal system are mixed and integrated. In FIG. 5, AM is an analog test unit that performs analog signal system tests such as adding an analog signal to an IC to be tested (hereinafter referred to as DUT) and measuring an analog signal output from the DUT. FC is a digital test unit that performs a digital signal system test by adding a predetermined digital pattern to the DUT, and MC is a main controller that comprehensively controls these test units AM and FC.

In such a configuration, the test units AM and FC are connected to the main controller MC by a relatively low speed bus (about 1 MW / S). Then, the main controller MC performs a generation operation of a data communication test signal such as measurement data and pattern data and a start / stop control of the measurement operation for each test unit AM, FC.

By the way, focusing on the speeds required for the digital test unit FC and the main controller MC, the digital test unit FC has 25 ns to 100 ns per instruction, while the main controller MC has 500 ns to 3000 ns per instruction. For example, as the processor of the digital test unit FC, a micromachine with one instruction of 100 ns or less and a microcode of about 50 to 120 bits is used.
As a general-purpose microprocessor such as 68000 or 8086 is used.

(Problems to be solved by the invention) However, according to such a configuration, the main controller
The MC cannot follow the speed of each instruction of the digital test unit FC, and cannot synchronize in detail. Therefore, in general, the main controller MC often only executes simple instructions such as start and stop to the digital test unit FC. In addition, general-purpose slice AL is used in the digital test section FC.
Some U (Am2901 manufactured by Advanced Micro Devices Co., Ltd.) is provided to perform synchronous communication with the main controller MC at a relatively slow speed, but data is transmitted inside the ALU when switching digital patterns. The output of the digital pattern is stopped in that section, and a dummy cycle is generated. In such a dummy cycle, for example, an analog signal system and a digital signal system are mixed and accumulated.
When testing the LSI, inconvenience occurs when continuity of digital patterns is required.

The present invention focuses on such a point, and an object thereof is to provide an IC test system capable of switching a digital pattern without causing a dummy cycle.

(Means for Solving Problems) The present invention that achieves such an object includes a digital test unit that performs a digital signal system test on an IC to be tested, and a main controller that controls the digital test unit. In the IC test system, the digital test section receives the rising edge of the digital pattern switching command signal applied to the digital test section from the main controller, and then raises a flag applied to the instruction decoder A handshake logic for raising a response signal to be returned to the main controller is provided, and the main controller lowers the digital pattern switching command signal after the digital pattern is switched,
The handshake logic is characterized in that the response signal falls after the fall of the digital pattern switching command signal.

(Example) Hereinafter, it demonstrates in detail using drawing.

FIG. 1 is a block diagram showing an embodiment of the present invention.
In FIG. 1, in addition to the signal RUN / STOP for controlling the start / stop of the digital test unit FC from the main controller MC, a command signal GO for pattern switching is added, and the digital test unit FC sends the command signal GO. A response signal GACK corresponding to the command signal GO is sent back to.

FIG. 2 is a block diagram showing a specific example of the digital test unit FC according to the present invention. In FIG. 2, MUX1 is an address multiplexer which selectively outputs an address by using a decoder signal added from the instruction decoder ID as a selection signal. This address multiplexer MUX1
Is added with the address stored in the jump address memory JM via the pipeline register PLR and the address output from the program counter PC. The address output from the address multiplexer MUX1 is added to the instruction memory IM, the jump address memory JM, the condition multiplexer memory CM and the pattern memory PM, and is also added to the program counter via the arithmetic unit that adds +1 to the address. ing. These instruction memory IM, jump address memory JM, condition multiplexer memory CM and pattern memory
The outputs of PM are added to pipeline registers PLR1 to PLR4, respectively. The output of the pipeline register PLR1 is added to the instruction decoder ID, the output of the pipeline register PLR2 is added to the address multiplexer MUX1, the output of the pipeline register PLR3 is added to the condition multiplexer MUX2 as a selection signal, and the output of the pipeline register PLR4 is added. The output is applied to the DUT as a digital pattern. Condition multiplexer MUX
A predetermined flag indicating completion of the handshake operation is added to 2 from the handshake logic HSL, and a flag indicating each status is added from other parts not shown. The handshake logic HSL has an instruction memory I as a control symbol.
M output has been added. A command signal GO for pattern switching is added to the handshake logic HSL from the main controller MC, and a response signal GACK corresponding to the command signal GO is returned from the handshake logic HSL to the main controller MC.

The operation of the system thus configured will be described.

FIG. 3 is an explanatory diagram showing an example of a program for operating the system of FIG. 2, and FIG. 4 is a timing chart. In addition, in FIG. 4, (a) is a clock CLK.
, (B) shows the state of the table output from the pattern memory PM, (c) shows the command signal GO applied to the handshake logic HSL from the main controller MC for pattern switching, and (d) shows the handshake. Logic H
The response signal GACK added from SL to the main controller MC in response to the command signal GO is shown, and (e) shows the flag FLAG added from the handshake logic HSL to the instruction decoder ID.

For example, if a command signal GO for pattern switching is applied to the handshake logic HSL from the main controller MC at time t _{1 when the} digital pattern based on the table A is output, the clock CLK immediately after that is output.
Flag rises to the rising time t ₂ of. Then, the handshake logic HSL outputs a response signal GACK corresponding to the command signal GO to the main controller MC at time t ₃ after the flag rises. on the other hand,
Address multiplexer MUX1, a table for generating a predetermined digital pattern to the rise time t ₄ of the next clock CLK by the flag is output from the handshake logic HSL (Table B in this example)
The address corresponding to is output. As a result, the pipeline register PLR4 outputs a digital pattern corresponding to the table B. Thus the main controller MC at time t ₅ after the table is switched to the released command signal GO, the handshake logic HSL in the subsequent time t ₆ releases the response signal GACK. Incidentally, in a series of table switching operation from these time t ₁ to time t _6, from time t ₁ to time t ₄ is performed at high speed, from time t ₄ to time t ₆ is performed at low speed.

As is clear from these explanations, by configuring as shown in FIG. 2, it is possible to switch the table at high speed without generating a dummy cycle when switching the table. For example, an analog signal system and a digital signal system can be used. There is no inconvenience even when the continuity of the digital pattern is required for the test of the LSI integrated and mixed.

Also, regarding the synchronization between the main controller MC and the digital test unit FC, the next step is not performed until the mutual signals are completely recognized, so that the synchronization is not broken.

Also, for the program, it is only necessary to add simple instructions (JMNG) and it does not become complicated.

Moreover, regarding the circuit configuration, it is only necessary to add two to three ICs, and the configuration is relatively simple and inexpensive.

In the above embodiment, the example of the system used for testing the LSI in which the analog signal system and the digital signal system are mixed and integrated has been described.
It can also be applied to the test system of.

(Effects of the Invention) As described above, according to the present invention, it is possible to realize an IC test system capable of switching digital patterns with a relatively simple configuration without causing a dummy cycle,
The practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a concrete example of a digital test unit FC according to the present invention, and FIG. 3 is a program for operating the system of FIG. 4 is a timing chart, and FIG. 5 is a block diagram showing an example of an IC test system to which the present invention is applied. AM …… Analog test section, DUT …… Test target IC, FC…
… Digital test department, MC… Main controller, HSL
...... Handshake logic.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nagaki Arasawa 2-9-32 Nakamachi, Musashino-shi, Tokyo Inside Yokogawa Hokushin Electric Co., Ltd. (56) Reference JP-A-57-116269 (JP, A) JP JP-A-54-123053 (JP, A) JP-A-58-141055 (JP, A) JP-A-59-69836 (JP, A) JP-A-57-10858 (JP, A) JP-A-57-168367 (JP , A) JP-B-51-42905 (JP, B1) "Microcomputer Basic Course 5 Test and Reliability" PP. 109-111 Ohmsha issued April 20, 1982

Claims (1)

[Claims] 1. An IC test system comprising: a digital test section for performing a digital signal system test on an IC to be tested; and a main controller for controlling the digital test section, wherein the digital test section has a digital signal from the main controller. Handshake logic that raises a flag that is applied to the instruction decoder by receiving the rising edge of the digital pattern switching command signal that is applied to the test unit, and then activates the response signal that is returned to the main controller in response to this command signal. The main controller lowers the digital pattern switching command signal after the digital pattern is switched,
The digital signal generator, wherein the handshake logic causes the response signal to fall after the fall of the digital pattern switching command signal.