JPH0695564B2 - Semiconductor integrated device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an ultrahigh-speed semiconductor integrated device using a high-speed carrier at a semiconductor heterojunction interface.

(Background of technology and problems of conventional technology) In recent years, field-effect transistors (hereinafter referred to as FETs) that use high-speed carriers at the heterojunction interface have been regarded as promising as one of ultra-high-speed devices, and in reality, they are simple substances. High performance as an element has also been confirmed.

However, prior art (eg, gallium arsenide IC Symposium Technical Digest (GaAs I
C Symposium Technical Digest (1984), page 125)) uses a so-called recess structure in which a part of the semiconductor layer under the gate electrode of the FET is dug, so control of the gate threshold voltage and other characteristics is performed. There was a problem in terms of reliability and reliability. In other words, originally, in this element, the characteristics relating to the FET greatly change due to the processing accuracy and damage of the semiconductor layer. Therefore, with the conventional technology, the semiconductor integrated device with high element uniformity demands high performance. It was difficult to realize it in a way that makes the most of it.

(Object of the Invention) The object of the present invention is to eliminate the above-mentioned drawbacks in the prior art, and in particular, the controllability of the gate threshold voltage and the FET characteristics is high, and the degree of freedom in selecting the constituent elements is increased. It is to provide a highly reliable ultra-high speed semiconductor integrated device.

(Structure of the Invention) According to the present invention, a high-purity or p-type first semiconductor layer on a high-resistance substrate, and an n-type second semiconductor layer smaller than the electron affinity of the first semiconductor, A p-type third semiconductor layer is sequentially provided, at least one first control electrode is provided on the third semiconductor layer, and the first semiconductor layer is sandwiched by the first control electrode. And at least two first and second ohmic regions electrically connected to a channel region formed at a junction interface between the second ohmic region and the second semiconductor layer, and at least one of the second ohmic regions, An n-type fourth semiconductor layer is provided on the third semiconductor layer facing the first control electrode, and at least one n-type fourth semiconductor layer electrically connected to the channel region is provided on the fourth semiconductor layer. A second control voltage is provided between the third ohmic region and the second and third ohmic regions. A semiconductor integrated device characterized by having zero or more poles is obtained.

Further, according to the present invention, a high-purity or n-type first semiconductor layer and a p-type second semiconductor larger than the sum of the electron affinity and energy gap of the first semiconductor are provided on the high-resistance substrate. A layer and an n-type third semiconductor layer are sequentially provided, and at least one first control electrode is provided on the third semiconductor layer, and the first control electrode is sandwiched between the first and second control electrodes. At least two first and second electrical regions electrically connected to a channel region formed at a junction interface between the semiconductor layer and the second semiconductor layer.
An ohmic region is provided, and a p-type fourth semiconductor layer is provided on the third semiconductor layer facing the first control electrode for at least one of the second ohmic regions.
On the semiconductor layer, at least one third ohmic region electrically connected to the channel region, and the second and third ohmic regions.
A semiconductor integrated device is obtained in which zero or more second control electrodes are provided between the ohmic regions.

Further, according to the present invention, a high-purity or p-type first semiconductor layer, an n-type second semiconductor layer smaller than the electron affinity of the first semiconductor, and a p-type first semiconductor layer are formed on a high-resistance substrate. 3 semiconductor layers are sequentially provided, at least one first control electrode is provided on the third semiconductor layer, and the first semiconductor layer and the second control layer are sandwiched by the first control electrode. Of at least two first and second ohmic regions electrically connected to the channel region formed at the junction interface with the semiconductor layer, the first ohmic region being at least one of the second ohmic regions. An n-type fourth semiconductor layer electrically connected to the second ohmic region is provided on the third semiconductor layer facing the control electrode, and at least the fourth semiconductor layer is provided on the fourth semiconductor layer. At least one third ohmic region electrically connected to the fourth semiconductor layer; Beauty second during a third ohmic region
A semiconductor integrated device is obtained in which zero or more control electrodes are provided.

Further, according to the present invention, a high-purity or n-type first semiconductor layer and a p-type second semiconductor larger than the sum of the electron affinity and energy gap of the first semiconductor are provided on the high-resistance substrate. A layer and an n-type third semiconductor layer are sequentially provided, and at least one first control electrode is provided on the third semiconductor layer, and the first control electrode is sandwiched between the first and second control electrodes. At least two first and second electrical regions electrically connected to a channel region formed at a junction interface between the semiconductor layer and the second semiconductor layer.
Of the p-type ohmic region electrically connected to the second ohmic region on the third semiconductor layer facing the first control electrode with respect to at least one of the second ohmic regions. A fourth semiconductor layer is provided, and on the fourth semiconductor layer, at least one third ohmic region electrically connected to the fourth semiconductor layer and the second and third ohmic regions.
A semiconductor integrated device is obtained in which zero or more second control electrodes are provided between the ohmic regions.

(Principle and Action of the Invention) Hereinafter, the principle of the present invention and its unique action and effect will be clarified with reference to the drawings. For convenience of explanation, a specific material will be used, but it is obvious that the invention can be applied to other materials by checking the principle of the present invention.

FIG. 1A is a schematic structural sectional view showing an example of the basic structure of a semiconductor integrated device of the present invention.

In FIG. 1A, 11 is a high-resistance substrate, 12 is a high-purity or p-type first semiconductor layer, and 13 has an electron affinity smaller than that of the first semiconductor layer 12. ,
An n-type second semiconductor layer, 14 is a p-type third semiconductor layer, 15 is an n-type fourth semiconductor layer, 16, 18 and 19 are ohmic electrodes, and 17 is a control electrode.

1 (b) and 1 (c) show the semiconductor integrated device according to the present invention shown in FIG. 1 (a) under the control electrode 17 and the fourth semiconductor layer under thermal equilibrium state, respectively.
It is an example of the energy band diagram under the surface of 15. First
In FIG. 1B and FIG. 1C, E _C is the energy level at the bottom of the conduction band, and E _F is the Fermi level. 1 (a), (b) and (c) shown here integrate a normally-off type FET (left side of FIG. 1 (a)) and a current saturation type resistor (right side of FIG. 1 (a)). This shows the case where the

The basic principle of the present invention is to uniformly control V _T and other characteristics of elements incorporated in a semiconductor integrated device by determining a desired gate threshold voltage V _T at the time of crystal growth of a semiconductor layer. Especially. That is, for example, FIG. 1 (a)
By setting the film thicknesses and the impurity densities of the second and third semiconductor layers 13 and 14 to appropriate values, the electric potential at the interface between the second and third semiconductor layers 13 and 14 is increased, and therefore the thermal equilibrium is increased. In this state, as shown in FIG. 1 (b), carriers (currently electrons) do not exist at the heterojunction interface between the first and second semiconductor layers 12 and 13, that is, a normally-off state is generated. be able to. Further, in FIG. 1A, for example, the potential at the interface between the second and third semiconductor layers 13 and 14 is lowered by setting the film thickness and impurity density of the fourth semiconductor layer 15 to appropriate values. Therefore, under the thermal equilibrium state, carriers are present at the heterojunction interface between the first and second semiconductor layers 12 and 13 as shown in FIG. 1C, that is, a substantially normally-on state is generated. be able to.

Hereinafter, the basic principle of the present invention will be described in more detail.
First, in FIG. 1 (a), a design guideline for V _T of a normally-off type FET (hereinafter referred to as E-FET) having a control electrode 17 will be described. Referring to FIG. 1 (b), this V _T is the Pilt-in voltage of the second semiconductor layer 13 is Vbi,
The energy difference at the bottom of the conduction band at the heterojunction interface between the semiconductor layers 12 and 13 is ΔE _C , the energy difference between E _C and E _F of the first semiconductor layer 12 is δ, and the second and third thermal equilibrium states are Semiconductor layer 13
And 14 interface the energy difference between the potential and E _F in When Vin, it can be seen that given approximately by the following equation.

_{V T = Vin-Vbi- △ E} C -δ (1) where, approximately Vbi than (1) to be designed as a [delta] = 0 to zero the V _T of the E-FET for example = Vin- △ E _C (2) At this time, Vin is the second and third semiconductor layers 13 and 14
It is mainly determined by the impurity density and the film thickness. However, if the impurity density of the third semiconductor layer 14 is sufficiently higher than that of the second semiconductor layer (for example, about 10 times), and if the impurity density is made high, the value of this Vbi is equal to that of the third semiconductor layer 14. Is almost equal to. Therefore, equation (2) is Becomes Here, the impurity density of the second semiconductor layer 13 And q is the electron charge amount, Given in. Therefore, from equations (3) and (4) And follows this formula (5) Is used for the second semiconductor layer 13, an E-FET with T _T 0 is realized.

On the other hand, in FIG. 1 (a), for example, two of the heterojunction interfaces of the first and second semiconductor layers 12 and 13 having the electrodes 18 and 19 are formed.
The design guideline of the current-saturation type resistor which uses the dimensional electron gas as the carrier is described. As described above, by the junction of the second and third semiconductor layers 13 and 14 which form the E-FET,
At the heterojunction interface between the first and second semiconductor layers 12 and 13, a normally-off state in which no channel is formed in a thermal equilibrium state is realized. However, the third semiconductor layer 14
The thickness d ₃ of the semiconductor layer 14 is sufficiently thin, and the impurity density of the fourth layer is substantially equal to or higher than the impurity density of the semiconductor layer 14.
By providing the semiconductor layer 15 of, the third semiconductor layer 14 is completely depleted, Vin is substantially reduced, V _T seen as a so-called FET shown in the equation (1) shifts to the negative side, Therefore, a channel is formed at the heterojunction interface between the first and second semiconductor layers 12 and 13. Here, by design, the film thickness d _{3 of} the third semiconductor layer 14, the acceptor impurity density N _A, and the film thickness d _{4 of} the fourth semiconductor layer 15 are Must follow the formula: That is, according to the law of continuous electric flux density The condition of is satisfied. Here, ▲ d ^′ ₂ ▼ is the width of the depletion layer from the interface of the second semiconductor layer 13 with the third semiconductor layer 14, and ▲ d
^′ ₃ ▼ is the depletion layer width from the interface of the third semiconductor layer 14 with the second semiconductor layer 13, and ▲ d ^″ ₃ ▼ is the fourth depletion of the third semiconductor layer 14.
Width of the depletion layer from the interface with the semiconductor layer 15 of ( ₄₎ , (d ^′ ₄₎ is the width of the depletion layer from the interface of the fourth semiconductor layer 15 with the third semiconductor layer 14, Is the donor impurity density of the fourth semiconductor layer 15. Therefore, it is necessary for the third semiconductor layer 14 to satisfy the following formula: ▲ d ^′ ₃ ▼ ≦ d ₃ <▲ d ^′ ₃ ▼ + ▲ d ^″ ₃ ▼ (8). With respect to 15, although it depends on the design value of the saturation current of the resistance in this case, it is necessary to satisfy d ₄ ≧ ▲ d ^′ ₄ ▼ (9) for this film thickness d ₄ . With regard to the above, it is desirable that the height be at least near the interface with the third semiconductor layer 14.

On the other hand, a design guideline for a current-saturation-type resistor that uses, for example, electrons existing in the fourth semiconductor layer 15 as carriers will be described. In this case, the condition of equation (9) described above is no longer necessary,
Instead, it becomes necessary to satisfy the following formula.

d ₄ <▲ d ^′ ₄ ▼ (10) In this case, depending on the settings of the second, third and fourth impurity densities and the film thickness, two of the heterojunction interfaces of the first and second semiconductor layers 12 and 13 may be formed. Eliminates the existence of three-dimensional electron gas, and is effectively the fourth
Only the carriers in the semiconductor layer 15 are examined as conduction carriers on the load side. Of course, both carriers can be made to exist and used. It is also clear that a normally-on FET can be formed, for example by providing a second control electrode between the electrodes 18 and 19.

Incidentally, in manufacturing, in order to form the control electrode 17 on the third semiconductor layer, it is necessary to remove at least the fourth semiconductor layer 15 in this region. However, the processing accuracy at the time of removal only affects the uniformity of the film thickness of the third semiconductor layer 14, and the V _T of the FET in this portion is determined by the second third semiconductor layer 13
The effect on the V _T and characteristics of the FET is almost negligible as it is largely determined at the junctions of 14 and 14. Similarly, surface damage due to processing hardly contributes to the characteristics.

Therefore, it is clear that the present invention makes it possible to produce an ultrahigh-speed semiconductor integrated device in which the V _T and other characteristics of the FET are substantially uniform and have both normally-on type and normally-off type.

(Example) Next, the Example of this invention is described. A schematic structural sectional view of the FET in this embodiment is similar to that shown in FIG. In this embodiment, the high resistance substrate 11 is a high resistance GaAs substrate, the first semiconductor layer 12 is an undoped GaAs film having an impurity density of 1 × 10 ¹⁵ cm ⁻³ or less and a film thickness of 1 μm, and the second semiconductor layer is a second semiconductor layer.
13, the donor impurity density is about 2 × 10 ¹⁸ cm ^-3 and the film thickness is about 350.
N-type Al _0.3 Ga _0.7 As of about Å is used as the fourth semiconductor layer 15 in the third semiconductor layer 14 with p-type GaAs having an acceptor impurity density of about 2 × 10 ¹⁹ cm ^-3 and a film thickness of about 100 Å. N-type GaAs having a donor impurity density of about 1 × 10 ¹⁹ cm ^-3 and a film thickness of about 250 Å is formed by, for example, molecular beam epitaxy (MBE),
AuGa / Ni electrodes are used for the ohmic electrodes 16, 18 and 19.
An electrode made of aluminum (Al) is formed on the control electrode 17. The energy band diagram under the thermal equilibrium state in this example is a discontinuity value ΔE _C (~ 0.3e) of the energy level at the bottom of the conduction band at the heterojunction interface between the second and third semiconductor layers 13 and 14.
Although V) needs to be considered, it is basically the same as that shown in FIGS. 1 (b) and 1 (c). That is, the region immediately below the control electrode 17 is in the normally-off state, and the region directly below the fourth semiconductor layer 15 is in the normally-on state. That is, in this example, an inverter circuit including a normally-off type FET and a current saturation type resistor is configured.
The film thickness and impurity density of the fourth semiconductor layer in this example are designed so that the third and fourth semiconductor layers 14 and 15 are completely depleted in consideration of the spread width of the surface depletion layer. Therefore, these two semiconductor layers 14 and 15 do not contribute to conduction, and the channel in this example is a high-speed two-dimensional electron layer 20 formed at the heterojunction interface between the first and second semiconductor layers 12 and 13. Only. Here, V _T of the E-FET in this example
Is almost 0 V, which is a value corresponding to the substantial V _T of the current saturation resistance, that is, a Schottky electrode made of, for example, Al.
Of the normally-on type provided on the fourth semiconductor layer between
The value given as V _T of the FET was approximately -0.6V.
The fourth semiconductor layer necessary for forming the control electrode 17
Almost no change in V _T due to etching of 15 was observed, and 2
The variations in V _T and transconductance gm in the inch substrate plane were extremely small.

It should be noted that a normally-on type FET (D-FET) can be easily realized instead of the current saturation type resistor used in this example. That is, a Schottky electrode made of, for example, Al is formed on the fourth semiconductor layer between the ohmic electrodes 18 and 19, and the voltage applied to the Schottky electrode causes the two-dimensional electronic layer to be formed.
Change the conductivity of 20. For example, by short-circuiting the Schottky electrode and the ohmic electrode 18, a high speed inverter circuit can be realized. In this example, the third and fourth semiconductor layers between the electrodes 16 and 17 and the electrodes 18 and 17 are removed as shown in FIG. It is not necessary to remove it because the electron channel can be formed under this region. Furthermore, the electrode
It is not necessary to use metal for 16, 17, 18 and 19, and it is also possible to form a semiconductor layer having a high impurity density by, for example, a vapor phase growth method. It should be noted that the electrode 18 does not have to contact the semiconductor layers 14 and 15 in this case.

In order to increase the mobility of two-dimensional electrons at the heterojunction interface, a high-purity semiconductor layer called a spacer layer, for example, AlGa, is formed at the junction interface between the first and second semiconductor layers 12 and 13.
It is also possible to use As. With respect to element isolation, which is important for integration of semiconductor elements, since this structure is almost planar, element isolation can be easily performed by mesa etching or ion implantation of oxygen ions, boron ions, protons and the like.

(Regarding the Second Invention) In the above description of the first invention, the case where the carrier is an electron has been described, but the principle of the present invention can be similarly applied to the case where the carrier is a hole. In this case, holes are somewhat different from the case of electrons because holes are accumulated in the valence band.

FIG. 2A is a schematic structural cross-sectional view showing an example of the basic structure of a semiconductor integrated device having a hole channel according to the present invention.

In FIG. 2A, 2 is a high-resistance substrate, 22 is a high-purity or n-type first semiconductor layer, and 23 is larger than the sum of electron affinity and energy gap of the first semiconductor layer 22. It has a sum of electron affinity and energy gap and is a p-type second semiconductor layer, 24 is an n-type third semiconductor layer, 25 is a p-type fourth semiconductor layer, and 26, 28 and 29 are ohmic. And 27 is a control electrode.

2 (b) and 2 (c) show the semiconductor integrated device according to the present invention shown in FIG. 2 (a) immediately below the control electrode 27 and the fourth semiconductor layer under thermal equilibrium, respectively.
It is an example of the energy band diagram under the surface of 25.

In FIGS. 2B and 2C, E _F is the Fermin level, E _V is the energy level at the top of the valence band, and 30 is the two-dimensional hole layer. 2 (a) and 2 (b) shown here.
(C) shows the case where a normally-off type FET and a current saturation type resistor are integrated.

It goes without saying that the semiconductor integrated device according to the present invention has, in principle, the same principle, action, and effect as in the case where electrons are used as the carriers described in the description of the first invention.

(Example) Next, one example of the second invention using holes as carriers will be described. A schematic structural sectional view of the semiconductor integrated device in the present embodiment is similar to FIG. In this embodiment, 21 is a high resistance GaAs substrate and 22 is a non-doped film having an impurity density of about 1 × 10 ¹⁵ cm ⁻³ or less and a film thickness of 1 μm.
Ge, 23 is p-type GaAs with an acceptor impurity density of about 3 × 10 ¹⁸ cm ^-3 and a film thickness of about 300Å, 24 is n with a donor impurity density of about 2 × 10 ¹⁹ cm ^-3 and a film thickness of about 100Å. -Type GaAs with an acceptor impurity density of about 1 × 10 ¹⁹ cm ^-3 and a film thickness of about 300
Å p-type GaAs is formed by, for example, the MBE method,
AuZn electrodes are formed on the ohmic electrodes 26, 28 and 29, and Al electrodes are formed on the control electrode 27. The energy band diagram under the thermal equilibrium state in this example is basically the same as that shown in FIGS. 2 (b) and 2 (c). That is, the region immediately below the control electrode 27 is in the normally-off state, and the region directly below the fourth semiconductor layer 25 is in the normally-on state. That is, in this example, an inverter circuit including an E-FET and a current saturation type resistor is configured. In this example, it is desirable that the third and fourth semiconductor layers 24 and 25 are completely depleted. Here, V of E-FET in this example
_T is almost 0V. It should be noted that there was almost no change in V _T due to the etching of the fourth semiconductor layer 25 necessary for forming the control electrode 27, and the variations in V _T and gm within the plane of the coninch substrate were extremely small.

Further, it goes without saying that the contents described in the first embodiment of the invention using the electron channel can be applied to the present invention as they are in principle.

(Regarding the Third Invention) In the above description of the first and second inventions, the case where the two-dimensional carrier at the heterojunction interface is used as the load-side conductive carrier has been described. The basic principle of the present invention can be similarly applied to the case where the carrier in the bulk is used.

FIG. 3A is a schematic structural sectional view showing an example of a basic structure of a semiconductor integrated device using bulk electrons on the load side according to the present invention.

In FIG. 3A, 31 is a high resistance substrate, 32 is a high-purity or p-type first semiconductor layer, and 33 has an electron affinity smaller than that of the first semiconductor layer 32. And an n-type second semiconductor layer 34 is a p-type third semiconductor layer 35
Is an n-type fourth semiconductor layer, 36, 38 and 39 are ohmic electrodes, and 37 is a control electrode.

FIG. 3B is an example of an energy band diagram under the surface of the fourth semiconductor layer 35 in the thermal equilibrium state in the semiconductor integrated device according to the present invention shown in FIG. 3A. FIG. 3B shown here is a normally-off type FE.
This shows a case where current saturation resistances using T and the bulk electrons of the fourth semiconductor layer 35 are integrated.

It goes without saying that the semiconductor integrated device according to the present invention has basically the same principle, operation and effect as those shown in the description of the first and second inventions.

(Example) Next, the Example of this invention is described. A schematic structural sectional view of the semiconductor integrated device in the present embodiment is similar to FIG. In principle, the same components as those shown in FIGS. 1 (a) and 2 (a) are designated by the same reference numerals. In this embodiment, 31 is a high resistance GaAs substrate, 32 is a non-doped GaAs having an impurity density of 1 × 10 ¹⁵ cm ⁻³ or less and a film thickness of 0.5 μm, and 3
3, the donor impurity density is about 2 × 10 ¹⁸ cm ^-3 and the film thickness is about 350Å
Al _0.3 Ga _0.7 As of 34, acceptor impurity density of 2 × 10
P-type GaAs with a film thickness of about 150 cm at about ¹⁹ cm ^-3 and n-type G with a donor impurity density of about 1 × 10 ¹⁸ cm ^-3 and a film thickness of about 700 Å at 35
aAs is formed by, for example, metal organic chemical vapor deposition (MOCVD), AuGe / Ni electrodes are formed on the ohmic electrodes 36, 38 and 39, and tungsten (W) electrodes are formed on the control electrode 37. In this embodiment, a normally-off state is realized just below the control electrode 37 of the drive FET shown on the left side of FIG. 3 (a) as in FIG. 1 (b) of the first invention. At the heterojunction interface of the first and second semiconductor layers 32 and 33 below the surface of the fourth semiconductor layer 35 having the resistance on the load side shown on the right side of (a), FIG. 1 (c) of the first invention. Unlike, it is in a normally off state. This is a result of reducing the donor impurity concentration of the fourth semiconductor layer 35 and further increasing the film thickness of the third semiconductor layer 34. However, the fourth semiconductor layer
Since the film thickness of 35 is thickened, without completely depleting,
Therefore, a normally-on state is realized in the fourth semiconductor layer 35, and the bulk electrons in the fourth semiconductor layer 35 carry the load. This state is shown in FIG. 3 (b). FIG. 3 (b) is a fourth semiconductor layer of the resistance on the load side.
The energy band diagram in the thermal equilibrium state under the surface of 35 is shown. The carrier electrons are represented by ●. Therefore, in FIG. 3 (a), it is constituted by an E-FET that controls the conductivity of the two-dimensional electron layer 20 and a current saturation type resistor that uses the conductivity of carrier electrons in the fourth semiconductor layer 35. ER type inverter circuit configuration can be realized.

The feature of this embodiment is that semiconductor elements that control carrier electrons traveling in two different semiconductor layers are integrated on the same substrate in principle, and, for example, the degree of freedom in design regarding the current driving capability of the load of the inverter circuit is improved. To improve the integration degree and performance of the semiconductor integrated device.

Also in this example, variations in V _T and gm in the plane of the 2-inch substrate were extremely small.

Further, in the present embodiment, a control electrode between the electrodes 38 and 39,
For example, by providing a Schottky electrode made of Al, the conductivity of the channel on the load side can be controlled. In this case, an inverter circuit including an E-FET and a D-FET can be realized by short-circuiting the control electrode and the electrode 38, for example.

Further, both the two-dimensional electron layer formed at the heterojunction interface between the first and second semiconductor layers 32 and 33 and the bulk electrons in the fourth semiconductor layer 35 can be used as the conduction carriers on the load side. is there. In this case, ohmic electrodes 38 and 39
Must be electrically connected to both the fourth semiconductor layer 35 and the two-dimensional electronic layer.

It is obvious that the contents described in the embodiments of the first and second inventions can be applied to the present invention as it is in principle.

(Regarding the Fourth Invention) The third invention has been described above using the electrons in the bulk of the semiconductor layer as the conduction carriers on the load side. However, the present invention is also applicable to the case where the carriers use holes in the bulk. The principle of can be applied similarly.

FIG. 4A is a schematic structural cross-sectional view showing an example of the basic structure of a semiconductor integrated device using bulk holes on the load side according to the present invention.

In FIG. 4A, 41 is a high-resistance substrate, 42 is a high-purity or n-type first semiconductor layer, and 43 is the sum of electron affinity and energy gap of the first semiconductor layer 42. And a p-type second semiconductor layer, 44 is an n-type third semiconductor layer, 45 is a p-type fourth semiconductor layer, 46, 48 and 49 are ohmic electrodes, and 47 is a control electrode. .

FIG. 4B is an example of an energy band diagram below the surface of the fourth semiconductor layer 45 in a thermal equilibrium state in the semiconductor integrated device according to the present invention shown in FIG. 4A. FIG. 4 (b) shown here is a normally-off type FE.
This shows the case where current saturation type resistors using T and the bulk holes of the fourth semiconductor layer 45 are integrated.

It goes without saying that the semiconductor integrated device according to the present invention has the same principle, action, and effect as the case shown in the description of the first, second, and third inventions.

(Example) Next, the Example of this invention is described. A schematic structural sectional view of the semiconductor integrated device in the present embodiment is similar to FIG. In principle, the same components as those shown in FIGS. 1 (a), 2 (a) and 3 (a) are designated by the same reference numerals. In this embodiment, 41 is a high resistance GaAs substrate,
42 with an impurity density of about 1 × 10 ¹⁵ cm ^-3 or less, a film thickness of about 1 μm
Non-doped Ge with 43 and an acceptor impurity density of 3 × 10
^{About 18} cm ^-3 of p-type GaAs with a film thickness of about 300 Å, 44 with n-type G with a donor impurity density of about 2 × 10 ¹⁹ cm ^-3 and a film thickness of about 150 Å
p-type GaAs with an acceptor impurity density of about 1 × 10 ¹⁸ cm ^-3 and a film thickness of about 800 Å is formed on the 55 by, for example, the MBE method. An electrode made of Al is formed on the control electrode 47. In this embodiment, a normally-off state is realized just below the control electrode 47 of the drive FET shown on the left side of FIG. 4 (a) as in FIG. 2 (b) of the second invention. At the heterojunction interface of the first and second semiconductor layers 42 and 43 below the surface of the fourth semiconductor layer 45 of the load side resistance shown on the right side of (b),
Unlike FIG. 2 (c) of the second invention, it is in a normally-off state. This is because the acceptor impurity density of the fourth semiconductor layer 45 was lowered and the film thickness of the third semiconductor layer 44 was further increased. However, since the thickness of the fourth semiconductor layer 45 is increased, this layer is not completely depleted, and thus a normally-on state is realized in the fourth semiconductor layer 45. The bulk holes in the semiconductor layer 45 are responsible for conducting the load. This is shown in Fig. 4 (b).
It was shown to. FIG. 4 (b) shows an energy band diagram in the thermal equilibrium state under the surface of the fourth semiconductor layer 45 of the resistance on the load side. Carrier holes are represented by ◯. Therefore, in FIG. 4 (a), an E-FET for controlling the conductivity of the two-dimensional hole layer 30 and a current saturation type resistor using the conductivity of carrier holes in the fourth semiconductor layer 45 are used. ER type inverter circuit configuration can be realized.

The feature of this embodiment is that semiconductor elements that control carrier holes traveling in two different semiconductor layers are integrated on the same substrate in principle, and, for example, the degree of freedom in design regarding the current driving capability of the load of the inverter circuit is increased. To improve the integration degree and performance of the semiconductor integrated device. Also in this example, variations in V _T and gm in the plane of the 2-inch substrate were extremely small.

Further, in this embodiment, by providing a control electrode, for example, a shot electrode made of Al, between the electrodes 48 and 47, it is possible to control the conductivity of the channel on the load side. In this case, the E-FE
An inverter circuit composed of T and D-FET can also be realized.

Further, both the two-dimensional hole layer formed at the heterojunction interface between the first and second semiconductor layers 42 and 43 and the bulk holes in the fourth semiconductor layer 45 may be used as the load side conduction carriers. It is possible. In this case, ohmic electrodes 48 and 49
Must be electrically connected to both the fourth semiconductor layer 45 and the two-dimensional hole layer.

It is obvious that the contents described in the first, second and third embodiments can be applied to the present invention as they are in principle.

As described above, according to the present invention, the date threshold voltage V _T of the semiconductor integrated device having the crystal structure according to the design is set to a desired value at the time of crystal growth. There is almost no variation in V _T and other element characteristics due to the above, and there is an effect that the degree of freedom in selecting constituent elements is expanded. Further, since it is almost a planar type, it also has an effect that element isolation can be easily performed. According to the present invention, a high performance and highly reliable ultra high speed semiconductor integrated device can be realized, and the effect of the present invention is extremely great.

[Brief description of drawings]

1 (a), 2 (a), 3 (a) and 4 (a) are schematic sectional views showing an example of a basic structure of a semiconductor integrated device of the present invention, FIG. (B) and FIG. 1 (c), second
FIG. 2 (b), FIG. 2 (c), FIG. 3 (b) and FIG. 4 (b) are respective energy band diagrams. 11, 21, 31, and 41 ... High-resistance substrate, 12 and 32 ... High-purity or p-type first semiconductor layer, 22 and 42 ... High-purity or n-type first semiconductor layer, 13 and 33 ... n-type second semiconductor layer, 23 and 43 ... p-type second semiconductor layer, 14 and 34 ...
p-type third semiconductor layer, 24 and 44 ... n-type third semiconductor layer, 15 and 35 ... n-type fourth semiconductor layer, 25 and 45 ...
... P-type fourth semiconductor layer, 16,18,19,26,28,29,36,38,3
9,46,48 and 49 ... Ohmic electrodes, 17,27,37 and 47
...... Control electrode, 20 …… two-dimensional electron layer, 30 …… two-dimensional hole layer, E _F …… Fermi level, E _C …… energy level at the bottom of the conduction band, E _V …… top of the valence band Energy levels of Vbi ...
… Built-in voltage of the second semiconductor layer, Vin …… Potential from the Fermi level at the interface between the second and third semiconductor layers in thermal equilibrium, V _T …… Gate threshold voltage, ΔE _C …… Energy difference at the bottom of the conduction band between the first and second semiconductor layers, δ
The difference between the energy at the bottom of the conduction band of the first semiconductor layer and E _F.

Claims (4)

[Claims] 1. A high-purity or p-type first semiconductor layer, an n-type second semiconductor layer smaller than the electron affinity of the first semiconductor, and a p-type third layer on a high-resistance substrate. Semiconductor layers are sequentially provided, and at least one semiconductor layer is provided on the third semiconductor layer.
At least one first control electrode is provided, and the first control electrode is sandwiched between the first control electrode and the first control electrode, and the first control electrode is electrically connected to a channel region formed at a junction interface between the first semiconductor layer and the second semiconductor layer. Two first and second ohmic regions are provided, and an n-type fourth semiconductor layer is provided on the third semiconductor layer facing the first control electrode with respect to at least one of the second ohmic regions. And at least one third ohmic region electrically connected to the channel region and a second control electrode between the second and third ohmic regions on the fourth semiconductor layer. A semiconductor integrated device characterized in that zero or more are provided. 2. A high-purity or n-type first film on a high-resistance substrate.
A semiconductor layer, a p-type second semiconductor layer larger than the sum of electron affinity and energy gap of the first semiconductor, and an n-type third semiconductor layer are sequentially provided, and the third semiconductor layer At least one first control electrode is provided on the layer, and a channel region electrically formed at a bonding interface between the first semiconductor layer and the second semiconductor layer with the first control electrode interposed therebetween is electrically connected to the channel region. At least two first and second ohmic regions connected to each other, and at least one of the second ohmic regions is provided on the third semiconductor layer facing the first control electrode. A fourth semiconductor layer is provided, and at least one third semiconductor layer electrically connected to the channel region is provided on the fourth semiconductor layer.
And at least two second control electrodes are provided between the ohmic region and the second and third ohmic regions. 3. A high-purity substrate, a high-purity or p-type first semiconductor layer, an n-type second semiconductor layer smaller than the electron affinity of the first semiconductor, and a p-type third semiconductor layer. Semiconductor layers are sequentially provided, at least one first control electrode is provided on the third semiconductor layer, and the first control electrode is sandwiched between the first control electrode and the third control layer.
At least two first and second ohmic regions electrically connected to a channel region formed at a junction interface between the first semiconductor layer and the second semiconductor layer are provided, and at least one first ohmic region is provided. For the second ohmic region, an n-type fourth semiconductor layer electrically connected to the second ohmic region is provided on the third semiconductor layer facing the first control electrode. A second control electrode between at least one third ohmic region electrically connected to the fourth semiconductor layer and the second and third ohmic regions on the fourth semiconductor layer; A semiconductor integrated device characterized in that at least one is provided. 4. A high-purity or n-type first semiconductor layer and a p-type second semiconductor layer, which is larger than the sum of electron affinity and energy gap of the first semiconductor, on a high-resistance substrate. , N-type third semiconductor layers are sequentially provided, and
Providing at least one first control electrode on the semiconductor layer of
The first semiconductor layer and the second semiconductor layer are sandwiched by the first control electrode.
A p-type fourth semiconductor layer electrically connected to a channel region formed at a junction interface with the semiconductor layer, and electrically connected to at least the fourth semiconductor layer on the fourth semiconductor layer. And at least one third ohmic region connected to
And zero or more second control electrodes are provided between the third ohmic region and the third ohmic region.