JPH0695569B2 - Gate array LSI device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate array LSI device, and more particularly to a memory-equipped gate array LSI device having a memory circuit dedicated area and a bulk.

(Prior Art) Conventionally, a memory-equipped gate array equipped with a memory circuit such as a random access memory (hereinafter simply referred to as RAM)
In the LSI device, as a method of realizing the memory circuit,
(1) A method for realizing peripheral circuits such as a memory mel and address register, a write amplifier, a sense amplifier using a basic cell of the same kind as a basic cell for forming a logic circuit, and (2) a bulk for a memory cell. A method has been used in which the peripheral circuit of the memory is prepared in a wiring channel region provided between the basic cell columns for the logic circuit, and the peripheral circuit of the memory is realized by a basic cell common to the logic circuit.

However, in such a conventional method, since the logic circuit portion and the memory circuit portion are mixed, the arrangement determination process and wiring of each basic cell and the like become extremely complicated,
There is a problem in that the utilization efficiency of the basic cells and the like decreases and the area occupied by each circuit increases. Further, in particular, in the above method (2), since the memory bulk is arranged under the wiring region between the basic cells for the logic circuit, there is a disadvantage that the wiring capacity increases and the operation speed becomes slow. there were.

(Problems to be Solved by the Invention) In view of the above-mentioned problems in the conventional type, the present invention simplifies the layout determination process and wiring of each basic cell and the like in a memory-equipped gate array LSI device, and mounts each circuit. It is intended to improve the density and prevent a decrease in operating speed due to an increase in wiring capacitance and the like. Another object of the present invention is to easily realize a memory circuit of arbitrary capacity in a gate array LSI device.

(Means for Solving the Problems) In order to solve the above problems, according to the present invention, there are provided one or a plurality of logic blocks each having a plurality of logic circuit cells, and at least one memory block, and , The memory block includes a first memory cell
A first basic memory block having a memory cell region and a first peripheral circuit, a second memory cell region including a plurality of memory cells, and a second
A second basic memory block having a peripheral circuit, and the first basic memory block and the second basic memory block are adjacent to each other on the first side and have a mirror image relationship. And the first memory cell region and the second memory cell region are adjacent to each other on the first side,
Bit lines are connected to each other, and the first peripheral circuit and the second peripheral circuit are both formed along the sides of the first and second basic memory blocks other than the first side. And all the memory blocks and all the logic blocks have substantially the same shape, and these blocks are adjacent to each other. It

(Operation) By using the memory block as a dedicated area for realizing a memory circuit by using the above means, it is possible to realize a memory circuit of the same capacity in a smaller area than the conventional one. Become. Further, the layout determination and wiring of each circuit element are simplified, and the wiring capacitance can be reduced. Furthermore, by appropriately combining adjacent basic memory blocks that are mirror images of each other, it is possible to easily realize a memory circuit of arbitrary capacity.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit arrangement on a semiconductor chip of a gate array LSI device according to an embodiment of the present invention. The device shown in FIG. 1 has two logic blocks 2-1 and 2-2 and two memory blocks 3-1 and 3-3 on the semiconductor chip 1, and further has peripheral circuits around these respective circuit blocks. An input / output buffer circuit 4 is provided. Each of the logic blocks 2-1 and 2-2 has a basic logic cell row 5 in which a plurality of basic logic cells 5a are arranged, and the area around these basic logic cell rows 5 is a logic wiring area 6. used. Each memory block 3-1 and 3
-2 includes, for example, four basic memory blocks, and the area around each basic memory block is used as a memory wiring area 8. Furthermore, logic blocks 2-1 and 2
-2 and the areas around the memory blocks 3-1 and 3-2 are used as wiring areas between these circuit blocks and the input / output buffer circuit 4. As a basic cell,
For example, those described in JP-A-54-93375 are used.

In the gate array LSI device of FIG. 1, a desired logic circuit is realized by appropriately connecting each basic cell in each logic block 2-1 and 2-2 with aluminum wiring or the like, and each memory block 3- A memory circuit having a desired capacity is formed by using each of the basic memory blocks 7 in 2, 3-1 individually or in combination.

FIG. 2 shows a gate array LS according to another embodiment of the present invention.
I device. In the figure, the device comprises three logic blocks 2-1, 2-2, 2-3 and one memory block 3-1 on a semiconductor chip 1.

As described above, in the gate array LSI device according to the present invention, the number of logic blocks and memory blocks can be set to any value. For example, FIG. 3 (a)
It is also possible to provide one logical block 2-4 and one memory block 3-3 as shown in FIG. 2, and two logical blocks 2-5, 2-5, as shown in FIG. 2
It is also possible to provide -6 and one logic block 3-4.

FIG. 4 shows the structure of a basic memory block included in the memory block in each of the above-mentioned embodiments. In the figure, 10 is a memory cell array having a configuration of, for example, 32 rows × 48 columns, and 11 is a control circuit including a clock buffer, a memory control signal circuit, and the like. Memory cell array 10
A write amplifier 12, a sense amplifier 13, a test circuit 14, and the like are arranged along one side. In addition, the write word line buffer 15 along the other side of the memory cell array 10,
Peripheral circuits such as the first address decoder 16, the second address decoder 17, the first address register 18, the second address register 19 and the like are arranged. The address decoder and the address register are provided in two systems so that a so-called dual port type memory circuit can be configured. Further, the wiring in the memory block is also made into a master slice, and a part of the wiring is not provided, so that a memory other than 32 rows × 48 columns can be configured.

Next, how the above-mentioned basic memory block 7 is arranged in each memory block will be described.
For simplification of the drawing, each circuit portion of the basic memory block 7 is now referred to as a memory cell array portion MCA as shown in FIG.
A control circuit portion C including a clock buffer and a memory control signal circuit; a row side peripheral circuit RW including a row decoder and an address register; and a column side peripheral circuit CLM including a write amplifier, a sense amplifier, a column decoder and the like. Divide into blocks and think.

FIG. 6 shows an arrangement of basic memory cell blocks in each of the memory blocks 3-1 and 3-2 in the gate array LSI device of FIG. As shown in FIG. 6, for example, the memory block 3-1 includes four basic memory blocks. Of these four basic memory blocks, two adjacent basic memory blocks 7 and 7'are The memory cell arrays MCA are arranged so as to be adjacent to each other. In the basic memory block 7 ′, the portion of the circuit C including the row side peripheral circuit RW, the column side peripheral circuit CLM, the clock buffer, etc. is arranged in a mirror image relationship with the basic memory block 7. That is, in FIG. 6, each basic memory block 7'is configured in a mirror image relationship with respect to the adjacent basic memory block 7 with the adjacent line as the center. Also in the other memory block 3-2, two of the four basic memory blocks are adjacent to each other,
Moreover, the circuit elements of the adjacent basic memory blocks are arranged in a mirror image relationship with each other. Each basic memory block is arranged such that the row-side peripheral circuit is located on the boundary line 20 side with the logic block.

FIG. 7 shows how a memory circuit, that is, a memory macro, is constructed by using the basic memory block as described above. 7 (a) and 7 (b) each have 2
3 shows a memory macro configured using a number of basic memory blocks. FIG. 7A shows, for example, two basic memory blocks 7 arranged on the side closer to the logical block among the basic memory blocks of the memory block 3-1 in FIG.
And 7 '. In this case, the low-side peripheral circuits RW of the adjacent basic memory blocks 7 and 7 '
The memory cell array MCA is connected to each other to form a memory circuit having a capacity double that of one basic memory block. Further, the control circuit portion C such as the column side peripheral circuit CLM and the clock buffer is of the basic memory block 7 and not of the basic memory block 7 '. The area 21 is used as a wiring area for input / output signals of the basic memory block.

FIG. 7 (b) shows a memory macro constituted by using two basic memory blocks 7 and 7'located on the side far from the logical block in the memory block 3-1 etc. of FIG. Even in this case, each basic memory block 7
And 7'low side peripheral circuit RW and memory cell array
The MCAs are connected to each other to form a memory circuit having a capacity double that of the basic memory block. In the basic memory block 7 ', only the low-side peripheral circuit RW and the memory cell array MCA are used, and the other circuit parts are those of the basic memory block 7. Area 21 is the seventh
It is used as a wiring area for input / output signals of the basic memory block as in the case of FIG.

FIGS. 7 (c) and 7 (d) show an example of a memory macro configured by using one basic memory block 7 arranged on the side closer to the logical block and on the side farther from the logical block.

FIG. 8 shows the arrangement of memory macros in a memory block. FIG. 8 (a) shows that a memory macro (hatched portion) is formed by using one basic memory block on the side closer to the logic block. In the memory block on the right side of FIG. And one basic memory block on the far side is used. Further, in the memory block on the left side of FIG. 8B, a memory macro is configured by using two basic memory blocks near the logic block, and in the memory block on the right side of FIG. By combining the blocks, a memory macro having a capacity four times as large as one basic memory block is configured.

(Effect of the invention) As described above, according to the present invention, since the memory circuit is realized by the dedicated bulk, the memory having the same capacity as that of the conventional method in which the memory circuit is configured by using the logic basic cells or the like is used. The circuit can be realized in a smaller area. Further, since the logic circuit portion and the memory circuit portion do not coexist, the wiring can be simplified and the reduction of the operation speed due to the wiring capacitance or the like can be prevented. Further, since each memory block is composed of a plurality of basic memory blocks and the constituent circuits of the adjacent basic memory blocks are arranged in a mirror image relationship with each other, it is possible to easily realize a memory circuit of an arbitrary capacity, and Wiring is not complicated and operation speed is not reduced.

[Brief description of drawings]

1 and 2 are plan views showing the arrangement of each circuit block on a semiconductor chip of a gate array LSI device according to an embodiment of the present invention, and FIGS. 3 (a) and 3 (b) are memory blocks. FIG. 4 is an explanatory diagram showing another arrangement mode with respect to the logic block, FIG. 4 is an explanatory diagram showing details of each constituent circuit in the basic memory block, and FIG. 5 is an explanatory diagram showing an outline of each constituent circuit in the basic memory block. FIG. 6 is an explanatory diagram showing the arrangement of basic memory blocks in each memory block in the gate array LSI device of FIG. 1,
7 (a) to 7 (d) are explanatory diagrams showing the configuration of the memory macros, and FIG. 8 is an explanatory diagram showing an example of arrangement of the memory macros in each memory block. 1: semiconductor chip, 2-1, 2-2, ..., 2-6: logic block,
3-1, 3-2, ..., 3-4: memory block, 4: input / output buffer circuit, 5: basic cell row for logic, 6: wiring area for logic, 7,
7 ': basic memory block, 8: memory wiring area, 10: memory cell array, 11: control circuit, 12: write amplifier, 1
3: Sense amplifier, 14: Test circuit, 15: Write word line buffer, 16, 17: Address decoder, 18, 19: Address register, 20: Boundary line on logical block side, 21: Input / output signal wiring area.

Claims (1)

[Claims] 1. A first memory cell region comprising one or a plurality of logic blocks each having a plurality of logic circuit cells, and at least one memory block, the memory block comprising a plurality of memory cells. A first basic memory block including a first peripheral circuit, a second memory cell region including a plurality of memory cells, and a second
A second basic memory block having a peripheral circuit, and the first basic memory block and the second basic memory block are adjacent to each other on the first side and have a mirror image relationship. And the first memory cell region and the second memory cell region are adjacent to each other on the first side,
Bit lines are connected to each other, and the first peripheral circuit and the second peripheral circuit are both formed along the sides of the first and second basic memory blocks other than the first side. And all of the memory blocks and all of the logic blocks have substantially the same shape, and these blocks are adjacent to each other.