JPH0697392B2 - Image display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device, and more particularly, to a dot map type screen memory having a storage element corresponding to one dot for each image displayed on a display. About writing.

[Conventional technology]

In the conventional image display device of this type, the process of partially changing the dot data stored in the screen memory is performed by, for example, a central processing when transferring the dot data of the character pattern stored in the character generator to the screen memory. The device (hereinafter referred to as CPU) (1) reads out the dot data already written in the relevant part of the screen memory and takes it into the CPU.

(2) Shift the dot data to be added to the display bit position.

(3) A non-rewritten portion is read from the original dot data stored in the CPU by a mask process, and only a write bit is extracted from the dot data to be added after the shift by a mask process. Create a new write dot data by taking the sum.

(4) Write new write dot data to the corresponding portion of the screen memory.

The processing step was called. However, the CPU is originally slow in bit processing, and especially the data shift of multiple bits is 1
There is a drawback that the number of processing steps increases because the processing is performed by repeating the command step of bit shift a plurality of times.

In order to improve such a defect, a memory control system has been proposed in which data shift is performed by using a shift register, as described in JP-A-59-90156.
However, even in this method, since the shift operation is a shift of one bit with one clock, it takes time for a plurality of clocks to shift a plurality of bits of data.

On the other hand, the character pattern stored in the character generator has a 24 x 24 dot matrix structure,
When the processing unit of 16 bits is a word unit of 16 bits, the method of reading the dot data from the charactor generator is divided into 16 bits on the right side and 8 bits on the left side, and 8 bits on the left side are invalid. It is common to add data and perform word access.

[Problems to be solved by the invention]

In this method of accessing the character generator, the dot data of the character pattern is read out, and the data shift processing described above is performed to write new dot data to the screen memory. In such a case, the reading of the dot data from the character generator has to be executed in a large number of times, which causes a problem that the display speed becomes slow.

Therefore, an object of the present invention is to further increase the display speed by further increasing the speed of the dot data shift processing and by continuing the reading of the dot data from the character generator.

[Means for solving problems]

In order to solve this problem, the present invention divides the dot data of a 24 × 24 dot matrix into three sets in byte units in the scanning line direction in the charactor generator.
A memory for parallelly storing 24 continuous addresses in the arrangement direction of the scanning lines for all dot data in one scanning line direction is provided, and the screen memory is configured to have an address order in the arrangement direction of the scanning lines. Memorized by Rakuta generator
A charactor generator read control circuit for reading out 24 × 24 dot data in 16-bit one-word units from the CPU side according to the instruction from the CPU, either the left 16-bit or the right 16-bit in the scanning line direction. The barrel shifter that shifts the dot data of the given image by the bit amount according to the shift amount command value given by the CPU, and the CPU
The mask controller that generates the mask data that limits the write range of the dot data given from the side, and the new write data by combining the dot data read from the screen memory and the dot data output from the barrel shifter according to the mask data. And a light controller for creating.

[Action]

When accessing the charactor generator, the CPU outputs a read address signal with a string instruction, and sequentially accesses either the left 16-bit or right 16-bit group of the memory in the arrangement direction of the scan lines in the dot pattern. The dot data is fetched in bit units, and the corresponding portion is output together with this address signal so as to be written in the screen memory. The barrel shifter immediately shifts this dot data by the bit amount according to the shift amount command value from the CPU and outputs it. On the other hand, the write controller creates new write data by synthesizing the dot data read from the screen memory by the address signal and the dot data output from the barrel shifter according to the mask data from the mask controller. Write to. Such processing is performed on the left side of the memory read by the string instruction.
By sequentially executing 24 words for one side of 16 bits or 16 bits on the right side, and then for the other side in the same manner, writing of dot data in the image pattern area for one character is completed.

〔Example〕

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of an image display device according to the present invention. Reference numeral 11 denotes a central processing unit (hereinafter referred to as CPU) that controls the display function unit, and for example, Intel's 8086 or the like is suitable. Reference numeral 12 is an interrupt controller that gives an interrupt signal to the CPU 11 and branches the program in response to an external event. Reference numeral 13 is a program memory for storing programs executed by the CPU 11 and data processing information. Reference numeral 14 is a character generator (hereinafter referred to as CG) that stores a character pattern to be displayed in a dot matrix.
And is generally composed of a ROM. Reference numeral 19 is a CG read control circuit for changing the right side and the left side of the read data from the CG 14. Reference numeral 15 is an interface circuit for receiving a command from the host CPU located above the display function unit. 16
Is a graphic display controller (hereinafter referred to as GDC) which generates an address signal for sequentially reading the contents of the screen memory 20 and generates a synchronizing signal for controlling the CRT monitor 24. Reference numeral 17 is a control circuit that generates a timing signal for the screen memory 20 and its peripheral circuits.
Reference numeral 18 denotes a screen memory control circuit that supports drawing processing by the CPU 11 in synchronization with a write signal from the CPU 11 to the screen memory 20. Reference numeral 20 is a bit map type screen memory in which a storage element for storing one dot image of the dot tomato image displayed on the screen of the CRT monitor 24 exists corresponding to the screen, and is composed of a dynamic RAM. 21 is GDC 16
It is a synchronizing circuit for synchronizing the horizontal and vertical synchronizing signals from the and the video signal from the shift register 23. 22 is a latch for temporarily storing the image dot data read from the screen memory 20, 23 is a shift register for receiving the image dot data stored in the latch 22 and converting the image parallel data into parallel serial data, and 24 is a video signal and It is a CRT monitor that displays a screen in response to a synchronization signal. 51-1, 51-2 are transceivers / receivers located between the CPU bus signal line a and the GDC 16 or the screen memory control circuit 18 for buffering signals. 52-1, 52-2, 52-3 are multiplexers, which select and output a set of signals from the input signal lines.

Details of the screen memory control circuit 18, which has an important function as a component of the present apparatus, will be described with reference to FIG.

In FIG. 2, 18-1 is a data latch for holding data from the CPU 11. 18-2 is a barrel shifter and data latch 18
Shifts the data from -1 in the specified bit units.
A write controller 18-3 generates write data to the screen memory 20. Reference numeral 18-4 is an operation register, which holds an operation command for image dot data in bit units to be given to the write controller 18-3. 18-5 and 18-6 are bit registers, which hold the designated value of the data shift amount in the barrel shifter 18-2. 18-7 holds the bit width command value for write operation with the mask register. Reference numeral 18-8 is an arithmetic unit (hereinafter referred to as ALU), which calculates the shift amount to be shifted by the barrel shifter 18-2 based on the bit shift amount held in the bit registers 18-5 and 18-6. Reference numeral 18-9 is a mask controller, which outputs mask data for masking the writing of the write data from the CPU 11 to the screen memory 20 in accordance with the bit width command value held in the mask register 18-7. Reference numeral 18-10 is a control circuit for controlling these operation timings.

Next, access to the screen memory 20 will be described. The screen memory 20 is operated by the read modifier eyelight when the CPU 11 writes. That is, CPU1
The dot data from 1 is temporarily stored in the data latch 18-1, processed by the barrel shifter 18-2, and input to one input terminal of the write controller 18-3. The image dot data of the designated address of the screen memory 20 is read and given to the other input terminal of the write controller 18-3. The above two inputs are logically operated bit by bit on the basis of the instruction stored in the operation register 18-4 and written to the designated address of the screen memory 20.

Next, the address configuration of the screen memory 20 will be described with reference to FIG.

The video signal is formed in raster units as a series of image dots. That is, the reading by the GDC16 for the screen refresh is in 16-bit units from the beginning of the screen, serially converted in order from the MSB, and next to the LSB.
16-bit MSBs are connected.

When the CPU 11 handles a 24 × 24 bit character pattern, the depth is 3 bytes in the raster scan direction and 24 bytes in the raster arrangement direction. CPU1
The Intel 8086 used as 1 is provided with a string instruction for repeating sequential addresses. According to this string instruction, the transfer of data from the source address specified in the predetermined register to the destination address in the specified number of words or bytes is performed with the minimum instruction step and the minimum processing time. In order to obtain the maximum effect in this processing method, it is effective to take a large number of transfers at one time. Focusing on this point, the screen memory 2 seen from the CPU 11
Addresses of 0 should be aligned in the raster order.

FIG. 3 shows the address configuration of the screen memory 20 realized based on the above points.

Next, CG14 will be described. In this embodiment, the dot data of the character pattern is stored in the ROM as shown in FIG. That is, the dot data of the pattern that constitutes one character is divided into 3 sets in byte units in the scanning line direction, and the left 24 bytes, the center 24 bytes, and the right 24 bytes are vertically connected and divided into 3 ROMs. It has been stored.

FIG. 5 shows the CPU11 from the CG14 in which the patterns are stored in the three ROMs by dividing them by 8 bits in the scanning direction.
2 shows a detailed configuration of the CG read control circuit 19 for controlling the data read in word units.

In FIG. 5, CG14 has three ROMs 14-1 to 14-3 each having a data bus of 8 bits. Numerals 19-1 to 19-4 are transceivers which perform buffering when outputting the dot data read from the ROMs 14-1 to 14-3 to the CPU data bus. Here, when the left word of CG14 is accessed from CPU11, transceivers 19-1 and 19-2 are
It is enabled by the data select circuit 19-5,
The left 16 bits of the character pattern dot matrix are output. Similarly, if the right word is accessed,
The right 16 bits are output.

FIG. 6 clearly shows the relationship between addresses and dot data when the character pattern dot matrix of the Chinese character “Kan” is read by the CG read control circuit 19 of FIG.
It is possible to read 8 bits in the scanning direction at the central portion in duplicate in either the left word access or the right word access.

Note that FIG. 7 shows the relationship between the read address and the dot data in the conventional case where the CG read control circuit 19 is not provided. When the left word of the character pattern dot matrix is accessed, the left 8 bits of the 16 bits are read as invalid data.

Next, write the image dot data to the screen memory 20, and
The operation of displaying the contents of the screen memory 20 on the CRT monitor 24 will be described.

The image is displayed by writing dot data of "1" (bright spot) or "0" (dark spot) to the screen memory 20 in bit units. The character is displayed on the screen by writing the dot data of the character pattern designated by the CG 14 to the word address on the screen memory 20 to be displayed using the string command.

The bit positions of the character pattern dot data when the data is read from the CG14 are arranged in word units as shown in FIG. Therefore, for example, "Kanji" as shown in Fig. 8
In the case of displaying the character example on the CRT monitor 24, since the access unit to the screen memory 20 is a word, the left end bit position of the second character "character" is shifted by 8 bits, and a state of inconsistency occurs. At this time, in the structure without the screen memory control circuit 18, in the character pattern dot data transfer process from the CG 14 to the screen memory 20, the bit shift process must be performed every 1 word transfer. That is, 8086
Even in the CPU 11 of the system, the memory movement by the string instruction, which is strong against the above word transfer, cannot be used.

In the present embodiment, since the screen memory control circuit 18 shown in FIG. 2 is provided, the barrel shifter 18-2 performs bit shift processing in place of the CPU 11. In addition, since the barrel shifter 18-2 rotates the word data, the data to be shifted and written to the next address is
The mask controller 18-9 masks each bit to prohibit writing. By the above processing, the character pattern "character" can be displayed by two word string commands.

Further, when displaying the character pattern of the first character "Kan" shown in FIG. 8, the read data from the CG14 is divided into 8 bits on the left side and 16 bits on the right side as shown in FIG. If the screen memory control circuit 18 is used to develop the characters in the screen memory 20, the characters are divided into three areas A, B and C as shown in the lower part of FIG. I had to do the word writing process. However, if the CG read control circuit 19 shown in FIG. 5 in this embodiment is used and the CG read mode as shown in FIG. 6 is adopted, as shown in the lower part of FIG. The data can be divided into two areas, D and E, and can be displayed by word writing processing twice.

As described above, by combining the screen memory control circuit 18 and the CG read control circuit 19 of this embodiment, it is obvious that the dot data of the character pattern can be displayed at a higher speed than in the conventional case.

Further, in the above-described embodiment, the effect of the string instruction is illustrated using the 8086 as the CPU 11, but the same effect can be exerted in the DMA transfer between the memories. Therefore, 8086
It can be realized by CPUs other than the above.

〔The invention's effect〕

According to the present invention, by supplementing the processing for reading the dot data of the character pattern from the character generator and writing it to any position of the screen memory and displaying it at any position on the display screen, the CPU speeds up. It can be used in a versatile state. Further, not only the display of the character pattern but also the writing of the figure into the memory in bit units becomes faster when drawing the figure.

As described above, the display processing time can be shortened in the display device using the CPU, and the operability is improved.

[Brief description of drawings]

1 is a block diagram of a circuit of a display device according to the present invention, FIG. 2 is a block diagram showing details of a screen memory control circuit, and FIG. 3 is an explanatory diagram showing an address configuration of a screen memory according to the present invention. FIG. 4 is an explanatory view showing the accommodation of character pattern dot data in the character generator, FIG. 5 is a block diagram showing the details of the character generator read control circuit, and FIG. 6 is the character pattern dot data according to the present invention. FIG. 7 is an explanatory view showing the relationship between the address and the data when the data is read, FIG. 7 is an explanatory view showing the relationship between the address and the data when the character pattern dot data in the conventional case is read, and FIG. 8 is the present invention. It is explanatory drawing which shows the data of the screen memory explaining a character display process. 11 …… CPU, 14 …… Character generator, 18 …… Screen memory control circuit, 18-2 …… Barrel shifter, 18-3 …… Light controller, 18 …… Mask controller, 19 ……
CG readout control circuit, 20 …… screen memory, 24 …… CRT monitor.

Claims (1)

[Claims] 1. A character generator for storing dot data of a character pattern composed of a 24 × 24 dot matrix, and a display for displaying an image in a dot matrix.
A control is executed to read out dot data of a character pattern from a bitmap type screen memory having a storage element corresponding to one dot to a dot of an image displayed on this display and the character generator, and store this in the screen memory. In an image display device comprising a CPU and a display control circuit for reading the dot data stored in the screen memory and giving it to the display, the character generator outputs 24 × 24 dot data in byte units in the scanning line direction. And a memory for storing all the dot data in one scanning line direction in parallel with 24 consecutive addresses in the scanning line arrangement direction, and the screen memory has an address order in the scanning line arrangement direction. And the dot data of 24 × 24 dots stored in the character generator in the scanning line direction. A character generator read control circuit that reads either 16 bits on the side or 16 bits on the right side in 16-bit units according to the instruction from the CPU, and the dot data of the image given from the CPU according to the shift amount command value given from the CPU. Barrel shifter that shifts only the amount of bits, a mask controller that generates mask data that limits the writing range of the dot data given from the CPU side, the dot data read from the screen memory and the dot data output from the barrel shifter are masked An image display device, comprising: a light controller for synthesizing according to data to create new writing dot data.