JPH0697658B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a high-concentration n-type and p-type doped layer under a silicide film having substantially equal junction depths. The present invention relates to a method of manufacturing a semiconductor device suitable for manufacturing.

[Background of the Invention]

Conventionally, as a method of forming a diffusion layer under a silicide film, as described in JP-A-59-88868, impurities are diffused through a refractory metal silicide film to form a diffusion layer on a silicon substrate under the silicide film. Method and JP-A-59-997
As described in No. 74, a method has been proposed in which impurities are ion-implanted at the interface of a refractory metal film / silicon substrate, and then heat treatment is performed to simultaneously form a refractory metal silicide film and a diffusion layer on a silicon substrate. ing.

However, in these methods, no consideration was given to making the doped layer under the silicide film shallow and making the junction depth of the n-type doped layer and the p-type doped layer the same. According to these methods, when an n-type doped layer and a p-type doped layer having the same junction depth are formed on the same substrate, an impurity having a small diffusion coefficient in the silicon substrate (for example, arsenic as the n-type impurity) is used. It is necessary to form the second doped layer with impurities having a large diffusion coefficient (for example, boron as a p-type impurity) after forming the first doped layer having a depth of 1.

Therefore, the first impurity introduction step and the first doping step for forming the first doped layer, and the second impurity introduction step and the second diffusion step for forming the second doped layer are performed. In addition, a two-step impurity introduction step and diffusion step are required. Further, in order to obtain the same junction depth, there are various combinations of the conditions of the first and second impurity introducing steps and the conditions of the first and second diffusion steps, which makes it very difficult to set the conditions. .

Further, in order to obtain a shallow junction depth of about 0.2 μm, the diffusion layer forming temperature of arsenic and boron cannot be raised by annealing for about 30 minutes using a conventional electric furnace. For example,
With annealing for about 30 minutes, the above temperature is limited to 1000 ° C or lower. Further, the temperature for obtaining the same junction depth differs by about 50 ° C. due to the difference in the diffusion coefficient of arsenic and boron in silicon. For example, the first diffusion layer is formed by diffusing arsenic at a predetermined temperature, and then the second diffusion layer is subjected to boron diffusion at a temperature lower by about 50 ° C. than the above arsenic diffusion temperature. A diffusion layer having a junction depth can be obtained.

The concentration of electrically active impurities strongly depends on the processing temperature,
For example, the higher the processing temperature, the higher the concentration, and the lower the processing temperature, the lower the concentration. For this reason, since the second diffusion temperature is lower than the first diffusion temperature, the active arsenic concentration of the first diffusion layer formed by arsenic diffusion at a relatively high temperature decreases during the second diffusion step. In addition, the active boron concentration is also suppressed to a low level.

As described above, according to the conventional method, it is difficult to form a highly active impurity concentration in a shallow junction of about 0.2 μm.
The concentration is limited by the solid solubility of each impurity determined by the processing temperature for forming the second diffusion layer. As a result, the resistance of each diffusion layer cannot be made sufficiently low.

[Object of the Invention]

An object of the present invention is to solve problems such as the large number of steps and the difficulty in setting conditions, which the above-mentioned conventional methods have, to easily set the steps and the conditions thereof, and to provide a high concentration (or It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of forming a shallow n-type doped layer and a p-type doped layer having a substantially same junction depth (low resistance).

[Outline of Invention]

The present invention is based on the novel finding that the above object can be achieved by satisfying the following sufficient conditions. That is, the first condition is to introduce impurities into the silicide film 4 only by ion implantation, as shown in FIGS. 1, (a) and (b). The reason is that when the implanted impurities 6 and 8 reach the silicon substrate 1 under the silicide film 4, generation of defects in the silicon substrate due to the implanted impurities, increase in depth of implanted impurity distribution due to channeling phenomenon, and The purpose is to prevent deterioration of controllability. That is, when ions are directly implanted into the silicon substrate, the junction depth is sufficiently shallow, and it becomes extremely difficult to form a good quality junction.

The second condition is to introduce an amount of impurities having a solid solubility or higher into the silicide film. The reason is as follows. In order to form a silicide electrode having a low contact resistance, it is desirable to make the concentration of electrically active impurities directly under the silicide film as high as possible, as shown in FIG. This is because the above amount of impurities is required. That is, high concentration n-type or p
In order to form the mold diffusion layer, it is necessary that the diffusion of impurities into the silicon substrate during the heat treatment is limited by the solid solubility of the silicon substrate. That is, the amount of impurities introduced into the silicide film must be equal to or higher than the solid solubility of impurities in the silicide so that a large amount of excess impurities having a solid solubility or higher in the silicide film diffuse to the silicon substrate side. When the amount of introduced impurities does not satisfy the above requirement, the active impurity concentration immediately below the silicide film is determined by the segregation coefficient of the impurities between the silicide film and the silicon substrate, so that a high active impurity concentration cannot be expected. .

Further, the third condition is that after the impurities are introduced into the silicide film 4, the surface of the silicide film 4 is covered with the film 9 in which the diffusion of the impurities is slow, as shown in FIG. The reason is to prevent the impurities 6 and 8 from evaporating from the surface of the silicide film in which the impurity diffusion is very fast, and avoid the invalidation of the limitation of the impurity introduction amount under the second condition. . For example, as shown in FIG. 3, when the film is not provided, the active impurity concentration is extremely lowered as compared with the case where the film is provided. Therefore, the diffusion process needs to be performed by forming the film on the surface of the silicide film. is there.

Finally, the fourth condition is that the diffusion of impurities from the silicide film into the silicon substrate is performed at a high temperature for a short time.
The reason is that the diffusion temperature is set to a high temperature of 1000 to 1200 ° C. and the diffusion time is set to a short time of about 5 to 60 seconds, so that each diffusion layer 10 can be formed as shown in FIG. 1 (d). The active impurity concentration of 11 can be increased to 1-3 × 10 ²⁰ cm ^-3 ,
This is also because the junction depth of each of the diffusion layers 10 and 11 can be arbitrarily selected within the range of about 0.2 μm or less. That is, since the contact resistance of the silicide electrode can be lowered by setting the active impurity concentration to the above range,
As shown in FIG. 2, the resistance of the source / drain regions can be kept stable and low. Further, as shown in FIG. 4, in a MOS transistor having a gate length L of about 1 μm, when the gate is processed with an accuracy of 10% (the gate processing variation ΔL with respect to the gate length L).
Is ΔL = 0.1 L), in order to suppress the threshold voltage fluctuation due to the variation of the gate length to 0.2 V or less,
It is necessary to make the junction depth about 0.2 μm or less, and this requirement can be easily achieved under the above conditions of the present invention.

Further, phosphorus can be used as the n-type impurity instead of arsenic.

Example of Invention

Hereinafter, as an embodiment of the present invention, the formation of a CMOS junction will be described with reference to FIGS.

A field oxide film 13 is formed on the n-type silicon substrate 12 having a substrate concentration of 1 × 10 ¹⁵ cm ^-3 by a normal LOCOS method to form a p-well diffusion layer 14 having a concentration of 1 × 10 ¹⁵ cm ^-3. A gate oxide film 15 having a thickness of 20 nm was formed, a tungsten film was formed as a gate electrode material, and then a gate electrode 16 was formed by a normal photoetching process (a).

Next, the gate electrode 16 is covered with a silicon oxide film 17 (b),
The tungsten silicide film 18 was selectively formed at 0.1 nm only on the surface of the silicon substrate (c).

Next, using a normal photo-etching process, a photoresist film 19 having a thickness of 1 μm is formed only on the p-well diffusion layer 14, and using this photoresist film 19 as a mask, the silicide film 18 on the n-type substrate is subjected to implantation energy. = 20 keV, and implantation amount = 1 × 10 ¹⁶ / cm ² 20 boron was performed (d).

Next, after removing the photoresist film 19, a photoresist film 21 having a thickness of 1 μm is formed only on a portion other than the p-well diffusion layer 14, and implantation energy = 140 keV and implantation amount =
Arsenic 22 was implanted under the condition of 1 × 10 ¹⁶ / cm ² (e).

Then, after removing the photoresist film 21, a PSG (phosphorus glass) film 23 having a thickness of 0.5 μm is formed, and the heat treatment temperature = 1150.
By the heat treatment at ℃, heat treatment time = 20 seconds, the silicide film 18
Boron and arsenic implanted therein were diffused into a silicon substrate to form a p-type diffusion layer 24 and an n-type diffusion layer 25 (f). At this time, the p-type diffusion layer 24 and the n-type diffusion layer 25
Fig. 3 shows the distribution in the depth direction of the carrier. The surface concentration of each diffusion layer under the tungsten silicide film 18 is as high as 1 × 10 ²⁰ cm ^−3, and the junction depth is almost equal to about 0.2 μm. At this time, the layer resistances of the p-type and n-type diffusion layers are as low as 80Ω / □ and 40Ω / □, respectively.

According to this embodiment, it is possible to form conductive diffusion layers having different junction depths by a single diffusion process. Making the junction depths of the respective diffusion layers the same has the advantage that the effective gate length can be made equal for manufacturing CMOS transistors. Further, a diffusion layer having an arbitrary junction depth can be easily formed under the diffusion conditions. For example, the junction depth can be easily determined by determining the heat treatment temperature as shown in FIG. Furthermore, since the electrically active impurity concentration of each diffusion layer is high, the contact resistance between the silicide film and the diffusion layer can be reduced. In addition, the heat treatment conditions described in this embodiment are sufficient for performing the densification of the PSG film, and the above film (PSG film) can be used as the passivation film.

Further, according to the present embodiment, the electrically active impurity concentration of the diffusion layer under the silicide film can be set to 1 × 10 ²⁰ cm ⁻³ or more, so that the resistance of the source and drain regions is low and A stable value is obtained without depending on the variation in the impurity concentration. Furthermore, the junction depth can be controlled as shallow as within 20 nm (see Fig. 4), and the n and p diffusion layers can be made to have the same junction depth, so the characteristics of each element are stable with very little variation. It can be anything.

〔The invention's effect〕

According to the present invention, when manufacturing a semiconductor device having different conductivity type diffusion layers, the same junction depth can be obtained in one diffusion step for forming both p-type and n-type diffusion layers. Since the diffusion layer can be formed, the number of steps is reduced, and the heat treatment conditions for diffusion can be easily set. Further, under the heat treatment conditions of the present invention, the electrically active impurity concentration of the diffusion layer can be increased to about 2 to 5 times that of the conventional method, so that the total resistance of the respective silicide film diffusion layers can be reduced by the conventional method. It can be reduced from 1/2 to 1/3 compared to.

[Brief description of drawings]

FIG. 1 is a process diagram showing the outline of the present invention, FIG. 2 is a diagram showing the relationship between the active impurity concentration at the WSi ₂ silicide / Si substrate interface and the total resistance of the source / drain regions, and FIG. 3 is the active impurity concentration. Distribution diagram in the depth direction, FIG. 4 shows the relationship between junction depth and threshold voltage fluctuation, and FIG. 5 shows COMS using the present invention.
FIG. 6 is a process diagram of manufacturing a transistor, FIG. 6 is a depthwise distribution diagram of electrically active impurity concentration, and FIG. 7 is a relational diagram between the heat treatment temperature and the junction depth of the diffusion layer. 1,12 ... n-type silicon substrate, 2,14 ... p-well diffusion layer,
3,13,15,17 …… Silicon oxide film, 4,18 …… Tungsten silicide film, 5,7,19,21 …… Resist film, 6,20 …… Boron ion, 8,22 …… Arsenic ion, 9 ... film, 10,24
...... p-type diffusion layer, 11,25 …… n-type diffusion layer, 16 …… gate electrode, 23 …… PSG film, 26 …… carrier distribution of p-type diffusion layer, 27 …… carrier distribution of n-type diffusion layer .

Continuation of front page (51) Int.Cl. ⁵ Identification number Reference number in the agency FI Technical indication location H01L 27/092 29/784 (72) Inventor Tadashi Suzuki 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Hitachi Central Inside the laboratory (72) Inventor Masao Tamura 1-280 Higashi Koigakubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-59-105367 (JP, A)

Claims (2)

[Claims] 1. A step of forming a metal silicide film on a first region where a p-type region is to be formed and a second region where an n-type region is to be formed on the surface of a semiconductor substrate, and on the first region. A step of ion-implanting the formed metal silicide film and the metal silicide film formed on the second region with boron and arsenic or phosphorus having a solid solubility or higher; and, on the metal silicide film,
The step of forming a film having a diffusion coefficient of boron, arsenic, and phosphorus smaller than that of the silicide film of the above metal, and the temperature of 1000 to
Heat treatment is performed at 1200 ° C. for a time of 5 to 60 seconds to diffuse boron and arsenic or phosphorus in the metal silicide film into the first region and the second region, respectively, so that the junction depths are substantially equal to each other. A method of manufacturing a semiconductor device, comprising the step of forming equal p-type regions and n-type regions. 2. The junction depth of the p-type region and the n-type region is
The method for manufacturing a semiconductor device according to claim 1, wherein the thickness is 0.2 μm or less.