Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JPH0697691B2 - Semiconductor device - Google Patents
[go: Go Back, main page]

JPH0697691B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0697691B2
JPH0697691B2 JP1317281A JP31728189A JPH0697691B2 JP H0697691 B2 JPH0697691 B2 JP H0697691B2 JP 1317281 A JP1317281 A JP 1317281A JP 31728189 A JP31728189 A JP 31728189A JP H0697691 B2 JPH0697691 B2 JP H0697691B2
Authority
JP
Japan
Prior art keywords
annular region
guard ring
type
semiconductor layer
conductivity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1317281A
Other languages
Japanese (ja)
Other versions
JPH03177068A (en
Inventor
隆 濱名
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1317281A priority Critical patent/JPH0697691B2/en
Publication of JPH03177068A publication Critical patent/JPH03177068A/en
Publication of JPH0697691B2 publication Critical patent/JPH0697691B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置に関し、特にショットキー・バリ
ア・ダイオードの環状領域(ガードリング)の構造に関
するものである。
The present invention relates to a semiconductor device, and more particularly to the structure of an annular region (guard ring) of a Schottky barrier diode.

〔従来の技術〕[Conventional technology]

第3図は従来のショットキー・バリア・ダイオードのガ
ードリング構造の一例を示す断面図で、図において1は
p型半導体基板、2はこのp型半導体基板1上に堆積さ
れたp型半導体層、3はp型半導体層2上に堆積された
金属、4は上記p型半導体基板1内に形成されたn型の
ガードリング、5は絶縁膜、6は金属3に電位を与える
ための電極、7はガードリング4に電位を与えるための
電極である。
FIG. 3 is a sectional view showing an example of a guard ring structure of a conventional Schottky barrier diode, in which 1 is a p-type semiconductor substrate and 2 is a p-type semiconductor layer deposited on the p-type semiconductor substrate 1. 3 is a metal deposited on the p-type semiconductor layer 2, 4 is an n-type guard ring formed in the p-type semiconductor substrate 1, 5 is an insulating film, and 6 is an electrode for applying a potential to the metal 3. , 7 are electrodes for applying a potential to the guard ring 4.

次に動作について説明する。Next, the operation will be described.

第4図は第3図におけるガードリング4付近の拡大図で
あり、図において、9は空乏領域を表し、11はショット
キ接合周囲でのリーク電流を表している。同図(a)は
ガードリング4に与える正の電位+VGがある闘値電圧V
thより低い場合を示し、(b)はVthより高い場合を示
している。
FIG. 4 is an enlarged view of the vicinity of the guard ring 4 in FIG. 3, in which 9 represents the depletion region and 11 represents the leakage current around the Schottky junction. The figure (a) shows a threshold voltage V with a positive potential + V G given to the guard ring 4.
The case is lower than th , and (b) shows the case higher than V th .

同図(a)において、ガードリング4には正の電位が与
えられているためpn接合は逆バイアスされ接合部には空
乏領域9が形成されている。しかし、ガードリング4に
与える正の電位が小さい(+VG<Vth)ため、空乏領域
9の広がりが不十分であり、ショットキ接合周囲で発生
したリーク電流11はガードリング4と金属3の間を通っ
てp型半導体基板1へと流れてしまう。
In FIG. 4A, since a positive potential is applied to the guard ring 4, the pn junction is reverse biased and a depletion region 9 is formed at the junction. However, since the positive potential applied to the guard ring 4 is small (+ V G <V th ), the expansion of the depletion region 9 is insufficient, and the leak current 11 generated around the Schottky junction is generated between the guard ring 4 and the metal 3. Flow through to the p-type semiconductor substrate 1.

一方、同図(b)ではガードリング4に十分な正の電位
(+VG>Vth)を与えているため、ガードリング4と金
属3の間は空乏領域9で埋められている。このためリー
ク電流11は空乏領域9の高いポテンシャルに阻止され、
p型半導体基板1へと流れることができない。
On the other hand, giving the same figure (b) in sufficient positive potential to the guard ring 4 (+ V G> V th ), during the guard ring 4 and the metal 3 is filled with the depletion region 9. Therefore, the leak current 11 is blocked by the high potential of the depletion region 9,
It cannot flow to the p-type semiconductor substrate 1.

なお、上記従来例においてp型とn型が逆の構造である
半導体装置においても、電位の正負を入れ換えれば同様
に成り立つものである。
Even in the semiconductor device in which the p-type and the n-type are opposite to each other in the above conventional example, the same holds if the positive and negative potentials are switched.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

従来のショットキー・バリア・ダイオードは以上のよう
に構成されており、p型半導体層2には絶縁膜5との境
界近傍において結晶格子のミスフィットによる結晶欠陥
や局在準位が多数存在しており、この境界近傍ではガー
ドリング4とp型半導体層2は正常なpn接合を形成して
いない。したがってガードリング4に電位を与えガード
リングと半導体層2のpn接合が逆バイアスになるように
しても、絶縁膜5との境界近傍において、ガードリング
4とp型半導体層2の周囲部分の間にリーク電流が発生
し、さらに金属3へ流れるという問題点があった。
The conventional Schottky barrier diode is configured as described above, and in the p-type semiconductor layer 2, many crystal defects and localized levels due to misfit of the crystal lattice exist near the boundary with the insulating film 5. Therefore, near this boundary, the guard ring 4 and the p-type semiconductor layer 2 do not form a normal pn junction. Therefore, even if a potential is applied to the guard ring 4 so that the pn junction between the guard ring and the semiconductor layer 2 is reversely biased, between the guard ring 4 and the peripheral portion of the p-type semiconductor layer 2 in the vicinity of the boundary with the insulating film 5. There is a problem that a leak current is generated in the metal and further flows into the metal 3.

この発明は以上のような問題点を解決するためになされ
たものであり、絶縁膜近傍の半導体層の結晶欠陥や局在
準位に起因して生じる、ガードリングと金属の間のリー
ク電流を抑制することができる半導体装置を得ることを
目的とする。
The present invention has been made to solve the above problems, and prevents leakage current between a guard ring and a metal caused by a crystal defect or a localized level of a semiconductor layer near an insulating film. An object is to obtain a semiconductor device that can be suppressed.

〔課題を解決するための手段〕[Means for Solving the Problems]

この発明に係る半導体装置は、基板内に形成されたガー
ドリング主表面の、半導体層と絶縁膜との接触端同士が
当接する位置に沿って、半導体層と同じ導電型の環状領
域を形成するようにしたものである。
In the semiconductor device according to the present invention, an annular region having the same conductivity type as that of the semiconductor layer is formed along the position where the contact ends of the semiconductor layer and the insulating film contact each other on the main surface of the guard ring formed in the substrate. It was done like this.

〔作用〕[Action]

この発明においては、基板内に形成されたガードリング
主表面の、半導体層と絶縁膜との接触端同士が当接する
位置に沿って、半導体層と同一導電型の環状領域を形成
したから、半導体層とガードリング間のpn接合は完全な
ものとなり、ガードリングと金属の間のリーク電流を制
御することができる。
In the present invention, since the annular region of the same conductivity type as the semiconductor layer is formed along the position where the contact ends of the semiconductor layer and the insulating film contact each other on the guard ring main surface formed in the substrate, The pn junction between the layer and the guard ring is perfect and the leakage current between the guard ring and the metal can be controlled.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例によるショットキー・バリア
・ダイオードの断面図であり、第3図及び第4図と同一
符号は同一または相当部分を示し、4はp型半導体基板
1内に形成されたn型のガードリング、8はガードリン
グ4主表面に形成されたp型環状領域である。
FIG. 1 is a cross-sectional view of a Schottky barrier diode according to an embodiment of the present invention, in which the same reference numerals as those in FIGS. 3 and 4 indicate the same or corresponding portions, and 4 is inside a p-type semiconductor substrate 1. The formed n-type guard ring, 8 is a p-type annular region formed on the main surface of the guard ring 4.

次に動作について説明する。Next, the operation will be described.

第2図は第1図におけるガードリング4付近の拡大図で
あり、図において、9は空乏領域、10はp型半導体層2
と絶縁膜5との結晶格子のミスフィットによる結晶欠陥
及び局在準位を表している。ガードリング4主表面に形
成されたp型環状領域8はp型半導体層2と同じ導電型
であるので機能的にはp型半導体層2と一体のものと考
えてよい。すなわちガードリング4に高い正の電位を与
えると、pn接合における空乏領域9は図のように広が
る。そしてp型半導体層2の一部は完全に空乏化され、
金属3とp型半導体層2とによるショットキ接合の周囲
におけるリーク電流は、この空乏領域の高いポテンシャ
ルにより阻止される。
FIG. 2 is an enlarged view of the vicinity of the guard ring 4 in FIG. 1, in which 9 is a depletion region and 10 is a p-type semiconductor layer 2.
3 shows a crystal defect and a localized level due to a misfit of the crystal lattice between the insulating film 5 and the insulating film 5. Since the p-type annular region 8 formed on the main surface of the guard ring 4 has the same conductivity type as the p-type semiconductor layer 2, it may be considered to be functionally integral with the p-type semiconductor layer 2. That is, when a high positive potential is applied to the guard ring 4, the depletion region 9 at the pn junction expands as shown in the figure. Then, a part of the p-type semiconductor layer 2 is completely depleted,
The leak current around the Schottky junction formed by the metal 3 and the p-type semiconductor layer 2 is blocked by the high potential of the depletion region.

また、ガードリング4主表面のp型環状領域8は不純物
拡散やイオン注入等の方法により作製されるためn型の
ガードリング4とのpn接合は結晶欠陥や局在準位のない
完全な接合であり、リーク電流は発生しない。したがっ
てガードリング4と金属3の間にリーク電流が流れる事
はない。
Further, since the p-type annular region 8 on the main surface of the guard ring 4 is formed by a method such as impurity diffusion or ion implantation, the pn junction with the n-type guard ring 4 is a perfect junction having no crystal defects or localized levels. Therefore, no leak current occurs. Therefore, no leak current flows between the guard ring 4 and the metal 3.

以上のように本実施例によれば、ガードリング4主表面
の、ガードリング4と半導体層2の接触端がその主表面
上となる位置に、半導体層2と同じ導電型の環状領域8
を形成したので、半導体層2とガードリング4間のpn接
合は完全なものとなり、ガードリング4と金属3の間の
リーク電流を制御することができる。
As described above, according to this embodiment, the annular region 8 of the same conductivity type as that of the semiconductor layer 2 is formed on the main surface of the guard ring 4 at the position where the contact end between the guard ring 4 and the semiconductor layer 2 is on the main surface.
Since the pn junction between the semiconductor layer 2 and the guard ring 4 is completed, the leak current between the guard ring 4 and the metal 3 can be controlled.

なお、上記実施例においてp型とn型を入れ換えても、
電位の正負を入れ換えれば同様な効果があることは言う
までもない。
Even if the p-type and the n-type are interchanged in the above embodiment,
It goes without saying that the same effect can be obtained by switching the positive and negative potentials.

〔発明の効果〕〔The invention's effect〕

以上のようにこの発明に係る半導体装置によれば、基板
内に形成されたガードリング主表面に、半導体層と絶縁
膜との接触端同士が当接する位置に沿って、半導体層と
同一導電型の環状領域を形成したので、半導体層とガー
ドリング間のpn接合が完全なものとなり、金属とガード
リングとの間のリーク電流を制御することができるとい
う効果がある。
As described above, according to the semiconductor device of the present invention, the same conductivity type as the semiconductor layer is formed on the main surface of the guard ring formed in the substrate along the position where the contact ends of the semiconductor layer and the insulating film contact each other. Since the annular region is formed, the pn junction between the semiconductor layer and the guard ring is completed, and the leak current between the metal and the guard ring can be controlled.

【図面の簡単な説明】[Brief description of drawings]

第1図はこの発明の一実施例による半導体装置の断面
図、第2図は第1図の要部拡大図である。第3図は従来
の半導体装置の断面図であり、第4図(a)及び(b)
は第3図の要部拡大図である。 図において1はp型半導体基板、2はp型半導体層、3
は金属、4はガードリング、5は絶縁膜、6及び7は電
極、8はp型環状領域、9は空乏領域、10は結晶欠陥や
局在準位を表わす印、11はリーク電流を表わす矢印であ
る。 なお図中同一符号は同一又は相当部分を示す。
FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is an enlarged view of a main part of FIG. FIG. 3 is a sectional view of a conventional semiconductor device, and FIGS. 4 (a) and 4 (b).
FIG. 4 is an enlarged view of a main part of FIG. In the figure, 1 is a p-type semiconductor substrate, 2 is a p-type semiconductor layer, 3
Is a metal, 4 is a guard ring, 5 is an insulating film, 6 and 7 are electrodes, 8 is a p-type annular region, 9 is a depletion region, 10 is a mark indicating a crystal defect or a localized level, and 11 is a leak current. It is an arrow. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】第1導電型半導体基板の主表面に設けられ
た第2導電型の環状領域と、 該環状領域の内周縁部から外周縁部までの間の主表面に
その接触端が位置する絶縁膜と、 上記半導体基板,絶縁膜及び上記環状領域の主表面上に
設けられ、その接触端が上記絶縁膜の接触端と当接し、
素子を構成する第1導電型の半導体層と、 該第1導電型の半導体層上に設けられ、その接触端が上
記環状領域又は該環状領域の外側に存在する上記第1導
電型の半導体基板の主表面上に位置する、電極を有する
ショットキ接合金属層と、 上記第2導電型の環状領域の主表面で上記絶縁膜の接触
端と上記第1導電型の半導体層の接触端同士が当接する
位置に沿って設けられた第1導電型の環状領域とを備え
たことを特徴とする半導体装置。
1. A second-conductivity-type annular region provided on the main surface of a first-conductivity-type semiconductor substrate, and its contact end located on the main surface between the inner peripheral edge and the outer peripheral edge of the annular region. Provided on the main surfaces of the insulating film and the semiconductor substrate, the insulating film and the annular region, the contact end of which is in contact with the contact end of the insulating film,
A first-conductivity-type semiconductor layer that constitutes an element, and the first-conductivity-type semiconductor substrate that is provided on the first-conductivity-type semiconductor layer and has a contact end located outside the annular region or outside the annular region. The Schottky junction metal layer having an electrode located on the main surface of the second conductive layer, and the contact surface of the insulating film and the contact edge of the first conductive type semiconductor layer contact each other on the main surface of the second conductivity type annular region. A semiconductor device comprising: a first conductivity type annular region provided along a contact position.
【請求項2】上記第2導電型の環状領域に所定の電圧を
印加する電極を備えたことを特徴とする特許請求の範囲
第1項記載の半導体装置。
2. The semiconductor device according to claim 1, further comprising an electrode for applying a predetermined voltage to the second conductivity type annular region.
JP1317281A 1989-12-05 1989-12-05 Semiconductor device Expired - Fee Related JPH0697691B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1317281A JPH0697691B2 (en) 1989-12-05 1989-12-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1317281A JPH0697691B2 (en) 1989-12-05 1989-12-05 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH03177068A JPH03177068A (en) 1991-08-01
JPH0697691B2 true JPH0697691B2 (en) 1994-11-30

Family

ID=18086482

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1317281A Expired - Fee Related JPH0697691B2 (en) 1989-12-05 1989-12-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0697691B2 (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4934028A (en) * 1972-07-31 1974-03-29
JPS6031112A (en) * 1983-08-01 1985-02-16 Hitachi Ltd Scanning photon microscope
CA1285334C (en) * 1987-01-13 1991-06-25 Rick C. Jerome Schottky barrier diode with highly doped surface region

Also Published As

Publication number Publication date
JPH03177068A (en) 1991-08-01

Similar Documents

Publication Publication Date Title
JPH04127480A (en) High breakdown strength low resistance semiconductor device
JP2003142698A (en) Power semiconductor device
US6423598B1 (en) Semiconductor device, a method of manufacturing the same, and a semiconductor device protective circuit
JPWO2000021140A1 (en) Semiconductor device, its manufacturing method, and semiconductor device protection circuit
JP3623687B2 (en) Schottky barrier diode and manufacturing method thereof
JP2013105798A (en) Semiconductor device and method for manufacturing the same
KR100491851B1 (en) Semiconductor device and manufacturing method therefor
JP3489567B2 (en) Semiconductor element
JP3357394B2 (en) Bidirectional surge suppressor circuit
JP2005005486A (en) Silicon carbide semiconductor device
JPH0697691B2 (en) Semiconductor device
JP2758465B2 (en) Semiconductor device
JP3581027B2 (en) Schottky barrier semiconductor device
JPH0227822B2 (en)
JP6539026B2 (en) Semiconductor device and method of manufacturing the same
JP4942367B2 (en) Semiconductor device
KR101184378B1 (en) Schottky diode and method for manufacturing the same
JP2785792B2 (en) Power semiconductor device
KR100298573B1 (en) Triac device of planar type
JPH0832049A (en) Semiconductor device
JP3149483B2 (en) Planar type semiconductor rectifier
JP2000340806A (en) Semiconductor device
JPS5992575A (en) Schottky barrier diode in semiconductor integrated circuit device
JPS639670B2 (en)
JPH05218452A (en) Electrostatic induction type semiconductor device

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees