JPH07101341B2 - Access method for refresh memory, display controller, and graphic processing device - Google Patents

Description

The present invention relates to a method for accessing a refresh memory for storing display information to be displayed on a display device, a display controller using the access method, and the display controller. The present invention relates to a graphic processing device using.

[Conventional technology]

A CRT controller that realizes the display control function of a raster scanning type display device with a large-scale integrated circuit (hereinafter referred to as LSI) is used as a control for displaying characters and figures using a cathode ray tube (hereinafter referred to as CRT). Widely used. This CRT controller has a function of sequentially outputting memory addresses from a preset display start address in accordance with raster scanning. It also has a function of outputting a synchronization signal for driving the display device. This conventional type
There is a method shown in FIGS. 1 and 2 as a method of superimposing and displaying a plurality of independent pieces of screen information by using a CRT controller.

In FIG. 1, one CRT controller 13 controls the refresh memories 161 and 162 divided into a plurality of banks. The CRT controller 13 is connected to a central processing unit (CPU) by an address bus 11 and a data bus 12, and is provided with a refresh memory address for display and a CRT.
To generate the sync signal. The CRT controller 13 of the clock generation circuit 14 supplies an operation clock to the parallel / serial converters 171 and 172. The address selection circuit 15 is
Select the display memory address supplied from the CRT controller 13 by selecting the CPU address bus 11 during the non-display period.
Two refresh memory banks 161, 162 are accessed. The data read from the memory are independently converted into serial signals by the parallel / serial converters 171 and 172, and the synthesis circuit 1
Stacked at 8.

Since the same display address is supplied to the two memory banks in the conventional method having such a configuration, the two screens to be superimposed must have the same screen configuration.
Therefore, even when only a part of the display screen is superposed, there is a problem that the memory capacity for two display screens is required and the memory utilization efficiency deteriorates. Further, when the screen is moved by rewriting the display start address, the two screens cannot be moved independently. Further, there is a drawback that the drawing speed becomes slow because the contents of the refresh memory cannot be rewritten during the display period.

FIG. 2 shows the individual control of a plurality of memory banks by using a plurality of CRT controllers as shown in FIG.
The two CRT controllers 131 and 132 receive the same clock from the clock generation circuit 14 and perform a synchronous operation, and individually generate a display memory address to access the refresh memories 161 and 162. The read data is converted into a serial signal by the parallel / serial converters 171, 172, and the combining circuit 1
At 8, a superposed image signal is obtained.

In this method, since the addresses of the two display screens are controlled independently, the screens can be moved independently, but there is a disadvantage that the number of parts and the amount of wiring are large and the device becomes large-scale. Also, when overlaying only a part of the display screen, the capacity of the refresh memory can be reduced, but the memory for each screen is physically separated, so the maximum size of the overlay screen is It must be designed according to the size. Further, also in this case, as in FIG. 1, the drawing speed is slow because the contents of the refresh memory cannot be rewritten during the display period. As a conventional method similar to the method shown in FIG. 2, Japanese Patent Laid-Open No. 52-95926 is known.

In any of the above-mentioned known techniques, during the display period of the display device, the CRT controller only performs display access for reading display information from the refresh memory, and the central processing unit (excluding the display period). CP
U) was performing drawing access for rewriting the memory (hereinafter, rewriting between the CPU and the memory is called "drawing"). That is, there is a problem that a sufficient drawing speed cannot be achieved due to the limited time for drawing access.

As a method for solving this problem, a method disclosed in Japanese Patent Laid-Open No. 52-82134 is known. This is one character display timing is 2 in the charactor code method.
It is divided into display access and drawing access. That is, according to this method, half of one frame period can be allocated to the drawing access from the CPU, and the drawing speed is improved.

[Problems to be Solved by the Invention]

In the character code method as shown in the above-mentioned conventional example, there is no problem even if the time for drawing access is limited to the drawing access time by the conventional time division method. However, in the graphic display method, the amount of data to be handled is remarkably increased, so that securing sufficient time for drawing access remains a problem. In other words, securing as much time as possible for drawing access directly affects the performance of graphics processing.
Further improvement is strongly demanded.

The present invention provides a refresh memory that can secure a sufficient drawing cycle for performing drawing access for rewriting the contents of a refresh memory that stores display information, has a high drawing speed, and can supply a stable image to a display device. The purpose is to provide access methods.

Another object of the present invention is to provide a display controller and a graphic processing device for accessing a refresh memory by the access method.

[Means for Solving the Problems]

In order to achieve the above object, in a method of accessing a refresh memory for storing display information to be displayed on a display device, a drawing access for rewriting the display information of the refresh memory is performed in a display period of the display device. And the period other than the display period, the ratio of the time for executing the drawing access during the period other than the display period is made higher than the ratio for the time for performing the drawing access during the display period. It is a thing.

Further, in order to achieve the above-mentioned other object, in a display controller for performing display control of a scanning type display device using a refresh memory for storing display information, a timing signal indicating a display period of the display device is generated. A timing processor which is a first means, and a display processor which is a second means which performs display access for reading display information from the refresh memory, and a drawing access which is a process for rewriting the display information of the refresh memory are executed. And a drawing processor which is the third means.

Further, a graphic processing device equipped with such a display controller is also featured.

[Action]

By setting the ratio of the time for executing drawing access during the period other than the display period to be higher than the ratio of time for executing the drawing access during the display period, the drawing access time of the refresh memory will be sufficient. It can be secured and the drawing speed can be increased. Specifically, in response to the signal from the timing processor, during the display time of the display device, m (m
Is an integer greater than or equal to 1) and n (n is a rectification of 1 or more) drawing access by the drawing processor is repeated, and during a period other than the display period of the display device, the drawing processor uses (n + 1) times. The drawing access is continuously performed. Accordingly, the display controller can secure a sufficient time for drawing access to the refresh memory.

〔Example〕

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 3 shows an example in which a display system is constructed using the display controller according to the present invention. In this example, it is composed of a display controller 31, a clock generation circuit 32, a refresh memory 33, a latch 34, parallel / serial conversion circuits 171, 172, and a synthesis circuit 18. Display Controller 31
Is connected to the address bus 11 and data bus 12 of the CPU to transfer various control information. Refresh memory bus 3c and CPU
It is separated from the buses 11 and 12, and all accesses from the CPU side are performed via the display controller 31. The refresh memory bus 3c is a multiplexed bus for address and data. The clock generation circuit 32 generates various clock signals used in the system such as the dot clock 3a, the drive clock 3b of the display controller 31, the first phase data load timing 3d, and the second phase data load timing 3e. In the mode for superimposing two (n = 2) screens, memory access is performed twice (n times) during one display period, and two independent image information are read in a time division manner. In the case of three screens, memory access is performed three times during one display period. The same applies to the case of four or more sheets.

FIG. 4 shows a time chart of superimposed display. One 16-dot cycle constitutes one display cycle, and memory access is performed twice during one display cycle. The read data in the first phase is temporarily stored in the latch 34 at the first phase load timing 3d. The read data in the second phase is loaded into the parallel / serial converter 172 at the second phase load timing, and at this time, the contents of the latch 34 are synchronized with the parallel / serial converter.
Loaded in 171. The contents of the two parallel-to-serial converters 171 and 172 are simultaneously converted into serial data, which are combined by the combining circuit 18 and output as a combined video signal 3f.

FIG. 5 shows the internal configuration of the display controller 31, which is composed of a drawing processor 51, a display processor 52, a timing processor 53, a CPU interface 54, and a display interface 55. Drawing processor 51
Controls the generation of graphics such as lines and planes and the data transfer between the CPU and the refresh memory. It outputs the drawing address and reads / writes the refresh memory. The display processor 52 outputs the display address of the refresh memory which is sequentially displayed according to the raster scanning. The timing processor 53 generates various timing signals such as a CRT synchronization signal, display timing, and a display / drawing switching signal.
The CPU interface 54 controls the interface with the CPU such as synchronization between the CPU data bus and the CRT controller. The display interface 55 controls the interface between the refresh memory and the display device, such as the address switching control between display and drawing. The processing efficiency is improved by the functions of the three processors for drawing, displaying, and timing being distributed and operating in parallel.

Now, in FIG. 5, the timing processor 53 inputs the clock through the display interface 55 and outputs various timing signals necessary for display here. Details of the internal structure of the timing processor 53 are shown in FIG. 6, and the description thereof will be given later. The timing processor 53 generates horizontal and vertical sync signals, a sync signal required for display such as a character sync signal indicating one character display period, and generates a display address at a timing when the one character display period is divided into n. Timing signals are generated. The period in which the timing signal is generated is called one memory cycle. Note that how much one memory cycle is, in other words, how much n is determined depends on the number of screens to be superimposed and the balance between display and drawing. The timing processor 53 stores the data n sent from the CPU (not shown) via the CPU interface 54 in an internal memory (register) and generates a timing signal corresponding to the data n. To do. Of course, the timing processor 53 similarly arranges other data for generating the synchronizing signal in the respective internal registers. The display processor 52 generates a display address in synchronization with the display address generation timing issued by the timing processor 53, and supplies this to the refresh memory 33 (see FIG. 3) via the display interface 55.

Details of the internal structure of the display processor 52 are shown in FIG. 15, and a detailed description thereof will be given later. Display processor
In 52, n sets of display addresses are generated in a time-division manner within one character display period. Therefore, n sets of display start addresses are stored, and the timing processor 53 generates a generation timing signal for each display address. Each time, the increment of each display address of n sets is calculated, and each display address is generated as the sum of this increment and the stored display start address. The respective generated display addresses are output to the refresh memory via the display interface 55. The data required for the calculation in the display processor 52 is stored in the internal memory or register via the CPU interface 54. Drawing processor 51
Is used when so-called display (drawing) is performed by storing information to be displayed in the refresh memory, but a detailed description thereof will be omitted here.

FIG. 6 shows the detailed structure of the timing processor 53 described above. It is composed of a control unit 61, a micro instruction decoder 62, and an arithmetic unit 63. Further, the control unit 61 includes a horizontal entry address pointer 6101, a micro program address register 6102, a micro program memory (composed of ROM) 6103, a micro instruction register 6104, registers 6105, 6106, 6107, a vertical entry address pointer 6108, a register 6109, It consists of 6110, 6111, 6112. The arithmetic unit 63 includes a data RAM 6301 for storing control data transferred from the CPU, a work register 6302, an arithmetic unit (AU) 6303, a horizontal counter 6304 for counting horizontal system timing and generating a horizontal synchronizing signal, and a vertical system. It is composed of a vertical counter 6305 for counting the raster timing of each and generating a vertical synchronization signal, and buses 6306, 6307. Details of the micro instruction decoder 62 itself will be described later.

FIG. 7 shows the time chart for FIG. At the start point of the vertical sync signal, the register 6109 uses the vertical entry address pointer to set the initial value A (V
B ₁ ), and is initialized to A (VW ₁ ) in the second phase. The vertical addresses of the first phase and the second phase are stored in the registers 6109 and 611.
It is stored by a closed loop of 0,6111,6112. At the start point of horizontal synchronization, the horizontal entry address pointer 61
01 allows the microprogram address register 6102
Are initialized to A (HB ₁ ) in the first phase and A (HW ₁ ) in the second phase. After that, the microprogram operation is started in synchronization with the falling edge of the horizontal sync signal (HSYNC), and according to the designation of the microprogram address register 6102, the corresponding microinstruction is read from the microprogram memory 6103 and stored in the microinstruction register 6104. To be done. The read micro instruction is decoded by the micro instruction decoder 62, and various control signals are supplied to the arithmetic unit 63. On the other hand, a part of the micro instruction is stored in the temporary storage register 6106 as the next address. One bit of the micro program address is a bit indicating whether it is a horizontal cycle micro program address or a vertical cycle micro program address, and this bit is returned to one bit of the register 6106 through the register 6105. On the other hand, in the φ1 cycle in which the next address of the first phase is fetched in register 6106, the microprogram address of the second phase is transferred to microprogram address register 6102, and the corresponding microinstruction is read and executed. The next address stored in register 6106 is
Micro Program Address Register 6102 through 6107
Sent to. In this way, the first-phase microprogram and the second-phase microprogram are sequentially executed alternately. When a vertical cycle microprogram is executed, the inputs of the microprogram address register 6102 and the register 6109 are switched according to the designation from the microinstruction. That is, the address A (V
B _n ), A (VW _n ) are sequentially sent to the microprogram address register 6102 during one cycle of the first phase and the second phase, and at the same time, the next address A (HB
_{m + 1} ), A (HW _{m + 1} ) are sequentially sent to the register 6109 and stored in the loop of the registers 6109-6112. As a result, it is possible to execute independent microprograms of horizontal first and second phases and vertical first and second phases in total in four phases.

FIG. 8 shows the format of the micro instruction. Word length is 21 bits and two formats are selected in bit 19 # 0, #
There is one. Bit 20 (HV) is a bit for controlling the switching between the horizontal microprogram address and the vertical microprogram address. Bits 18 to 10 have two microinstructions and different functions. The microinstruction # 0 controls the operation on the work register 6302. That is, the data is read from the register specified by S-REG, the operation specified by AUF is performed, and the result is written in the register specified by D-REG. The # 1 microinstruction controls data transfer between the data RAM 6301, the work register 6302, and the horizontal and vertical counters 6304 and 6305. FLAG of bits 9 to 5 designates control of flag information output from AUs and counters and control of conditional branching. Bits 4-0 of the ADF are fields that control the next address of the microprogram.

FIG. 9 shows details of the microinstruction decoder 62. The microinstruction temporarily stored in the microinstruction register 6104 is transferred via the control register 6201 to the decoder 6202 of each field.
Sent to ~ 6207. The RAM address decoder 6202 decodes the RAM field of the # 1 microinstruction and generates a word selection signal for RAM. Read register decoder 6203 is # 0
Decodes S-REG field of micro instruction
The signal for selecting the read register is output to 307. The write register decoder 6204 is a D-RE of # 0 micro instruction.
The G field and the REG field of the # 1 microinstruction are decoded and the write register selection signal from the bus 6306 is output. During the transfer from the horizontal / vertical counter to the data RAM 6301, the reading to the bus 6306 is controlled by the REG field. Function decoder 6205 decodes the AUF field of # 0 microinstruction, and arithmetic unit (AU) 6303
Control the calculation mode of. The conditional branch decoder 6206 determines the state of the flag register according to the designation of the FLAG field of the microinstruction, controls the least significant bit of the address transferred from the register 6106 to the register 6107, and enables the conditional branch. The flag register 6207 temporarily stores the plug information output from the adder (AU) 6303 and the counters 6304 and 6305 according to the designation of the micro instruction. The flag register has a horizontal sync signal (HSYNC) and a vertical sync signal (V
SYNC), horizontal base screen display timing (HBDISP), vertical base screen display timing (VBDISP), horizontal window screen display timing (HWDISP), vertical window screen display timing (VWDISP).

FIG. 10 shows a screen configuration example controlled by the display controller 31. Two independent screens, a base screen and a window screen, can be combined and displayed. The size and display position of the two screens can be set independently.

Of course, it is possible to set one screen by setting parameters. The meaning of each parameter is as follows.

(1) Horizontal sync cycle (HC): Horizontal sync signal (HSYN)
It is the number of sykes in C).

(2) Horizontal sync signal pulse width (HSW): This is the pulse width of the horizontal sync signal (HSYNC) that drives the CRT device.

(3) Horizontal base screen start position (HBS): From the falling edge of the horizontal sync signal (HSYNC) to the horizontal base screen display signal (HBD)
It is the time until the rise of ISP).

(4) Horizontal base screen width (HBW): Horizontal width of the base screen, that is, "1" of the horizontal base screen display signal (HBDISP)
Is the pulse width of the period.

(5) Horizontal window screen start position (HWS): From the falling edge of the horizontal sync signal to the horizontal window screen display signal (HWDI)
It is the period until the rise of SP).

(6) Horizontal window screen width (HWW): Horizontal width of window screen, that is, horizontal window screen display signal (HW)
DISP) “1” period pulse width.

(7) Vertical sync cycle (VC): Vertical sync signal (VSYN)
It is the number of cycles in C).

(8) Vertical sync signal pulse width (VSW): This is the pulse width of the vertical sync signal (VSYNC) that drives the CRT device.

(9) Vertical base screen start position (VBS): The time from the fall of the vertical sync signal (VSYNC) to the rise of the vertical window screen display signal (VBDISP).

(10) Vertical base screen width (VBW): Vertical line of the base screen, that is, "1" of the vertical base screen display signal (VBDISP).
Is the initial pulse width of.

(11) Vertical window screen start position (VWS): Vertical window screen display signal (VWDI)
It is the period until the rise of SP).

(12) Vertical window screen width (VWW): Vertical width of the window screen, that is, vertical window screen display signal (VW
DISP) “1” period pulse width.

In accordance with the above-mentioned setting of each parameter value, the timing processor 53 shown in FIG.
C, HBDISP, HWDISP, VSYNC, VBDISP, VWDISP, etc.). The display processor 52 proceeds with the process by referring to this timing signal.

11 to 14 show an example of the microprogram processing flow of the timing processor 53. FIG. 11 shows a horizontal first phase microprogram. 1
At the start point of the raster, the HBDISP flag is set to "0", and it is checked whether or not it is the first raster (first raster of the frame). In the case of the first raster, vertical parameters (VDS, VDW, VWS, VWW) are transferred from the data RAM 6301 to the work register 6302, and the processing of the raster is completed. For rasters other than the first raster, the horizontal control parameters (HDS, HDW, HWS, HWW) are first loaded into the corresponding work registers T0 to T3. Next, T0 is sequentially subtracted until it becomes "0", and when it becomes "0", the HBDISP flag is set to "1". After that, T1 is sequentially subtracted until it becomes "0", and when it becomes "0", HB
Set DISP flag to "0". Finally, the processing is switched to vertical processing, and the processing for one raster is completed.

FIG. 12 shows a horizontal second phase microprogram, which is the same as the eleventh embodiment except that the data RAM is not loaded.
It is similar to the case of the figure.

Similarly, FIGS. 13 and 14 show vertical first phase and second phase microprogramming processes, respectively. For vertical processing, the work register is subtracted and "0" only once per raster.
Detection processing is performed.

As described above, one arithmetic unit is used in time division by a four-phase microprogram, and four timing signals HBDIS are used.
Can generate P, HWDISP, VBDISP, VWDISP.

FIG. 15 shows the detailed structure of the display processor 52 shown in FIG. It is composed of a control unit 151, a micro instruction decoder 152, and a calculation unit 153. The control unit 151 includes an entry address pointer 1511, a micro program address register 1512, a micro program memory (made up of ROM) 1513, a micro instruction register 1514, and temporary storage registers 1515, 1516.

Further, the calculation unit 153 is directly accessed from the CPU side via the CPU interface, and the display start addresses (BSA, WSA) of the base screen (first screen) and the window screen (second screen) are displayed.
Data RAM 1531 that stores control information such as 1 Work register 1532 that stores the display address (BRS, WRS) at the beginning of the raster, Register 1533 that stores the current display address (ALM, ALS), 1 Display for each raster Address increment value (BMW, WM
W) register 1634, arithmetic unit (AU) 1535, memory address register (MAR) 1536, X bus 1537, Y bus 1538, Z
Consists of bus 1539.

FIG. 16 shows the time chart for FIG. Micro program address register by horizontal sync signal
1512 is initialized to the contents of the entry address pointer 1511. After the fall of the horizontal synchronizing signal (HSYNC), the microprogram ROM 1513 is accessed by the microprogram address register 1512, and the read output is temporarily stored in the microinstruction register 1514. This micro instruction is decoded by the micro instruction decoder 152,
Various control signals are supplied to the arithmetic unit 153. A part of the microinstruction is returned to the temporary storage registers 1515 and 1516, and the content becomes the address of the next next microinstruction. In this way, microprograms starting from the addresses A (B ₁ ) and A (W ₁ ) initialized by the entry address pointer are sequentially executed alternately.

FIG. 17 shows the microinstruction format of the display processor. The word length is 28 bits and the two formats selected in bit 27 are # 0, #
There is one. The # 0 microinstruction controls the operation between registers. In addition, the # 1 micro instruction controls data transfer between the data RAM and each register.

FIG. 18 shows the details of the microinstruction decoder 152. 9th
Microprocessor decoder for the timing processor shown in the figure
It consists of decoder units similar to 62. The conditional branch is controlled with reference to the synchronous timing signal supplied from the timing processor.

FIGS. 19A to 19C show three kinds of operation modes controlled by the display processor 52. CR depending on each mode
At the T interface 55, the memory address (B), the memory address (W) of the window screen, and the drawing memory address (hatched in the figure) are appropriately switched and output to the base screen.

(A) Single access mode (FIG. 19 (A)) This is a mode in which the display cycle and the memory cycle are the same. First in the base screen area outside the window
The switching control is performed so that the memory address (B) of the base screen calculated by the phase is output and the memory address (W) of the window screen calculated by the second phase is output inside the window. 1 memory cycle in this mode
In order to equalize the display cycle, the speed of the memory and the number of parts for the system mechanism are the same as in the case of using the conventional CRT controller, but various independent two pieces of screen information can be combined and displayed. In this mode, the time other than the display period (hatched portion in the figure) is used for drawing processing.

(B) Double access non-overlapping mode (FIG. 19 (B)) A mode in which memory access is performed twice during one display cycle. The first time is used for display and the second time is used for drawing during the display period. . In the first display cycle, the memory address (B) calculated by the microprogram of the first phase is output in the base screen area outside the window, and the memory address (W) calculated by the second phase is output inside the window. Switching control is performed so that Drawing can be continuously executed at times other than the display period. When this mode is used, the memory access time for drawing (hatched portion in the figure) can be secured during the display period in addition to the time other than the display period, which is effective in speeding up the drawing process. For example, when using a display device in which the display period occupies 75% of one frame time, 25% of the time other than the display period and half of the display period are used.
62.5% time plus 7.5% can be used for drawing.

(C) Double access overlay mode (Fig. 19 (C)) Two memory accesses are performed in one display cycle, and the first memory access is performed in the display area of the base screen by the first phase microprogram. The memory address (B) is output, and the memory address (W) calculated by the second phase microprogram is output as the second memory access inside the window. As a result, since the display memory is accessed twice in one display cycle within the window, the read-out independent screen information for two sheets can be combined and displayed by the external circuit, thereby making it possible to perform a superimposed display. The second memory cycle outside the window (shaded area in the figure) is used as a drawing cycle.

FIG. 20 shows the correspondence between the display screen and the memory space. As shown in the figure, the display data of the base screen and the window screen can be set in the same address space with any size. Therefore, the flexibility of the screen configuration is high and the memory efficiency is good.

FIG. 21 and FIG. 22 show an example of the processing flow of the microprogram of the display processor, which are the processing flow of the first phase and the second phase, respectively. Hereinafter, description will be added with reference to FIG. 21 as an example. Immediately after the horizontal synchronizing signal, it is first checked whether or not the VBDISP signal is "1", and if it is "0", the raster is ended without performing anything. If it is "1", then send the start address (BRS) of the raster of the base screen to the register (ALM, ALS) that manages the current display address, and then B
The increment value (BMW) for each raster is added to RS, and it is stored in BRS as the start address of that raster. Next, the base screen display start point (HBDISP = "1") becomes a waiting cycle, and when the display start point is reached, the ALS is transferred to the memory address register (MAR), and the ALS content is set to +1. Less than,
This process is repeated until the horizontal sync signal is reached, and memory addresses are sequentially output. Similar processing is performed in the case of FIG.

In this way, in this example, independent two-system microprograms are alternately processed, and as a result, the two-system display address update calculation can be efficiently performed.

In the display device using the display controller shown in the above-mentioned embodiment, it is also possible to perform the overlay display in which the memory efficiency of the refresh memory is improved.
Also, it is possible to realize overlay display with a high degree of freedom in screen configuration.

〔The invention's effect〕

As described in detail above, according to the present invention, the display access and the drawing access of the refresh memory are alternately performed during the display period of the display device, and the refresh memory is continuously refreshed during the period other than the display period of the display device. Since the drawing access of the memory can be performed, there is an effect that more drawing access time can be secured and the drawing speed can be increased as compared with the conventional known technique.

[Brief description of drawings]

1 and 2 are conventional system configuration diagrams, FIG. 3 is a system configuration diagram using a display controller according to the present invention, FIG. 4 is its operation time chart, and FIG. 5 is a display controller. Internal configuration diagram, No. 6
Fig. 7 is a block diagram of the timing processor, Fig. 7 is its operation time chart, Fig. 8 is its microinstruction format, Fig. 9 is a detailed block diagram of its microinstruction decoder, and Fig. 10 is a display screen. An example of the configuration of Fig. 11, Fig. 12, Fig.
13 and 14 show an example of the processing flow of the timing processor, FIG. 15 is a block diagram of the display processor, FIG. 16 is its operation time chart, FIG. 17 is its microinstruction format, and FIG. The figure is a detailed block diagram of the microinstruction decoder, FIGS. 19 (A) to (C) are diagrams for explaining the display operation mode, and FIG. 20 is a diagram for explaining the relation of display addresses.
21 and 22 are diagrams showing examples of the processing flow of the display processor, respectively. 31 …… Display controller, 32 …… Clock generation circuit, 34 …… Latch, 52 …… Display processor, 53 …… Timing processor, 1515,1516 …… Temporary storage register, 1532 …… Work register.

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical indication location G09G 5/00 R 9471-5G 5/36 520 M 9471-5G 530 E 9471-5G F 9471-5G (56) References JP-A-57-196292 (JP, A) JP-A-56-6187 (JP, A) JP-A-54-47424 (JP, A) Practical application Sho-55-169573 (JP, U)

Claims (6)

[Claims] 1. A refresh memory for storing display information to be displayed on a display device and an instruction from the central processing unit, and accesses the refresh memory according to the received instruction to update the display information in the refresh memory. A display controller including a drawing processor and a display processor that reads display information from the refresh memory for displaying on a display device, wherein one display unit is displayed on the display device during a display period of the display device. From K memory access cycles obtained by dividing a display cycle, which is a cycle synchronized with the display period having the same length as the period, into the number M of images to be superimposed and displayed in the dynamically changing display cycle. According to the above, the superimposed display is selected. A number of memory access cycles equal to the number M of images are assigned to display access cycles, and N (where N = K−M) memory access cycles not assigned to display access cycles out of K memory access cycles. , The drawing access cycle is allocated to the drawing access cycle, and during the non-display period of the display device, at least N memory access cycles out of K memory access cycles obtained by dividing the display cycle into K are used for the drawing access cycle. The display processor sequentially allocates M pieces of display information to be superimposed and displayed in the display cycle in each of the M memory access cycles allocated to the display access cycle during the display period. Display on the display device Read from the refresh memory, and the drawing processor accesses the refresh memory as necessary and stores the refresh memory in each memory access cycle assigned to the drawing access cycle of each display cycle. Updating the display information, the method for accessing a refresh memory in a display controller. 2. A display which, under the control of a central processing unit, controls updating of display information in a refresh memory for storing display information to be displayed on a display device and reading of display information from the refresh memory for displaying on the display device. A controller that receives an instruction from the central processing unit, accesses the refresh memory according to the received instruction, and updates display information in the refresh memory, and displays on a display device from the refresh memory. Display processor to read display information for
A timing access processor that allows the drawing processor to access a refresh memory; and a timing processor that allocates a display access cycle in which the display processor reads display information from the refresh memory for display on a display device. During the display period of the display device, the processor divides a display cycle, which is a cycle synchronized with the display period having a length equal to a period for displaying one display unit on the display device, into K memory access cycles. From among the number of memory access cycles selected according to the number M of images to be superimposed and displayed in the dynamically changing display cycle, the number of memory access cycles equal to the number M of images to be superimposed and displayed are set as the display access cycle. Allocation, K memory N not assigned to the display access cycle of the access cycles (however, N = K-
M) memory access cycles are allocated to the drawing access cycles, and during the non-display period of the display device, at least a number exceeding K of the K memory access cycles obtained by dividing the display cycle into K. Memory access cycle of the memory access cycle to the drawing access cycle, the display processor, in the display period, in each of the M memory access cycles allocated to the display access cycle, superimposed display in the display cycle. The drawing processor has means for sequentially reading M display information from the refresh memory for displaying on the display device, and the drawing processor is arranged in each memory access cycle allocated to the drawing access cycle of each display cycle. , The riff Display controller characterized in that it comprises means for updating the display information stored in the refresh memory and accessed as needed to Sshumemori. 3. The display controller according to claim 2, wherein the display processor unconditionally sets the one display cycle to the one memory cycle according to an external setting,
A display controller having means for allocating all memory access cycles during the display period of the display device to the display access cycles. 4. The display controller according to claim 2, wherein the refresh memory stores display information of a plurality of systems that respectively configure a plurality of screens, and the display controller has each display cycle. In accordance with the position on the screen of the display device in which the display unit is displayed by the display information read in, a system for reading display information from the refresh memory in the display cycle belongs to at least the display cycle. A display controller having means for switching for one display access cycle. 5. The display controller according to claim 2, wherein the timing processor, the display processor, and the drawing processor are constructed on a single integrated circuit. 6. A refresh memory for storing display information to be displayed on a display device, and during the display period of the display device, synchronizing with the display period having a length equal to the period for displaying one display unit on the display device. K is the display cycle that is the cycle
Of the divided K memory access cycles, the number equal to the number M of images to be superimposed and displayed, which is selected according to the number M of images to be superimposed and displayed in the dynamically changing display cycle. Memory access cycles are allocated to the display access cycle, and N (where N = K−M) memory access cycles which are not allocated to the display access cycle among the K memory access cycles are allocated to the drawing access cycle, A timing processor that allocates at least N memory access cycles, out of K memory access cycles obtained by dividing the display cycle into K, to the drawing access cycles during a non-display period of the display device; M allocated to the display access cycle during the period In each of the memory access cycles, a display processor for sequentially reading M pieces of display information to be superimposed and displayed in the display cycle from the refresh memory for displaying on the display device, and a drawing access cycle of each display cycle. In each allocated memory access cycle, a display controller including a drawing processor that accesses the refresh memory as needed to update display information stored in the refresh memory, and a display processor of the display controller, M sequentially read on each display cycle during the display period
A unit for matching the phases of the display information pieces, combining the M pieces of display information pieces with the matched phase information into one display information piece, and outputting the combined display information pieces at the same rate as the display cycle rate. A graphic processing device characterized by.