JPH07101450B2 - Labeling processor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a labeling processor, and more particularly, to labeling a plurality of images displayed on a display screen of a CRT or the like in the same image unit. The present invention relates to a labeling processor suitable for

[Conventional technology]

When performing particle analysis of various physical properties, the physical properties to be analyzed are imaged and displayed on a display screen such as a CRT, and labeling processing is performed to divide the objects on the display screen into a plurality of groups.

This labeling process, as shown in FIG.
Raster scanning is performed on the screen of 0 to output mask pattern data of, for example, vertical 2 × horizontal 3 pixels, and a process of attaching a temporary label to these mask pattern data is performed. When performing this temporary labeling, as shown in FIG. 3, when the pixel e of the mask pattern 12 consisting of the pixels a to f is set as the target point, the image 14 of FIG. The pixels are labeled with the number 1. At the time of this temporary labeling, pixels having image information in the mask pattern,
That is, when a high-level pixel first occurs, a label of 1 is attached, and when a point of interest moves in accordance with raster scanning, and when it is 4-connected vertically and horizontally connected to a pixel of another area, the previously assigned label is assigned. Propagate and attach the same number. Further, in the case of 8 connections, when the attention point is associated with the attention point in addition to the attention point in the vertical and horizontal directions, the same label as the previously assigned label is assigned to the attention point. When such temporary labeling processing is performed, the numbers 2, 3, and 4 are added to the image 16 and the image 18 is displayed.
Is attached to the number 6. The numbers 2 and 3 surrounded by the broken line in the image 16 are the confluence points to which either the numbers 2 or 3 are attached, and the number 5 surrounded by the broken line in the image 18 is also the number 5.
And the confluence of the number 6. Therefore, (2,3), (3,4), and (5,6) are respectively registered in the label relation table LRT as a merged label pair.

The numbers 2 to 4 of the numbers 1 to 6 attached as temporary labels are connected by 4 connections, but the numbers 1, 5 and 6 are not connected by 4 connections or 8 connections, so the numbers 2, A label B is attached to 3 and 4, and a label A is attached to the numeral 1. Furthermore, the numbers 5 and 6 are connected by 4 connections, but the numbers 2, 3 and 4 are 4
The numbers 5 and 6 are labeled C because they are not linked by 8 or 8 links. As a final label, the number 1 is labeled A, the numbers 2, 3, and 4 are labeled B, and the numbers 5 and 6 are labeled C. Therefore, it is possible to analyze the images 14, 16 and 18 as being divided into three groups by this labeling process.

[Problems to be solved by the invention]

However, in the above-mentioned conventional technique, as shown in FIG. 4, when the labeling process is performed, the mask pattern data from the pixel cutout unit 100 is transferred to the label determination unit 200.
Given to the 4-connected label determination logic 210 and the 8-connected label stabilization logic 220 to determine whether the mask pattern data belongs to 4-connection or 8-connection, and a signal corresponding to the determination result is generated via the multiplexer 230. Bowl 3
The configuration to output to 00 was adopted. That is, in order to perform the labeling process, since the grouping of images is different between 4-connection and 8-connection, the determination is made by the logic 210 when the 4-connection is made and by the logic 220 when the 8-connection is made. Therefore, there is a problem that the amount of hardware becomes huge when these logics are made into LSI.

An object of the present invention is to provide a labeling processor capable of performing 4-connection labeling and 8-connection labeling on an image signal even by a label determination unit having a single determination logic.

[Means for solving problems]

In order to achieve the above-mentioned object, according to the present invention, a pixel cutout unit for converting a digital image signal into mask pattern data of m × n pixels and a mask pattern data output from the pixel cutout unit according to a 4-connection selection command are left as they are. Transmit,
By the 8 connection selection command, when a specific pixel in the mask pattern is used as a point of interest and image information is present in a region of the mask pattern that is associated with only 8 connection, only 4 connections are associated with the target point. Even if there is no image information in the area, an image conversion unit that outputs mask pattern data forcibly allocating the image information in the area, and mask pattern data output from the pixel conversion unit and new label generation pattern data by 4-connection , Label propagation pattern data and label merging pattern data respectively, to determine whether the mask pattern data belongs to any of the label pattern data, and a label determination unit according to the determination result of the label determination unit. It is to provide a labeling processor including a label generator that generates a label signal.

[Action]

When the digital image signal is converted into m × n pixel mask pattern data and the mask pattern data is labeled by 3 concatenation, the mask pattern data is transmitted as it is, and the mask pattern data and the label pattern data by 4 concatenation are transmitted. Is checked to determine whether the mask pattern data belongs to any pattern. Then, labeling is performed according to the determination result.

On the other hand, in the case where the mask pattern data is labeled with 8 concatenations, when transmitting the mask pattern data, when the image information exists in the region related to only 8 concatenation in the region of the mask pattern data, the target point Four
Even if there is no image information in the area related only to connection,
The mask pattern data in which the image information is forcibly assigned to the area is output, the mask pattern data is collated with the label pattern data by 4-linking, and whether the mask pattern data belongs to any of the label pattern data. Is determined, and labeling is performed according to the determination result.

〔Example〕

 An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, digital image signals of various objects are transmitted to the pixel cutout unit 100.
The pixel cutout unit 100 is adapted to convert one-dimensional digital information into two-dimensional image information. That is, the digital image signal is converted into mask pattern data of m × n pixels. This output is then the pixel conversion unit 400
It is designed to be output to.

The pixel conversion unit 400 has an AND gate as shown in FIG.
440,430, OR gate 410,420, 3 input AND gate 430,
The connect signal 110 and the signals from the pixels a, c, and e of the mask pattern 12 are supplied to 440. A
The output of the ND gate 430 is supplied to the OR gate 410, and the output of the AND gate 440 is output to the OR gate 420. The signal from the pixel d is supplied to the other input of the OR gate 410, and the pixel f is supplied to the other input of the OR gate 420.
The signal from is supplied. And each OR
The outputs d ′ and f ′ of the gates 410 and 420 are 4 of the label determination unit 200A.
It is supplied to the concatenated label judgment logic 220.

The connect signal 110 is set to the low level by the 4-connection selection command and is set to the high level by the 8-connection selection command. For this reason, when 4-link is selected, each AN
The outputs of the D gates 430 and 440 become low level, and as shown in FIG. 6, the signals of the pixels d and f are supplied to the 4-connected label determination logic 210 as they are as d ′ and f ′.

On the other hand, the connect signal 110 becomes high level by the selection command of 8 connection, and the output d ′ of the 4-connection label determination lodge 210,
A high level signal is supplied to f ′ when the signals from the pixels d and f are at a high level and when the signals from the pixels a and e and the pixels c and e are also at a high level. That is, the inputs d ', f'are expressed as d' = d + a.e, f '= f + c.e, as shown in FIG.

That is, the pixel conversion unit 400 transmits the mask pattern of the pixel cutout unit 100 output as it is to the 4-connection label determination logic 210 at the time of 4-connection selection command, and the pixel e of the mask pattern 12 at the time of 8-connection selection command. As the point of interest, when the image information (high-level signal) is present in the area of the mask pattern 12 that is associated with only 8 connections, the image information is present in the area that is associated with only 4 connections of the point of interest e. Even without doing so, mask pattern data in which image information is forcibly assigned to the area is generated.

That is, when the signals from the pixel conversion unit 400 are respectively supplied to the 4-connected label determination logic 210, the pixel cutout unit 100 outputs the mask pattern data at the time of 4-connection as shown in FIG.
When it matches with the pattern shown in FIG. 7, it is determined that a new label has been generated. When 8 patterns are connected, when it matches with the pattern shown in FIG. It should be noted that the ∘ mark indicates a high level, the X mark indicates either a high level or a low level, and a blank region indicates a low level.

Further, when the mask pattern matches (C) or (E) during 4-connection, the pixel e of interest is labeled with the same label as a or c as the propagation from a or the propagation from c. Further, when the pattern of (G) coincides with four connections, e is labeled with the same label as pixels a and c as a confluence of pixels a and c.

On the other hand, in the case of the mask pattern as shown in FIG. 7D, the pixel e of interest is related only by 8 connections, but by the processing of the pixel conversion unit 400, the area of the pixel d is labeled with a circle. Is attached. Further, as shown in (F), the pixels e and c are related only by 8 connections, but the image conversion unit
By the process of 400, the region of the pixel (f) is forcibly labeled with a circle. Therefore, the mask pattern of (D) matches the mask pattern of (C), and the mask pattern of (F) matches the mask pattern of (E). Furthermore, in the pattern shown in (H), the area of the pixels d and f is forcibly converted to a circle by the same processing.
This will match the mask pattern of (G). Then, these determination results are output to the label generating unit 300, respectively, and the label generating unit 300 outputs the 4-connected label determining logic 2
A label signal corresponding to the determination result of 10 is output. For example, the pixel e of interest when it is determined to propagate from a
A signal for labeling the pixel a with is output.

In the above configuration, when 4-link is selected when the digital image signal of the original image shown in FIG. 8A is supplied to the pixel cutout unit 100, the label generation unit 300 shows the result as shown in FIG. A label signal as shown in (C) is output when 8-link is selected.

When the mask pattern data is composed of 2 × 3 pixels,
Although it is necessary to perform label determination with ²⁶ combinations, it is possible to simplify the logic circuit because the label determination logic can be configured with a single one. Therefore, it becomes easy to form a logic circuit into an LSI.

〔The invention's effect〕

According to the present invention, since 4-connection and 8-connection can be labeled with a single logic, the logic circuit of the labeling processor can be simplified.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of the present invention, FIG. 2 is a diagram for explaining labeling processing, FIG. 3 is a configuration diagram of a mask pattern, FIG. 4 is a configuration diagram of a conventional example, and FIG. FIG. 6 is a diagram showing the configuration of the pixel conversion unit 400, FIG. 7 is a diagram showing the configuration of the 4-connected label determination logic, and FIG. 8 is a diagram showing an example of labeling by the processor according to the present invention. is there. 100 ... Pixel cut-out section, 110 ... Connector signal, 200A ... Label determination section, 210 ... 4-connected label determination logic, 300 ... Label generation section, 400 ... Pixel conversion section, 410, 420 ... OR gate, 430, 440 ...... AND gate.

Claims (1)

[Claims] 1. A pixel cutout unit for converting a digital image signal into mask pattern data of m × n pixels, and a mask pattern data output from the pixel cutout unit is transmitted as it is according to a 4-connection selection command, and an 8-connection selection command is sent. As a result, when pixel information exists in a region of the mask pattern that is associated with only 8 connections, using a specific pixel in the mask pattern as an attention point, an image is displayed in a region that is associated with only 4 connections of the attention point. Pixel conversion unit that outputs mask pattern data forcibly allocating image information to the area even if information does not exist, new label generation pattern data and label propagation pattern by mask pattern data output from the pixel conversion unit and 4-connection Data and the label merging pattern data are compared with each other, and the mask pattern data is Labeling processor, characterized in that it comprises a determining label determining unit that determines whether belonging to the data, and a label generator for generating a label signal according to the determination result of the label determination section.