JPH07101676B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH07101676B2 JPH07101676B2 JP2048548A JP4854890A JPH07101676B2 JP H07101676 B2 JPH07101676 B2 JP H07101676B2 JP 2048548 A JP2048548 A JP 2048548A JP 4854890 A JP4854890 A JP 4854890A JP H07101676 B2 JPH07101676 B2 JP H07101676B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- diffusion
- semiconductor substrate
- impurities
- impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 35
- 238000000034 method Methods 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000012535 impurity Substances 0.000 claims description 56
- 238000009792 diffusion process Methods 0.000 claims description 53
- 239000000758 substrate Substances 0.000 claims description 27
- 238000010438 heat treatment Methods 0.000 claims description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 14
- 229910052796 boron Inorganic materials 0.000 description 14
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Landscapes
- Thyristors (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】 (イ) 産業上の利用分野 この発明は、半導体素子の製造方法、特に不純物拡散方
法に特徴を有する半導体素子の製造方法に関する。TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor element, and more particularly to a method for manufacturing a semiconductor element characterized by an impurity diffusion method.
(ロ) 従来の技術 従来、半導体基板に基板の表裏両面から不純物拡散を行
い、アイソレーション層を得る場合には、不純物マスク
として酸化膜(SiO2)を使用し、高温拡散を行う。その
処理過程を第5図(a)〜第5図(b)により説明する
と、先ずシリコン(Si)の半導体基板1の両面に酸化膜
2、3を形成し〔第5図(a)〕、次にフォトリゾ技術
等を用い、拡散すべき領域4の酸化膜2、3を除去し
(第5図(b)〕、さらに酸化膜2、3及び酸化膜除去
部4の上面に、ボロン等の不純物5、6を塗布し〔第5
図(c)〕、1270℃の高温で長時間に亘り、拡散領域7
と下の拡散領域8が連通するまで、拡散処理を行う。通
常酸化膜は5000〜8000Å程度の厚さであるが、ここでの
高温処理、そして、長時間の処理なので15000Å〜20000
Å程度に厚くし、拡散終了後に、表面を全面エッチング
して、つまり表面の酸化膜を一部除去し、ボロンリッチ
層を除去している。(B) Conventional Technology Conventionally, when impurity diffusion is performed on a semiconductor substrate from both front and back surfaces of the substrate to obtain an isolation layer, an oxide film (SiO 2 ) is used as an impurity mask and high temperature diffusion is performed. The process will be described with reference to FIGS. 5 (a) to 5 (b). First, oxide films 2 and 3 are formed on both surfaces of a semiconductor substrate 1 made of silicon (Si) [FIG. 5 (a)]. Next, the oxide films 2 and 3 in the region 4 to be diffused are removed by using a photolithography technique or the like (FIG. 5B), and further boron or the like is deposited on the upper surfaces of the oxide films 2 and 3 and the oxide film removing portion 4. Apply impurities 5 and 6 [Fifth
(Fig. (C)], at a high temperature of 1270 ° C for a long time, the diffusion region 7
The diffusion process is performed until the lower diffusion region 8 and the lower diffusion region 8 communicate with each other. Normally, the oxide film is about 5000 ~ 8000Å, but since it is a high temperature process here and a long time process, it is 15000 ~ 20000
After the diffusion is completed, the entire surface is etched, that is, the oxide film on the surface is partially removed and the boron-rich layer is removed.
(ハ) 発明が解決しようとする課題 上記した従来の高温拡散では、高温で長時間に亘る処理
が続くため、酸化膜が不純物(ボロン)と反応し、酸化
膜にピンホールが多く発生し(第4図参照)、このピン
ホールにより酸化膜の絶縁耐圧が悪化し、ショート等に
よる歩留りを低下させるという問題があった。(C) Problems to be Solved by the Invention In the conventional high temperature diffusion described above, since the treatment continues at high temperature for a long time, the oxide film reacts with impurities (boron), and many pinholes are generated in the oxide film ( (See FIG. 4), however, there is a problem that the withstand voltage of the oxide film deteriorates due to this pinhole, and the yield due to a short circuit or the like decreases.
この発明は、上記問題点に着目してなされたものであっ
て、高温拡散における酸化膜と不純物との反応を防止
し、ピンホールの発生を軽減し、歩留りの良い半導体素
子の製造方法を提供することを目的としている。The present invention has been made in view of the above problems, and provides a method for manufacturing a semiconductor device which prevents a reaction between an oxide film and impurities in high temperature diffusion, reduces the occurrence of pinholes, and has a high yield. The purpose is to do.
(ニ) 課題を解決するための手段及び作用 この発明の半導体素子の製造方法は、半導体基板上に酸
化膜を形成し、次に拡散すべき領域の酸化膜を除去し、
その後、前記半導体基板の酸化膜及び酸化膜除去部上面
に不純物を塗布し、1000℃〜1300℃の温度で加熱して第
1の不純物拡散を行い、次に酸化膜上の不純物層の除去
処理を行い、続いて1000℃〜1300℃の温度で100時間〜2
00時間の加熱による第2の不純物拡散を行い、半導体基
板内に拡散領域を形成するようにしている。(D) Means and Actions for Solving the Problems A method for manufacturing a semiconductor device according to the present invention is to form an oxide film on a semiconductor substrate and then remove the oxide film in a region to be diffused.
After that, impurities are applied to the oxide film and the upper surface of the oxide film removal portion of the semiconductor substrate, the first impurity diffusion is performed by heating at a temperature of 1000 ° C. to 1300 ° C., and then the impurity layer on the oxide film is removed. And then for 100 hours to 2 at a temperature of 1000 ° C to 1300 ° C.
The second impurity diffusion is performed by heating for 00 hours to form a diffusion region in the semiconductor substrate.
この半導体素子の製造方法は、処理時間が数十分と比較
的短い第1の不純物拡散の後で、酸化膜上の不純物層の
除去処理を行い、高温長時間の第2の不純物拡散に入る
前に酸化膜上の不純物がすでに除去されているので、高
温長時間の不純物拡散に入っても、酸化膜と不純物の反
応が少なくなり、酸化膜におけるピンホールの発生が軽
減される。In this semiconductor element manufacturing method, after the first impurity diffusion, which has a relatively short processing time of several tens of minutes, the impurity layer on the oxide film is removed, and the second impurity diffusion is performed at a high temperature for a long time. Since the impurities on the oxide film have already been removed, the reaction between the oxide film and the impurities is reduced even if the diffusion of the impurities at a high temperature for a long time is started, and the occurrence of pinholes in the oxide film is reduced.
(ホ) 実施例 以下、実施例により、この発明を詳細に説明する。(E) Examples Hereinafter, the present invention will be described in detail with reference to Examples.
第1図(a)乃至第1図(f)は、この発明の一実施例
を示し、半導体基板にSCR用のアイソレーション層を形
成するための拡散処理過程を示す半導体基板の断面図で
ある。1 (a) to 1 (f) are cross-sectional views of a semiconductor substrate showing an embodiment of the present invention and showing a diffusion process for forming an isolation layer for SCR on the semiconductor substrate. .
シリコン(Si)の半導体基板1の両面に酸化膜2、3を
形成すること〔第1図(a)〕、拡散すべき領域4の酸
化膜2、3を除去すること〔第1図(b)〕、酸化膜
2、3及び酸化膜除去部4の上面にボロン等の不純物
5、6を塗布すること〔第1図(b)〕は、第5図
(a)、第5図(b)、第5図(c)に示した従来方法
と同様である。ここで、ボロンソースとしては、PBF
(ポリボロンフィルム)、BN、BCl3等が使用される。Forming oxide films 2 and 3 on both surfaces of a semiconductor substrate 1 made of silicon (Si) [FIG. 1 (a)], and removing oxide films 2 and 3 in a region 4 to be diffused [FIG. 1 (b)]. )], And applying impurities 5 and 6 such as boron to the upper surfaces of the oxide films 2 and 3 and the oxide film removing portion 4 [FIG. 1 (b)] are shown in FIGS. 5 (a) and 5 (b). ), The same as the conventional method shown in FIG. Here, as the boron source, PBF
(Polyboron film), BN, BCl 3 etc. are used.
この実施例の特徴は、いきなり、高温長時間の拡散処理
に移らず、30〜60分程度の比較的短時間の不純物拡散を
行い、半導体基板1の酸化膜除去部4より、半導体基板
ウェハ1に拡散領域7、8の成長を開始させる〔第1図
(d)〕。この処理における温度プロセスの一例を示す
と、第2図(a)に示す通りである。半導体基板1を加
熱炉に入れて、温度1270℃における加熱30〜60分で半導
体基板(ウェハ)1を加熱炉から出し、次に今度は酸化
膜除去部4をマスクして、酸化膜2、3上をフォトリゾ
方式でエッチングし、酸化膜2、3上のボロンソースを
除去する〔第1図(e)〕。このフォトリゾ・エッチン
グでは、逆に酸化膜除去部4がマスクされるので、この
部分におけるボロン層はエッチングされず、ボロン層が
減らないので、後のボロンの押込みに有効である。次
に、半導体基板1を再度加熱炉に入れ、第2図の不純物
拡散処理を行い、ボロンの押込みを行う。この処理にお
ける温度プロセスの一例を示すと第2図(b)に示す通
りであり、1270℃の高温で170Hr〜190Hrの長時間に亘り
加熱を行う。これによりボロンの拡散領域としてx=10
0μ〜120μの押入れが可能となり、半導体基板1の上面
よりの拡散領域7と下面よりの拡散領域8が連結され、
アイソレーション層9が形成される〔第1図(f)〕。The feature of this embodiment is that the impurity diffusion is carried out for a relatively short time of about 30 to 60 minutes without changing to the high temperature and long time diffusion treatment, and the semiconductor substrate wafer 1 is removed from the oxide film removing portion 4 of the semiconductor substrate 1. Then, the growth of the diffusion regions 7 and 8 is started [Fig. 1 (d)]. An example of the temperature process in this process is as shown in FIG. The semiconductor substrate 1 is put in a heating furnace, and the semiconductor substrate (wafer) 1 is taken out of the heating furnace at a temperature of 1270 ° C. for 30 to 60 minutes. Next, the oxide film removing portion 4 is masked to remove the oxide film 2, 3 is photolithographically etched to remove the boron source on the oxide films 2 and 3 [FIG. 1 (e)]. On the contrary, in this photolithographic etching, the oxide film removing portion 4 is masked, so that the boron layer in this portion is not etched and the boron layer is not reduced, which is effective for the subsequent boron indentation. Next, the semiconductor substrate 1 is put into the heating furnace again, the impurity diffusion process shown in FIG. 2 is performed, and boron is pushed in. An example of the temperature process in this treatment is shown in FIG. 2B, and heating is performed at a high temperature of 1270 ° C. for a long time of 170 hours to 190 hours. As a result, x = 10 as a boron diffusion region.
It is possible to press 0 μ to 120 μ, and the diffusion region 7 from the upper surface of the semiconductor substrate 1 and the diffusion region 8 from the lower surface are connected,
The isolation layer 9 is formed [FIG. 1 (f)].
ここで、高温長時間の第2の不純物拡散に先立って第1
の不純物拡散を行う理由について記載する。前記したよ
うに、不純物拡散を長時間連続して行うと、第1図にお
いて、酸化膜2,3上に付着する不純物5,6が酸化膜2,3と
反応してしまい、酸化膜2,3にピンホール等が生じると
いった不具合が起こる。これを防ぐために、まず不純物
5,6を1000〜1300℃で30〜60分程度加熱し、半導体基板
1の拡散領域7,8内にそれぞれ不純物5,6をドープさせ
る。このドープ時には、拡散時間が比較的短時間である
ため、酸化膜2,3と不純物5,6との反応は殆ど起こらな
い。Here, prior to the second impurity diffusion for a long time at high temperature,
The reason for performing the impurity diffusion of is described. As described above, when the impurity diffusion is continuously performed for a long time, in FIG. 1, the impurities 5 and 6 attached on the oxide films 2 and 3 react with the oxide films 2 and 3, and the oxide film 2 and Problems such as pinholes on 3 occur. To prevent this, firstly impurities
5 and 6 are heated at 1000 to 1300 ° C. for about 30 to 60 minutes to dope the diffusion regions 7 and 8 of the semiconductor substrate 1 with impurities 5 and 6, respectively. During this doping, since the diffusion time is relatively short, the reaction between the oxide films 2 and 3 and the impurities 5 and 6 hardly occurs.
そして、酸化膜2,3上に付着した不純物5,6を除去した
後、拡散領域7,8内にドープされた不純物のみを、第2
の不純物拡散により基板1内に深く拡散させていくので
ある。この際、拡散領域7,8内の不純物だけでは不純物
の拡散量が不十分な場合があるので、酸化膜除去部4に
は不純物5,6を残しておき、第2の不純物拡散時の不純
物の押し込みに有効とするのである。勿論、第2の不純
物拡散時には、酸化膜2,3上に不純物5,6は存在しないた
め、酸化膜と不純物との反応は起こらない。このよう
に、第2の不純物拡散の前に第1の不純物拡散を行うこ
とで、酸化膜におけるピンホール等の発生が軽減される
のである。Then, after removing the impurities 5 and 6 attached on the oxide films 2 and 3, only the impurities doped in the diffusion regions 7 and 8 are removed by the second etching.
The impurities are diffused deeply into the substrate 1. At this time, the impurities in the diffusion regions 7 and 8 may not be sufficient in the amount of diffusion of the impurities. Therefore, the impurities 5 and 6 are left in the oxide film removing portion 4, and the impurities at the time of the second impurity diffusion are used. It is effective for pushing in. Of course, at the time of the second impurity diffusion, the impurities 5 and 6 do not exist on the oxide films 2 and 3, so that the reaction between the oxide film and the impurities does not occur. By thus performing the first impurity diffusion before the second impurity diffusion, the occurrence of pinholes and the like in the oxide film is reduced.
なお、上記実施例において、第1の不純物拡散、第2の
不純物拡散とも、1000〜1300℃の加熱温度で実用的であ
る。また、第2の不純物拡散における時間は、拡散幅に
より100〜200時間の範囲で選択すればよい。In the above embodiment, both the first impurity diffusion and the second impurity diffusion are practical at a heating temperature of 1000 to 1300 ° C. The time for the second impurity diffusion may be selected within the range of 100 to 200 hours depending on the diffusion width.
以上のようにしてアイソレーション層9が形成される半
導体基板1は、高温長時間の拡散時に酸化膜2、3上の
不純物層、つまりボロンソースが除去されているので酸
化膜2、3とボロンとの反応する度合が少なく、したが
って半導体基板1上に生じるピンホールも少ない。概略
的に、この実施例方法により得られた半導体ウェハ(基
板)1のピンホール10は第3図(a)に示す状態であ
り、ボート位置とオリフラ部に若干発生する程度であ
り、90〜95%の歩留りが得られた。従来方法による半導
体ウェハ1のピンホールが第3図(b)に示すようにウ
ェハ全体面にピンホール10が生じ、歩留りも40〜70%程
度であると比較すると格段の好結果を得ている。In the semiconductor substrate 1 on which the isolation layer 9 is formed as described above, the impurity layers on the oxide films 2 and 3, that is, the boron source is removed at the time of diffusion at high temperature for a long time. The degree of reaction with is small, and therefore the number of pinholes formed on the semiconductor substrate 1 is also small. Schematically, the pinholes 10 of the semiconductor wafer (substrate) 1 obtained by the method of this embodiment are in the state shown in FIG. 3 (a), which is slightly generated at the boat position and the orientation flat portion. A yield of 95% was obtained. The pinhole 10 of the semiconductor wafer 1 produced by the conventional method has a pinhole 10 on the entire surface of the wafer as shown in FIG. 3 (b), and the yield is about 40 to 70%. .
また、第4図(a)に示すように、本発明をSCRに実施
した場合の高温逆バイアス時のQAT(信頼性評価時間)
−IDRM(ピークオフ電圧の漏れ電流)の特性は、第4図
(b)に示す従来例による場合に比べ、はるかに変動幅
が小さい結果を得ている。Further, as shown in FIG. 4 (a), QAT (reliability evaluation time) at high temperature reverse bias when the present invention is applied to SCR.
With respect to the characteristic of −I DRM (leakage current of peak off voltage), the variation width is much smaller than that of the conventional example shown in FIG. 4 (b).
また、上記実施例では、酸化膜上の不純物層を除去する
のに、フォトリゾ・エッチング方式を採用しているが、
これに代えてフッ酸ライト・エッチングにより酸化膜上
のボロンリッチ層を除去してもよい。Further, in the above embodiment, the photolithographic etching method is used to remove the impurity layer on the oxide film.
Alternatively, the boron rich layer on the oxide film may be removed by hydrofluoric acid light etching.
(ヘ) 発明の効果 この発明によれば、1000℃〜1300℃の温度で加熱して第
1の不純物拡散を行い、次に酸化膜上の不純物層の除去
処理を行い、続いて1000℃〜1300℃の温度で100時間〜2
00時間の加熱による第2の不純物拡散を行い、半導体基
板内に拡散領域を形成するようにしているので、長時間
に亘る高温拡散時は、不純物が酸化膜上から除去されて
おり、したがって酸化膜と不純物との反応も少なく、ピ
ンホールの発生も軽減される。そのため、酸化膜の膜質
が向上し、信頼性試験、バイアス試験等に強くなり、ま
た耐圧不良による歩留り低下も格段に改善される。(F) Effect of the Invention According to the present invention, the first impurity diffusion is performed by heating at a temperature of 1000 ° C. to 1300 ° C., then the impurity layer on the oxide film is removed, and then the temperature of 1000 ° C. 100 hours ~ 2 at a temperature of 1300 ℃
Since the second impurity diffusion is performed by heating for 00 hours to form the diffusion region in the semiconductor substrate, the impurities are removed from the oxide film during the high temperature diffusion for a long time, and thus the oxidation is performed. The reaction between the film and impurities is small, and the occurrence of pinholes is reduced. Therefore, the film quality of the oxide film is improved, the reliability test, the bias test, and the like are strengthened, and the yield reduction due to the withstand voltage failure is remarkably improved.
第1図(a)、第1図(b)、第1図(c)、第1図
(d)、第1図(e)及び第1図(f)は、この発明の
一実施例を示す拡散処理過程を説明するための半導体基
板の断面図、第2図(a)は、同処理過程における第1
の不純物拡散の温度プロセス例を示す図、第2図(b)
は、同処理過程における第2の不純物拡散の温度プロセ
ス例を示す図、第3図(a)は、同実施例により得られ
た半導体ウェハのピンホール分布を示す図、第3図
(b)は、従来方法の実施で得られた半導体ウェハのピ
ンホール分布を示す図、第4図(a)は、上記実施例に
より製造したSCRのQAT−IDRM特性を示す図、第4図
(b)は、従来例により得られたSCRのQTA−IDRM特性を
示す図、第5図(a)、第5図(b)、第5図(c)及
び第5図(d)は、従来の不純物拡散処理過程を説明す
るための半導体基板の断面図である。 1:半導体基板、2・3:酸化膜、4:酸化膜除去部、5・6:
ボロン層、7・8:拡散領域。1 (a), 1 (b), 1 (c), 1 (d), 1 (e) and 1 (f) show an embodiment of the present invention. FIG. 2A is a cross-sectional view of the semiconductor substrate for explaining the diffusion process shown in FIG.
FIG. 2B is a diagram showing an example of a temperature process of impurity diffusion of Al.
Is a diagram showing a temperature process example of the second impurity diffusion in the same process, FIG. 3 (a) is a diagram showing pinhole distribution of the semiconductor wafer obtained by the same embodiment, and FIG. 3 (b). FIG. 4 is a diagram showing a pinhole distribution of a semiconductor wafer obtained by carrying out the conventional method, FIG. 4 (a) is a diagram showing the QAT-I DRM characteristics of the SCR manufactured by the above-mentioned embodiment, FIG. ) Is a diagram showing the QTA-I DRM characteristics of the SCR obtained by the conventional example, and FIGS. 5 (a), 5 (b), 5 (c) and 5 (d) are conventional. FIG. 6 is a cross-sectional view of a semiconductor substrate for explaining the impurity diffusion treatment process of FIG. 1: Semiconductor substrate, 2.3: Oxide film, 4: Oxide film removal part, 5: 6:
Boron layer, 7/8: Diffusion region.
Claims (1)
すべき領域の酸化膜を除去し、その後、前記半導体基板
の酸化膜及び酸化膜除去部上面に不純物を塗布し、1000
℃〜1300℃の温度で加熱して第1の不純物拡散を行い、
次に酸化膜上の不純物層の除去処理を行い、続いて1000
℃〜1300℃の温度で100時間〜200時間の加熱による第2
の不純物拡散を行い、半導体基板内に拡散領域を形成す
るようにした半導体素子の製造方法。1. An oxide film is formed on a semiconductor substrate, the oxide film in a region to be diffused next is removed, and thereafter, an impurity is applied to the oxide film and the upper surface of the oxide film removing portion of the semiconductor substrate.
℃ ~ 1300 ℃ to heat the first impurity diffusion,
Next, the impurity layer on the oxide film is removed, and then 1000
Second by heating for 100 to 200 hours at a temperature of ℃ to 1300 ℃
And a method for manufacturing a semiconductor element, wherein a diffusion region is formed in a semiconductor substrate by performing the impurity diffusion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2048548A JPH07101676B2 (en) | 1990-02-28 | 1990-02-28 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2048548A JPH07101676B2 (en) | 1990-02-28 | 1990-02-28 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03250729A JPH03250729A (en) | 1991-11-08 |
| JPH07101676B2 true JPH07101676B2 (en) | 1995-11-01 |
Family
ID=12806429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2048548A Expired - Lifetime JPH07101676B2 (en) | 1990-02-28 | 1990-02-28 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07101676B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016189411A (en) * | 2015-03-30 | 2016-11-04 | 新電元工業株式会社 | Semiconductor device manufacturing method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55143031A (en) * | 1979-04-25 | 1980-11-08 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS58175845A (en) * | 1982-04-07 | 1983-10-15 | Mitsubishi Electric Corp | Structure of isolation diffusion region in semiconductor device |
| JPS63117419A (en) * | 1986-11-06 | 1988-05-21 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1990
- 1990-02-28 JP JP2048548A patent/JPH07101676B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03250729A (en) | 1991-11-08 |
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