JPH07101683B2 - Method for forming pattern of semiconductor device - Google Patents

Description

The present invention relates to a pattern forming method for a semiconductor device, and particularly to a pattern forming method useful when the pattern is sparse.

[Conventional technology]

According to the conventional pattern forming method, when forming a circuit pattern as shown in FIG. 4, a known resist is used so that the same shape as the predetermined circuit patterns 2a and 2b remains in the circuit pattern formation planned region of the semiconductor substrate 1. It is formed by a lithography technique, and the layer to be etched is etched using this resist as a mask to obtain a desired circuit pattern.

However, when the circuit pattern formed on the surface of the semiconductor substrate 1 is sparse, the circuit pattern portion 4 which is not originally etched by being coated with the resist 3 is over-etched as shown in FIG. Four
A phenomenon occurs in which the resist 3 remains on the upper surface of the above in an overhang state.

In the anisotropic etching, the circuit pattern portion 4 coated with the resist 3 is not laterally etched,
Normally, only the layer to be etched 5 in the direction perpendicular to the resist is etched, but when the circuit pattern is sparsely formed, the over-etched state shown in FIG. 5 occurs next. It is thought that this is because of the phenomenon described.

FIG. 6 shows an etching progress model when the layer to be etched 5 is etched by anisotropic etching such as reactive ion etching (RIE).

In this case, a part of the resist 3 used for forming the circuit pattern portion 4 is decomposed by etching ions and the decomposed product is supplied to the surface of the layer to be etched 5,
The protective film 6 is formed to prevent abnormal etching. When such a protective film is formed, the side surface of the circuit pattern portion 4 is also covered with this protective film to prevent the etching from proceeding laterally. Therefore, if the resist 3 is appropriately decomposed, overetching as shown in FIG. 5 is unlikely to occur.

However, when the circuit pattern is sparse, as shown in FIG. 7, the decomposition products from the resist 3 are very small and do not sufficiently spread on the surface of the etching layer 5, so that a very thin protective film 7 is formed. Only Therefore, despite the anisotropic etching such as RIE, the lateral etching proceeds, and the side surface of the circuit pattern portion 4 is thus overetched. Especially when attempting to form a fine circuit pattern, if this lateral overetching with respect to the set dimension occurs, a desired pattern is not formed, which is a fatal problem in semiconductor manufacturing.

[Problems to be solved by the invention]

As described above, in the conventional pattern forming method, when the sparse circuit pattern is formed, the so-called etching conversion difference is large when the ratio of the surface of the layer to be etched facing the etching ions to the etching rate in the lateral direction orthogonal to the etching surface is large. There was a problem of becoming. Therefore, it is an object of the present invention to provide a pattern forming method capable of forming a circuit pattern while maintaining a small etching conversion difference even when forming a sparse circuit pattern.

[Structure of Invention]

(Means for Solving the Problems) In the pattern forming method according to the present invention, a first matrix portion of a matrix in which a semiconductor element to be formed is a unit on a semiconductor substrate or a layer to be etched formed on the semiconductor substrate. Has a device forming resist pattern for forming a desired circuit, and a full surface resist pattern for forming a protective film by a resist decomposed product on the surface to be etched during anisotropic etching in the remaining second matrix portion. A step of forming a first resist placement pattern, a step of performing a first anisotropic etching using the first resist placement pattern, and a step of completing the first anisotropic etching after removing the residual resist. An element for forming a desired circuit of the second matrix portion on a later semiconductor substrate or an etching target layer formed on the latter semiconductor substrate. A step of forming a child-forming resist pattern and a second resist arrangement pattern having an entire surface resist pattern for forming a protective film by a resist decomposed product on a surface to be etched during anisotropic etching in the first matrix portion. And a step of performing second anisotropic etching using the second resist arrangement pattern.

The first resist arrangement pattern is a pattern in which the element formation patterns are arranged in a checkered pattern, and the second resist arrangement pattern is formed on the entire surface resist pattern position in the first resist arrangement pattern. It is preferable that the pattern is a checkered pattern.

(Operation) The waving is performed using the first resist arrangement pattern including the element formation pattern and the entire surface resist pattern serving as a resist supply source necessary for forming the protective film, using the elements formed in a matrix as a unit. After performing the anisotropic etching for the second time and subsequently removing the resist, the anisotropic etching for the second time is performed by the second resist arrangement pattern in which the arrangement of the element formation pattern and the entire surface resist pattern are exchanged. . As a result, the resist decomposition product is sufficiently supplied to the surface of the layer to be etched from the entire surface resist pattern serving as the resist supply source at the time of each etching to form the protective film, so that arbor etching does not occur.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a pattern layout diagram showing an example related to the principle underlying the present invention. When the circuit patterns 12a, 12b for forming gate electrodes are to be formed in a sparse state on the polysilicon layer formed on the surface of the semiconductor substrate 1, a resist pattern other than the resist patterns corresponding to the circuit patterns 2a, 2b is used. A resist pattern 13 serving as a supply source is provided. In this case, the pattern 13 serving as the resist supply source
The case where it is provided in the chip is shown. If such a pattern configuration is adopted, even if the circuit patterns 12a and 12b are arranged in a sparse state, a resist pattern is formed during etching.
Since the resist decomposed product is supplied from 13 onto the surface of the layer to be etched of the circuit patterns 12a and 12b to form a protective film, overetching is prevented and normal etching can be realized. Although the resist pattern 13 forms a polysilicon pattern corresponding to this, if it is originally formed when there is no adverse effect on the circuit, it can be left as it is, and an unnecessary pattern exists. If this is not preferable in terms of the circuit, the unnecessary pattern may be removed again by masking the circuit pattern portion after the etching is completed.

FIG. 2 is a pattern layout diagram showing an embodiment of the present invention. When lithography is performed, a stepper is used for each shot, or a projection exposure apparatus is used, for each chip, an exposed portion 21 and an unexposed portion 22 of a circuit pattern are alternately provided.
As a result, since the resist is left on the entire surface in the unexposed portion 22, the circuit pattern and the entire surface pattern are alternately arranged in a checkered pattern on the wafer in which the chips are arranged in a matrix in a unit. A pattern layout is obtained. The entire pattern functions as a resist supply source during etching.

Therefore, a sufficient protective film is supplied at the time of etching the exposed portion 21, and normal etching can be realized.

Next, after completely removing the resist, the resist is applied again to the entire surface, and a circuit pattern is formed by etching according to a pattern in which the positions of the exposed portion and the non-exposed portion are exchanged.
At this time as well, the resist remains on the entire surface where the circuit pattern has already been formed, so that this serves as a supply source of the resist during anisotropic etching, and normal etching is performed. In the pattern realized in this way, as shown in FIG. 3, the circuit pattern portion 4 below the resist 3 can form a normal pattern with a small conversion difference without being over-etched in the lateral direction.

Therefore, a fine pattern can be accurately formed.

In the embodiment, the element formation pattern and the entire surface resist pattern are arranged in a checkered pattern in the matrix portion in which the element is a unit. However, the first resist arrangement pattern used for the first etching and the element formation pattern are used. And the number of chips to be etched in the second resist pattern in which the positions of the entire surface resist pattern are exchanged are substantially equal to each other, and the chips to be etched and the chips serving as the resist supply source are arranged substantially evenly. It may be a pattern.

〔The invention's effect〕

As described above in detail with reference to the embodiments, according to the present invention, the semiconductor element is used as a unit and the element formation pattern is arranged in the first matrix portion, and the entire surface resist pattern is arranged in the remaining second matrix portion. The resist pattern and the pattern in which these positions are exchanged are used to perform the etching twice in order to secure the supply source of the resist necessary for forming the protective film on the surface to be etched during etching. Therefore, during each anisotropic etching, a sufficient amount of resist decomposed product is supplied from the entire surface resist pattern to form a protective film on the surface to be etched, so that overetching does not proceed and a fine circuit pattern is formed. Even a semiconductor device having the same can accurately form a highly accurate pattern.

[Brief description of drawings]

FIG. 1 is a pattern layout diagram showing an example related to the present invention, FIG. 2 is a pattern layout diagram showing an embodiment of the present invention, FIG. 3 is an element sectional view when normal etching is realized, and FIG. FIG. 5 is a pattern layout diagram showing the arrangement of sparse circuit patterns, FIG. 5 is a sectional view showing an over-etched state, FIG. 6 is an etching model diagram for explaining the principle of etching, and FIG. 7 is a sparse circuit pattern. FIG. 3 is a model diagram for explaining the etching state of FIG. 1,11 ……
Semiconductor substrate, 2a, 2b, 12a, 12b ... Circuit pattern, 3 ...
Resist, 4 ... Circuit pattern part, 5 ... Etched layer, 6 ... Protective film, 13 ... Resist supply part, 21 ... Exposed circuit pattern part, 22 ... Unexposed circuit pattern part.

Claims (2)

[Claims] 1. An element forming resist pattern for forming a desired circuit on a first matrix portion of a matrix including a semiconductor element to be formed as a unit on a semiconductor substrate or a layer to be etched formed on the semiconductor substrate. And a step of forming a first resist arrangement pattern having an entire surface resist pattern for forming a protective film by a resist decomposed product on the surface to be etched during anisotropic etching in the remaining second matrix portion, A step of performing a first anisotropic etching using the first resist arrangement pattern, and a semiconductor substrate after completion of the first anisotropic etching after removing the residual resist or an etching target formed on the semiconductor substrate An element forming resist pattern for forming a desired circuit on the second matrix portion on the layer, and the first matrix. A step of forming a second resist arrangement pattern having an entire surface resist pattern for forming a protective film by a resist decomposition product on the surface to be etched at the time of anisotropic etching, and using the second resist arrangement pattern And a step of performing second anisotropic etching. 2. The first resist arrangement pattern is a pattern in which the element formation patterns are arranged in a checkered pattern, and the second resist arrangement pattern is a full-face resist pattern in the first resist arrangement pattern. The pattern formation method for a semiconductor device according to claim 1, wherein the element formation patterns are arranged in a checkered pattern at positions.