JPH07101715B2 - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, and in particular, a CMOS element composed of a p-channel MOS element and an n-channel MOS element and a bipolar element on the same chip. The present invention relates to a so-called Bi-CMOS integrated circuit device formed and a manufacturing method thereof.

[Conventional technology]

Generally, a bipolar element has a large drive capacity per occupied chip area, has high accuracy in analog amount processing, but has a low degree of integration and consumes a large amount of power. On the other hand, CMOS devices have the characteristics of low power consumption and high integration. Therefore, on a chip consisting mainly of bipolar devices, a CMOS that supplements the above-mentioned drawbacks of bipolar devices
It is effective to incorporate an element, and a typical example is a static RAM (random access memory (R
andom Access Memory)) has already been commercialized, and further B
Gate array LSIs using i-CMOS are sold.

Among such conventional Bi-CMOS integrated device devices, a method of manufacturing an npn transistor as a bipolar device will be described with reference to FIG.

First, as shown in FIG. 3 (A), a p-type silicon substrate 1
After forming the buried layer 2 having a high n-type impurity concentration, an epitaxial layer 3 having a low n-type impurity concentration is grown.

Next, selective oxidation is performed using an oxidation resistant film (not shown) as a mask to form a thick oxide film 101 for electrically separating the element formation portions of the epitaxial layer 3 from each other. Here, the case where the oxide film separation method is used will be described, but the same can be said for other separation methods such as the pn junction separation method. Furthermore, after p-type impurity diffusion is performed in the epitaxial layer 3 of the MOS transistor formation portion to form the p-well layer 4 and the gate oxide film 102 is grown,
N-type high-concentration polycrystalline silicon film for gate electrode
Form 201. Here, in addition to the polycrystalline silicon film, a silicide film (MoSi ₂ , WSi ₂ ) and a composite film thereof may be used as the gate electrode.

Next, as shown in FIG. 3 (B), n-type high impurity concentration implantation is performed using the resist film 301 and the gate electrode 201 as a mask to form the source layer 6, drain layer 7 and collector electrode of the n-channel MOS. The take-out layer 5 is formed.

Next, as shown in FIG. 3 (C), a new resist film 30
Using the gate electrode 201 and 2 as a mask, p-type impurity concentration is implanted to form the source layer 9, drain layer 10 and external base layer 8 of the p-channel MOS.

Next, as shown in FIG. 3D, a p-type low impurity concentration is implanted using a new resist film (not shown) as a mask to deposit a passivation film 401 such as a phosphorus glass film. Then, the active base layer 11a is formed by annealing while also tightening the passivation 401. By this annealing, the source layer, the drain layer, the external base layer, and the collector electrode extraction layer of the p-channel and n-channel MOS are simultaneously activated to form their respective diffusion layers. Here, annealing may be performed individually, but generally they are collectively performed to simplify the process.

Next, as shown in FIG. 3E, contacts for taking out electrodes of the source layer 6a and the drain layer 7a of the n-channel MOS are formed, and the n-type high impurity layers 12 and 13 are formed therein by diffusion. . It is desirable that the source / drain layer be formed as shallow as possible in order to improve the performance of the n-channel MOS transistor, and arsenic (As) having a small diffusion coefficient is used as the impurity, but the junction is not so good. If it becomes too shallow, the electrode layer material will have a large diffusion coefficient across the junction due to the distortion of the thick oxide film 101 in the feed portion and the effect of the edge of the contact hole, causing a short circuit with the substrate when the electrode material abnormally diffuses. This is because impurities such as phosphorus (P) are injected and diffused at a higher concentration to form a deeper electrode extraction layer.

Next, as shown in FIG. 3 (F), a window is opened in the passivation film 401 to form at least an emitter layer to introduce an n-type hole impurity concentration (As), and this window is used for electrode extraction. Contact window. This is because the emitter layer 15 is shallow for improving the performance of bipolar transistors.
In addition, it is necessary to have a narrow width. On the other hand, the length of the emitter has become slightly longer due to the securement of the driving force and the reduction of the base resistance, and the emitter is generally an elongated rectangular plane pattern. Further, in order to reduce the influence of the strain of the thick oxide film 101, the emitter layer is formed apart from the oxide film. Further, the MOS transistor is required to have a high degree of integration, and the source / drain contact is a square having a minimum pattern, and there is almost no distance from a thick oxide film.

Finally, as shown in FIG. 3G, at least a source contact, a drain contact, a base contact and a gate contact (not shown) of the p-channel MOS are opened to open a window, for example, aluminum (aluminum) as a low resistance metal wiring. Al) in the n-channel MOS (source 501 of n-channel MOS, drain 502 of n-channel MOS, base 503, emitter 504, collector 505, source 506 of p-channel MOS, drain 507 of p-channel MOS)
To form.

[Problems to be solved by the invention]

Conventional Bi-CMOS integrated circuit devices are bipolar and CMOS even if they can be shared in some processes.
Since it includes a large number of steps, there is a problem that the construction period becomes long, and eventually the yield is lowered. Further, as described above, particularly in a bipolar transistor as a transistor, the junction is deepened because it is formed by using a method such as directly implanting ions into impurities, which makes high-speed operation unsuitable. Further, even in a CMOS transistor, the speed may be further increased by reducing the resistance between the gate electrode and the source / drain electrodes.

The present invention has been made in order to solve the above problems, and an object of the present invention is to obtain a semiconductor integrated circuit device and a method for manufacturing the same which can shorten the process and operate at high speed.

[Means for solving problems]

The semiconductor integrated circuit device and the method of manufacturing the same according to the present invention make most of the manufacturing process common by making the structure near the emitter of the bipolar element and the structure near the gate of the n-channel MOS portion similar. is there.
In addition, the structure of the polysilicon emitter, LDD (Liyhtl
y Doped Drain) and low resistance or self-alignment by using silicide to enable fine processing and junction shallowing required for high-speed operation and high integration of elements. . Further, since the emitter region is formed by diffusion in the base region under the polysilicon film for the emitter, the extension of the surface of the silicide film provided on the base region is not affected by the difference between the emitter region and the polysilicon film for the emitter. The emitter region is configured to extend substantially below the sidewall provided on the side of the polysilicon film for the emitter so as to substantially coincide with the boundary surface, thereby minimizing the distance between the emitter and the base, and It aims at speeding up and fine processing.

[Operation] In the semiconductor integrated circuit device and the method for manufacturing the same according to the present invention, the emitter of the bipolar portion is formed by diffusion from polysilicon, and a sidewall is formed on the side wall thereof by, for example, a silicon oxide film, and silicide is further formed. By forming it, the emitter resistance and the base resistance can be reduced. In particular, the emitter and the base are insulated only by the sidewall of the silicon oxide film, but in such a state, it is not possible to use lithography, and the base resistance is not provided until such a configuration is adopted. Will be reduced. Moreover, this structure is similar to the structure of the gate electrode portion of the n-channel MOS transistor, and the difference between them is only the presence or absence of the gate oxide film. Therefore, in the bipolar transistor, if the silicon oxide film is removed only in the bipolar portion before forming the polysilicon for forming the base diffusion layer and the emitter diffusion, the n process can be performed in exactly the same process.
A channel MOS and a bipolar transistor can be formed, which will greatly contribute to shortening the process. Further, in the MOS transistor portion, since the source / drain portion is silicided by using the sidewall, the distance between the gate and the source / drain is substantially shortened, and the diffusion layer of the source / drain is accordingly reduced. A low concentration is also acceptable, and as a result, the short channel effect is less likely to occur when miniaturization progresses.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings. In addition, in the embodiment, a case of using an npn-type bipolar transistor will be described. In FIG. 1, 1 is a semiconductor substrate, 2 is an n-type high-concentration impurity layer formed on one surface of the semiconductor substrate, 3 is an epitaxial layer, 4 is a p-type well layer,
5 is a collector diffusion layer of a bipolar transistor, 6 is n
Drain diffusion layer of channel MOS, 7 is n channel MOS
Source diffusion layer, 9 is a p-channel MOS drain diffusion layer, 10 is a p-channel MOS source diffusion layer, 11 is a bipolar transistor base diffusion layer, 15 is a bipolar transistor emitter layer, 16 is a metal silicide layer, and 101 is Thick silicon oxide film for insulation, 102 is a silicon oxide film, 2
01 is polysilicon used for MOS gate, 202 is polysilicon for bipolar transistor emitter diffusion,
401 is a silicon oxide film for connecting a transistor and a wire, 501 is an n-channel MOS drain electrode, 502 is an n-channel MOS source electrode, 503 is a bipolar transistor base electrode, 504 is a bipolar transistor emitter electrode, and 505 Is the collector electrode of the bipolar transistor.

Next, an example of a method of manufacturing the semiconductor integrated circuit device having the above structure will be described with reference to the drawings. FIG. 2 (A) shows a known manufacturing method up to the element isolation step of the Bi-CMOS element,
A silicon oxide film 102 to be a gate oxide film is formed by thermal oxidation, and a resist 601 is patterned so as to open a region to be a bipolar base, and boron is implanted. Next, in order to diffuse this boron, drive is performed to form the base diffusion layer 11. Next, part of the bipolar transistor by lithography (equivalent to 103)
Except for, the silicon oxide film 102 is removed. However, in this case, since the silicon oxide film becomes the oxide film of the gate, it is not removed in the n-channel and p-channel MOS portions (FIG. 2 (B)). Subsequently, the polysilicon 200 is devoted to the entire surface. Furthermore, for the purpose of introducing resistance for polysilicon in the n-channel MOS gate portion and introducing impurities for forming an emitter into the polysilicon in advance,
Using the resist 602 that hides the p-channel part as a mask,
Arsenic ion implantation is performed (FIG. 2 (C)).

Further, in order to form the source / drain of the n-channel MOS, arsenic is ion-implanted using the resist patterns 603 and 604 which hide the base portion and the p-channel MOS portion of the bipolar transistor as a mask (FIG. 2 (D)). After that, the drive is performed, so that the collector diffusion layer 5, the emitter diffusion layer 15, and the n-channel MO of the bipolar transistor are
A drain diffusion layer 6 and a source diffusion layer 7 of S are formed. Next, in order to form the source / drain of the p-channel MOS portion, boron ions are implanted using the resist pattern 605 that hides the bipolar transistor and the n-channel MOS portion as a mask (FIG. 2 (E). Drain diffusion layer 11 and source diffusion layer of P-channel MOS
Then, a silicon oxide film is deposited on the entire surface by CVD, and RIE is used to form a silicon oxide film 17 on the side of the polysilicon 202 of the emitter and on the side of the polysilicon 201 of the gate in the n-channel MOS and p-channel MOS. The side wall is left (Fig. 2 (F). Then, refractory metal (Ti, M
(O, W, Pt, etc.) is deposited, and then heat treatment is performed in an inert atmosphere to silicify the refractory metal. in this case,
Since silicide is not formed in the thick silicon oxide film 101 for element insulation and the insulating silicon oxide film 103 between the base and collector of the bipolar transistor section, the portion where the silicide 16 is formed is It becomes possible to easily and selectively etch. Next, when the unreacted refractory metal is removed, the silicide 16 remains on the electrode portion of each transistor (FIG. 2 (G)). Further, a silicon oxide film 401 is attached by CVD or the like to insulate the wiring formed thereafter (FIG. 2 (H)). After that, contact holes are formed, aluminum wiring is applied, and Bi-CM
Complete the OS element.

In addition, in the above-mentioned embodiment, Bi-CM of the oxide film separation system
Although the OS element is taken as an example, the present invention is not limited to this, and the same effect can be obtained by applying it to a Bi-CMOS element using PN separation.

〔The invention's effect〕

As described above, according to the semiconductor integrated circuit device and the manufacturing method thereof according to the present invention, since the n-channel MOS and the bipolar transistor have almost the same structure, the manufacturing process thereof can be shortened. The work period can be shortened, and the yield of the device can be improved as the work period is shortened. In addition, by using silicide, the distance between the base and emitter of a bipolar transistor and the distance between the gate and source and drain of a MOS transistor can be made substantially shorter without narrowing the wiring interval, which results in high-speed operation of the device. There is an effect that it is possible to cope with the miniaturization and fine processing.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor integrated circuit device according to an embodiment of the present invention, and FIGS. 2A to 2H are process drawings for explaining a method for manufacturing the semiconductor integrated circuit device shown in FIG. ,
3 (A) to 3 (G) are process diagrams showing the manufacturing process of the conventional semiconductor integrated circuit device. 1 is a semiconductor substrate, 6 is an n-channel MOS drain diffusion layer, 7 is an n-channel MOS source diffusion layer, 9 is a p-channel MOS drain diffusion layer, 10 is a p-channel MOS source diffusion layer, and 15 is an emitter diffusion layer. , 16 is a silicide film,
Reference numeral 17 is a side wall of an insulating film, and 201 and 202 are polysilicon films. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device comprising at least a bipolar transistor and a MOS transistor on the same semiconductor substrate, wherein a silicon oxide film serving as a gate oxide film of the MOS transistor is formed on the semiconductor substrate. Then, the silicon oxide film in the region to be the base of the bipolar transistor of the silicon oxide film is removed to form a base region, and the emitter of the bipolar transistor and the gate of the MOS transistor are formed on the entire surface of the semiconductor substrate. A polysilicon film to be formed at the same time, an emitter region of the bipolar transistor is formed by diffusion in the base region below the polysilicon film to be the emitter, and a side portion of the polysilicon film for the emitter and the Insulating sidewalls on the side of the polysilicon film for the gate Then, a portion other than the emitter region and the sidewall on the base region, on the polysilicon film for the gate, on the polysilicon film for the emitter, and the source region of the MOS transistor and A method of manufacturing a semiconductor integrated circuit device, comprising forming a silicide film on a drain region. 2. A semiconductor device comprising at least a bipolar transistor and a MOS transistor on the same semiconductor substrate, a base region of the bipolar transistor, and an emitter polysilicon film and a gate polysilicon film formed at the same time. An emitter region of the bipolar transistor formed by diffusion in the base region below the emitter polysilicon film, and a sidewall that is an insulating film provided on a side portion of the emitter polysilicon film, A sidewall which is an insulating film formed on a side portion of the polysilicon film for gate, a silicide film provided on the base region other than the emitter region and the sidewall, and on the polysilicon film for gate. The emitter polysilicon film and the n-channel MOS type transistor A silicide film provided on the source region and the drain region of the emitter region, and the extension of the surface of the silicide film provided on the base region is at the surface of the boundary between the emitter region and the polysilicon film for emitter. The semiconductor integrated circuit device is substantially coincident with each other, and the emitter region extends below a sidewall provided on a side portion of the polysilicon film for emitter. 3. The semiconductor integrated circuit device according to claim 1, wherein the insulating film is a silicon oxide film. 4. The semiconductor integrated circuit device according to claim 1, wherein the silicide film is a titanium silicide film. 5. The semiconductor integrated circuit device according to claim 1, wherein the silicide film and the molybdenum silicide film are formed.