JPH07101822B2 - Amplifier with constant current bias circuit - Google Patents

Description

[Detailed Description of the Invention] Technical Field: The present invention relates to an amplifier having an input stage, a voltage amplification stage, and an SEPP output stage having at least one complementary amplification element, and wherein the majority of the bias current biasing the relay output terminals, excluding the control current flowing from the first and second relay output terminals of the voltage amplification stage to the control electrodes of the amplification elements of the output stage, is absorbed by a constant current element or constant current circuit, or the voltage appearing between two resistors directly connected to the output terminal is integrated, and then negatively fed back to the constant current circuit that absorbs the bias current to determine the bias of the SEPP output stage.

BACKGROUND ART A conventional amplifier has an input stage 10 as shown in FIG.
, a voltage amplification stage 20, and a SEPP (single-ended push-pull) output stage 30.

The input stage 10 is a monolithic IC with two FETs 11 and 12.
The amplifier is provided with an input terminal 13 connected to the gate of FET 11, an input resistor 14 connected between the input terminal 13 and the ground, a resistor 15 connected between the common source of FETs 11 and 12 and a negative voltage source -Vcc, and resistors 16 and 17 connected from the positive voltage source +Vcc to the drains of FETs 11 and 12. The gate of FET 12 is also provided with a negative feedback resistor 18 and a resistor 19 between the ground and the output terminal, which determine the gain of the amplifier.
19 is connected.

The voltage amplification stage 20 includes a PNP transistor 21 having a base connected to the drain of the FET 11, a PNP transistor 22 having a base connected to the drain of the FET 12, and
A resistor 23 connected between the common emitter of the NP transistors 21 and 22 and a positive voltage source +Vcc, and a PNP transistor 22
NPN with collector and base connected to the collector of
The PNP transistor 21 has a base connected to the collector of the PNP transistor 22 and an NPN transistor 25 having a base connected to the collector of the PNP transistor 22. The emitters of the NPN transistors 24 and 25 are both connected to a negative voltage source -Vcc. The collector current of the PNP transistor 22 has the same absolute value as that of the NPN transistor 25. The collector of the PNP transistor 21 forms the first relay output terminal _I1 , and the collector of the NPN transistor 25
The collector of forms the second relay output terminal _I2 .

Furthermore, the SEPP output stage 30 includes Darlington-connected NPN transistors 31 and 32, each having a collector connected to a positive voltage source +Vcc, Darlington-connected PNP transistors 33 and 34, each having a collector connected to a negative voltage source -Vcc, an output terminal 35, a first resistor 36 directly connected to the output terminal 35 and connected to the emitter of the NPN transistor 32,
and a second resistor 37 connected directly to the output terminal 35 and to the emitter of the PNP transistor 34.
The connection point between the emitter of the transistor 31 and the base of the NPN transistor 32 is connected to the output terminal 35 via a resistor 38, and the connection point between the emitter of the PNP transistor 33 and the base of the PNP transistor 34 is connected to the output terminal 35 via a resistor 38.
The connection point of the base of the NPN transistor 31 and the base of the PNP transistor 33 is connected via a resistor 39. The first relay output terminal _I1 is connected to the base (first control terminal) of the NPN transistor 31, and the second relay output terminal I2 is connected to the base (second control terminal) of the PNP transistor 33.
A constant voltage type bias circuit 26 is connected between _I2 .

The bias circuit 26 includes a temperature compensation NPN transistor 27 having a collector connected to the base of an NPN transistor 31 and an emitter connected to the base of a PNP transistor 32, a variable resistor 28 connected to the bases of the NPN transistors 31 and 27, and a resistor connected to the bases of the NPN transistors 27 and 27.
The NPN transistor 32 and the PNP transistor 34 are connected to the bases of the fixed resistors 29 and 28, respectively. In this case, the idle current flowing between the collectors of the NPN transistor 32 and the PNP transistor 34 is adjusted to class AB by adjusting the variable resistor 28. In this constant voltage bias circuit, the collector-emitter voltage of the NPN transistor 27 is calculated by adding the resistance values of the variable resistor 28 and the fixed resistor 29, dividing this sum by the resistance value of the fixed resistor 29, and then multiplying this divided value by the voltage of the NPN transistor 27.
Therefore, in the conventional constant voltage bias circuit 26, _VBE is approximately constant _, and therefore the bias voltage between the first and second relay output terminals is constant.

This conventional class AB amplifier includes, for example, NPN transistors 31 and 32
is driven positively, PNP transistors 33 and 34 are also driven positively via the constant voltage bias circuit. That is, as the base currents of NPN transistors 31 and 32 increase, their collector currents also increase, and the base-emitter voltages _VBE of NPN transistors 31 and 32 also increase. Furthermore, the voltage across first resistor 36 also increases due to the increased collector current. As a result, since the collector-emitter voltage of NPN transistor 27 remains approximately constant, the voltage applied between the emitter and base of PNP transistors 33 and 34 decreases, and PNP transistors 33 and 34 are turned off.

Generally, when bipolar transistors such as NPN and PNP transistors transition from the OFF state to the ON state,
Time is required for filling with hole or electron carriers, and this filling time adversely affects the amplifier characteristics.

When the PNP transistors 33 and 34 are driven negatively from a completely OFF state, in addition to the base current component that is directly proportional to the collector current, a carrier current is required to fill the transistor with electrons. This carrier current deteriorates the bare characteristics of the amplifier. Furthermore, when the amplifier is connected to an inductive load such as a speaker, this carrier current also causes the NPN transistors 31 and 32 and the PNP transistors 33 and 34 to
There is a time lag when turning the unit on and off, which adversely affects sound quality.
Therefore, conventional class AB amplifiers have the drawback of using a constant voltage bias circuit, which causes immeasurable deterioration in sound quality when measured with an actual measuring instrument.

DISCLOSURE OF THE INVENTION The present invention uses a constant current bias circuit to
The object is to provide an amplifier that eliminates problems caused by carrier current.

This constant current bias circuit is a commercially available Class B or AB
In the embodiment applied to a class A amplifier, the sound quality after the improvement is superior to that before the improvement, but the adjustment is more difficult than before.

To solve this difficulty in adjustment, two constant current bias circuits have been proposed.

First, a constant voltage bias circuit having an internal resistance higher than that of a conventional one is connected in parallel with the constant current bias circuit of the present invention, thereby providing a constant current bias circuit that takes over part of the current that flowed through the conventional constant voltage bias circuit.

The second is to use a feedback constant current bias circuit whose current value can be voltage controlled, and to provide a negative feedback circuit that determines this control voltage from the emitter resistor of the power transistor, i.e., the average voltage generated between the first and second resistors.

According to the present invention, there is provided an amplifier comprising an input stage having an inverting input terminal and a non-inverting input terminal, a voltage amplifier stage operatively connected to the input stage, and a SEPP output stage having first and second control terminals respectively connected to first and second relay outputs of the voltage amplifier stage, wherein a constant current bias circuit is connected between the first and second relay outputs to absorb current bypassing between the relay outputs. A constant current bias circuit according to the present invention and a constant voltage bias circuit may be connected in parallel to the first and second relay outputs.

According to the present invention, the SEPP output stage includes a first amplifying element, a second amplifying element having a polarity different from that of the first amplifying element, an output terminal, and a first amplifying element directly connected to the output terminal.
and a second resistor directly connected to the output terminal and connected to the common electrode side of the second amplifying element, wherein the current value of the constant current bias circuit is controlled by voltage, and a voltage appearing across both ends of the first and second resistors is applied to this constant current bias circuit via an integrating circuit, thereby controlling the current bypassing between the first and second relay output terminals, thereby controlling the bias current flowing through the first and second resistors.

The present invention originates from the discovery that a constant current bias circuit significantly improves the bare characteristics of an amplifier compared to a conventional constant voltage bias circuit. In a class AB amplifier using a constant current bias circuit, the elements used, such as bipolar transistors or field effect transistors (FETs),
T) and the temperature characteristics of the resistors must be taken into consideration. Of course, the constant current bias circuit itself also has temperature characteristics.
In addition, the ASO of the power transistor used in the output stage
The area must also be considered.

The present invention discloses two types of basic circuits using a constant current bias circuit.

In the first basic circuit, the operating temperature range of the amplifier is set to, for example, 0
Set the temperature to 70°C, and find the base value A and fluctuation range B (A±B) of the bypass current within this temperature range. Next, find the base value C and fluctuation range D (C±D) of the passing current of the constant current bias circuit, and set the current setting value of the constant current bias circuit to (C+D).
≦A, and the remaining bypass current is set as follows:
This is absorbed by a constant voltage bias circuit whose internal resistance is approximately (A-B)/B times higher than the conventional one.
D is positive.

In the second basic circuit, for example, the amplifier operating temperature range 0
The basic value A and fluctuation range B of the bypass current at 70°C (A±
B), and a constant current bias circuit is used that has a control current range that can completely absorb this fluctuation width B and can voltage-control the current value. Therefore, the voltage that appears across the output resistor connected to the output terminal is applied to the constant current bias circuit connected between the first and second relay output terminals via an integrating circuit, and negative feedback is applied to the power
The integrator circuit stabilizes the idle current of the transistor. In this case, it removes low frequency components, for example, above 20 Hz, of the signal flowing through the output resistor.
In the present invention, by using a constant current circuit, an integrator circuit, and negative feedback technology in the bias circuit, matching between the transistors in the drive stage and the transistors in the SEPP output stage can be achieved by simply adding or subtracting current, and transistors in the SEPP output stage that are not driven will not be turned off.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a conventional class AB amplifier, FIG. 2 is a basic circuit diagram of an amplifier equipped with a constant current bias circuit according to the present invention, FIG. 3 is a voltage/current graph diagram of a constant current element, a constant current bias circuit, and a constant voltage bias circuit, FIG. 4 is a circuit diagram showing an amplifier according to a first embodiment of the present invention, FIG. 5 is a circuit diagram showing a part of an amplifier according to a second embodiment of the present invention, FIG. 6 is a circuit diagram showing a part of an amplifier according to a third embodiment of the present invention, FIG. 7 is a circuit diagram showing a third embodiment of a constant current bias circuit according to the present invention, and FIG. 8 is a circuit diagram showing a fourth embodiment of a constant current bias circuit according to the present invention.
9 is a circuit diagram showing a constant current bias circuit equipped with a protection circuit for preventing rush idle current when the power is turned on; FIG. 10 is a circuit diagram showing a large current type constant current bias circuit; FIG. 11 is a circuit diagram showing a constant current bias circuit connected in parallel with a conventional constant voltage bias circuit in which the constant voltage effect is weakened; and FIG. 12 is a circuit diagram showing a class AB amplifier in which a constant current bias circuit according to the present invention is connected in parallel to a diode-type bias circuit of a class A amplifier.

BEST MODE FOR CARRYING OUT THE INVENTION In order to explain the invention in more detail, an embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which: FIG.

Fig. 2 shows the basic circuit of the amplifier according to the present invention. In this figure, the same reference numerals are used to designate components corresponding to those used in the amplifier of Fig. 1, and explanations of corresponding parts will be omitted.

As is clear from a comparison with the conventional amplifier shown in FIG. 1, the amplifier according to the present invention uses a constant current bias circuit 40 instead of the constant voltage bias circuit 26. This constant current bias circuit
40 is, for example, a junction type N-channel junction FET 41 having a drain connected to the first relay output terminal _I1 ;
and a resistor connected to the second relay output terminal _I2.
The gate of the FET 41 is connected to the second relay output terminal _I2 .
It will be apparent that may be replaced by, for example, a constant current diode, or a P-channel FET may be used in a similar circuit configuration.

Figure 3 shows the N-channel model number 2SK170 available on the market.
This figure shows typical current-voltage characteristics of an FET when _VGS = 0V, as well as typical current-voltage characteristics of a commercially available constant-current diode (model E272). This FET exhibits a rapid rise in current, similar to a resistor, when the drain-source voltage is in the range of 0 to 0.5V. However, once the drain-source voltage exceeds approximately 0.5V, the current slowly rises from approximately 8mA, exhibiting a nearly constant constant-current characteristic. On the other hand, a constant-current diode has a transition voltage of approximately 1.5V where it transitions from a resistor to a constant-current characteristic. It is clear from Figure 3 that the characteristics of the constant-current bias circuit of the present invention differ from those of a conventional constant-voltage bias circuit, an example of which is shown by the dotted line.

4 shows a circuit diagram of an amplifier with a feedback constant current bias circuit according to the present invention. The amplifier comprises a differential input stage 10, a voltage amplifier stage 20, and a complementary SEPP output stage 30.
It is equipped with the following.

First, the differential input stage 10 is composed of, for example, a dual FET IC in which two FETs 11 and 12 are integrated on a single substrate in consideration of thermal balance, and an input terminal connected to the gate of the FET 11.
13, and an input resistor 14 connected between the input terminal 13 and ground.
a resistor 15 connected between the common source of FETs 11 and 12 and a negative voltage source -Vcc, and resistors 16 and 17 connected from a positive voltage source +Vcc to the drains of FETs 11 and 12. Negative feedback resistors 18 and 19 that determine the gain of this amplifier are connected to the gate of FET 12 between the ground and an output terminal (to be described later).

The voltage amplification stage 20 includes a PNP transistor 21 having a base connected to the drain of the FET 11, a PNP transistor 22 having a base connected to the drain of the FET 12, and
The circuit is provided with a resistor 23 connected between the common emitter of the NP transistors 21 and 22 and a positive voltage source, and a current mirror circuit 60 connected to a negative voltage source -Vcc. This current mirror circuit 60 causes a current of the same absolute value as the collector current of the PNP transistor 22 to flow as the collector current of the NPN transistor 25. Therefore, when the PNP transistor 2
NPN with base and collector connected to collector of 2
The emitter of transistor 24 is connected to a negative voltage source −Vcc via resistor 61. NPN transistor 25 has its base connected to the base of NPN transistor 24.
The emitter of the PNP transistor 61 is connected to a negative voltage source −Vcc via a resistor 62 having the same value as the resistor 61.
The collector of NPN transistor 21 forms a first relay output _I1 , and the collector of NPN transistor 25 forms a second relay output _I2 .

The first relay output terminal _I1 and the second relay output terminal I2 of the voltage amplification stage 20 are connected to each other.
Between the relay output terminals I _{and 2} , a constant current bias circuit 40 of the present invention is provided.
A SEPP output stage 30 including:

The SEPP output stage 30 includes three Darlington-connected NPN transistors, each having its collector connected to a positive voltage source +Vcc.
The circuit comprises: NPN transistors 31 and 32; Darlington-connected PNP transistors 33 and 34, each having a collector connected to a negative voltage source −Vcc; an output terminal 35; a first resistor 36 directly connected to the output terminal 35 and to the emitter of the NPN transistor 32; and a second resistor 37 directly connected to the output terminal 35 and to the emitter of the PNP transistor 34. The connection point between the emitter of the NPN transistor 31 and the base of the NPN transistor 32 may be connected to the connection point between the emitter of the PNP transistor 33 and the base of the PNP transistor 34 via a constant current element (not shown).

A constant current bias circuit 40 is connected between a first relay output terminal _I1 connected to the base of the NPN transistor 31 and a second relay output terminal _I2 connected to the base of the PNP transistor 33. A voltage appearing at one end of the output resistor 36 and the other end of the output resistor 37 is applied to the constant current bias circuit 40 via an integrating circuit 50. The integrating circuit 50 is connected to the output resistor 36.
and a capacitor 52 connected between the other end of resistor 51 and the other end of output resistor 37, forming a 6 dB/octave first-order high-cut filter with a cutoff frequency of, for example, 20 Hz. Constant current bias circuit 40 also includes an N-channel junction FET 41 having its drain connected to the collector of PNP transistor 21 and the base of NPN transistor 31, and a PNP transistor 43 connected in cascade with FET 41, i.e., having its emitter connected to the source of FET 41. The collector of PNP transistor 43 is connected to the collector of NPN transistor 25 and the base of PNP transistor 33.
The collector current, i.e., drain current, of the cascaded FET 41 and PNP transistor 43 is adjusted by the control voltage applied between the gate of FET 41 and the base of PNP transistor 43. If this gate-to-base control voltage is constant, the collector current, i.e., drain current, remains approximately constant even if the voltage across the relay output terminals changes.

The operation of a class AB amplifier including a constant current bias circuit of the present invention will now be described. First, let us assume that the combined current amplification factor (collector current/base current) of the NPN transistors 31, 32 and the PNP transistors 33, 34 is 1,000, the idling current of the NPN transistors 31, 32 and the PNP transistors 33, 34 in a no-signal state is 50 mA, and the collector current of the PNP and NPN transistors 21 and 25 is 5 mA each.
and the base current of PNP transistors 31 and 34 is 0.05 m
A can drive the above idling current, so 4.95mA
This current flows through the first and second
The voltage appearing between the output resistors 36 and 37 is set to, for example, 0.1V.

Now, if a positive signal is applied to the input terminal 13 and the collector current of the PNP transistor 21 becomes 5.5 mA,
The collector current of NPN transistor 22 becomes approximately 4.5 mA, and therefore the collector current of NPN transistor 25 of current mirror circuit 60 decreases to approximately 4.5 mA. Therefore, the base current of NPN transistor 31 becomes 1.05 mA, and 1.
A positive current of 0.5A can be extracted.

Meanwhile, a total of approximately 4.5 mA flows through the drain of constant current circuit 40 and the base of PNP transistor 33. The distribution ratio of these currents depends on the voltage at the base point of NPN transistor 31, the output voltage, and the voltage at the base point of PNP transistor 33, and in this case, PNP transistors 33 and 34 do not enter the OFF state.

The present invention eliminates the drawbacks of bipolar transistors used in the SEPP output stage by using a constant current bias circuit whose current value is controlled by a control voltage. Therefore, the term "transistor" used here includes Darlington-connected and inverted Darlington-connected PNP and NPN transistors.

Furthermore, the amplifier equipped with the constant current bias circuit according to the present invention can be applied to MOS type FETs as well as bipolar type transistors and N- and P-channel MOSFETs, as shown in FIG.
The constant current bias circuit 40 may be connected in a mixed manner with the NPN transistors 63 and 64, or other amplifying elements such as junction FETs or SITs may also be used. In this case, the elements corresponding to those in the first embodiment of the present invention shown in Fig. 1 are given the same reference numerals. That is, the constant current bias circuit 40 includes an NPN transistor 44 having its collector connected to the base of the NPN transistor 31, and an NPN transistor
The drain of the P-channel FET 45 is connected to the base of the PNP transistor 33, and the NPN
The base of the transistor 44 is connected to one end of the first output resistor 36, the gate of the P-channel FET 45 is connected to the other end of the second output resistor 37 via a resistor 51, and a capacitor 52 is connected between the base of the NPN transistor 44 and the gate of the P-channel FET 45.

The drain of the N-channel MOSFET 63 is connected to a positive voltage source, the gate is connected to the emitter of the NPN transistor 31, and the source is connected to one end of the first output resistor 36. On the other hand, the drain of the P-channel MOSFET 64 is connected to a negative voltage source, the gate is connected to the emitter of the PNP transistor 33, and the source is connected to the second output resistor 37. Furthermore, the NPN and PNP transistors 31 and 33
A resistor 38 is connected between the emitters to allow a bias current with good frequency characteristics to flow.

Furthermore, the integrator circuit 50 may use a second-order or higher high-cut filter.

FIG. 6 shows a portion of an amplifier equipped with a constant current bias circuit according to a third embodiment of the present invention.

This constant current bias circuit 40 is a junction type N-channel FE
T47 and a junction type P-channel FET 48 having a source connected to the source of this N-channel FET 47 via a resistor 49.
The integrated voltage appearing across both ends of output resistors 36 and 37 connected in series is applied between the gates of these N-channel and P-channel FETs.

This constant current circuit also serves as temperature compensation for the NPN transistor 31 and the PNP transistor 33. Therefore, as shown in Figure 6, part of the bias current may be supplied to a constant current element 67 or a constant current connected N-channel FET 65 connected in parallel. Resistor 66 adjusts the drain current to obtain a predetermined constant current.

7 shows another embodiment of the constant current bias circuit. This circuit comprises a constant current diode 71 having an anode connected to the first relay output terminal _I1 , a base connected to the cathode of this constant current diode 71, and a resistor connected to the first relay output terminal _I1.
an NPN transistor 72 having a collector connected to
The emitter connected to the cathode of the constant current diode 71 and the second
a PNP transistor 73 having a collector connected to the first relay output terminal _I2 ; a resistor 74 having one end connected to the emitter of the NPN transistor 72; a PNP transistor 75 having an emitter connected to the other end of the resistor 74 and a collector connected to the second relay output terminal _I2 ;
a constant current diode 76 having an anode connected to the base of the first relay output terminal _I1 and a cathode connected to the second relay output terminal I2; a collector connected to the first relay output terminal _I1 ;
NPN transistor 7 with its emitter connected to the anode of
This circuit includes a PNP transistor 73 and
The voltage applied across the base of the NPN transistor 77 controls the current passing through the resistor 74. These constant current diodes may each be replaced with a resistor.

The constant current bias circuit used in the amplifiers shown in Figures 4 to 7 is suitable for a two- or three-stage Darlington-connected SEPP output stage. However, when the SEPP output stage is a single stage, as shown in Figure 8, the voltage _VBB between the base of PNP transistor 31 and the base of NPN transistor 33 is approximately 1.
Since it is 3V, for example, the PNP transistor 33 is driven
It is preferable to control the voltage on the emitter side from the base (control end) side.

This constant current bias circuit includes an SEPP output stage that includes an NPN transistor 31 having a collector connected to a positive voltage source +Vcc and an emitter connected to one end of a resistor 36, an output terminal 35 connected to the other end of the resistor 36 and one end of a resistor 37, and a PNP transistor 33 having an emitter connected to the other end of the resistor 37 and a collector connected to a negative voltage source -Vcc, and further includes an NPN transistor 78 having a collector connected to the base of the NPN transistor 31 and an emitter connected to the base of the PNP transistor 33. Therefore, the integrating circuit 50 includes a resistor 51 connected to the base of the NPN transistor 78 and one end of the resistor 36, and a capacitor 52 connected between the base and emitter of the NPN transistor 78.

This type of feedback constant current bias circuit charges the capacitor 52 that constitutes the integrating circuit, so that when the power is turned on, a rush idle current flows to the emitter of the power transistor in the output stage. In order to set this rush idle current within the ASO region of the power transistor, it is recommended to use the constant current bias circuit 40 shown in Figure 6. In this case, the bias current flowing between the FETs 47 and 48 is set to 2 mA.
Assuming that the absolute value of I _DSS is about 8mA or more, the FET47,4
8, it is recommended to adjust resistor 49 to set the bias current to 2 mA. Furthermore, it is preferable that the transconductance gm of these FETs 47 and 48 be a typical value of 30 mS or more. In this way, the voltage _VSS between the sources of FETs 47 and 48 during operation is approximately 20 times the voltage _VGG between the gates, thereby keeping the fluctuation range of the bias current low.

However, in an amplifier with three or more Darlington-connected SEPP output stages, there is a risk that rush idle current will destroy the power transistors in the output stage. In this case, to suppress rush idle current, it is recommended to provide a delay circuit that operates the conventional constant voltage bias circuit for, for example, two seconds after power is turned on.

FIG. 9 shows a constant current bias circuit according to the present invention and an ON/OFF
The figure shows part of an amplifier equipped with a controllable constant voltage bias circuit, a delay circuit that delays the signal for a predetermined period from when the power is turned on, and an isolator that receives only this signal and turns off the constant voltage bias circuit. The constant current bias circuit is similar to that shown in Figure 6, so its explanation will be omitted. The constant voltage bias circuit is composed of a Darlington-connected NPN transistor 81 having a common collector connected to the relay output terminal _I1 and an emitter connected to the relay output terminal _I2 , and a common collector connected to the relay output terminal _I3.
and a high resistance 82 connected to the base of an NPN transistor 81.
and a high resistance 83 connected between the base of the NPN transistor 81 and the relay output terminal _I2 .
For example, it is a photocoupler including a light-emitting diode 86 having an anode and a cathode connected to the output terminal Q of the delay circuit 89 and ground, respectively, and a phototransistor 87 having a collector and an emitter connected to the base and emitter of the NPN transistor 81. The delay circuit 89 includes, for example, a CMOS monostable multivibrator, i.e., a Motorola MC14528. A constant current diode 88 or a similar circuit is connected between the base and collector of the PNP transistor 33.

The above-described embodiment maximizes the advantages of the constant current bias circuit of the present invention. Furthermore, when the present invention is applied to operational amplifiers (OP amps), such as the TI TL-08X series or the Fairchild μA741 or 4558, it is preferable to connect the constant current bias circuit of the present invention in parallel with a conventional constant voltage bias circuit with weaker performance than the unimproved version. In other words, such monolithic integrated circuits are constructed by forming active elements such as transistors or resistors on the same P-type substrate, and connecting their electrodes with, for example, aluminum-evaporated wires to form an amplifier. Therefore, the temperature coefficients of these elements are more easily correlated with each other than in hybrid amplifiers. Therefore, the ratio of the bias current provided by the constant current bias circuit of the present invention to that provided by the constant voltage bias circuit can be set higher than in hybrid amplifiers. Furthermore, this improvement can be easily implemented in conventional monolithic OP amps. That is, the area occupied by the conventional constant voltage bias circuit is divided into, for example, 1:9, and the scaled conventional constant voltage bias circuit is accommodated in one area, and the remaining 9 areas are occupied by the constant current bias circuit,
In this case, a constant current diode or a constant current connected FET can be formed. Even if the capacity of this constant current bias circuit does not correspond to 0.9 times that of a conventional constant voltage bias circuit, the empty area near the bias circuit on the substrate can be used, and furthermore, since only two connections are required, the layout of these elements is quite easy.

An embodiment for teaching such an application is shown in Figure 10. The bias circuit shown in this figure is a parallel connection of a constant current bias circuit and a constant voltage bias circuit type.

This constant current bias circuit is an FE transistor having a drain connected to the relay output terminal _I1 and a gate connected to the relay output terminal _I2.
T41 and the resistor connected to the source of FET41 and the relay output terminal _I2
On the other hand, the constant voltage bias circuit includes an NPN transistor 27 having a collector connected to the relay output terminal _I1 and an emitter connected to the relay output terminal _I2 , and a
A variable resistor connected to the base of NPN transistor 27 _and
The NPN transistor 27 has a base terminal 28 and a resistor 29 connected to the base of the NPN transistor 27 and the relay output terminal _I2 . The capacitor 90 is used to make the constant voltage bias circuit a constant current circuit, and has a value of, for example,
The capacitor 27 has a capacitance of 100 μF and is connected to the base of the NPN transistor 27 and the relay output terminal _I2 . The capacitor 27 is provided to make the conventional constant voltage bias circuit a constant current circuit.

Next, a current distribution method between the constant current bias circuit and the constant voltage bias circuit will be described.

First, the operating temperature range of the amplifier is, for example, 0 to 70°C according to commercial standards. Within this operating temperature range, the base value A and fluctuation range B (A±B) of the bias current flowing between the relay output terminals _I1 and _I2 are calculated or estimated. Next, the base value C and fluctuation range D (C±B) of the current passing through the constant current bias circuit are calculated.
The current value of the constant current bias circuit is set so that (C + D) ≤ A is satisfied. The remaining bias current is absorbed by a constant voltage bias circuit whose internal resistance is approximately (A - B)/B times higher than that of the conventional circuit. However, A,
B, C, and D are correct.

In the improved amplifier, which is an embodiment of the present invention and is an improvement over the conventional amplifier, the bias current is measured, and the FET 41 and the resistor 42 are selected so that, for example, 99 to 80% of the measured current is supplied to the constant current bias circuit, and the variable resistors 28 and 29 are selected so that the remaining measured current is supplied to the constant voltage bias circuit.
The value is set to 1/(1-0.99) to 1/(1-0.8) times the conventional value.

FIG. 11 shows a circuit that is used when the current supplied to the constant current bias circuit exceeds, for example, 10 mA, since the I _DSS of the FET 41 is normally 10 mA or less.

This circuit has an emitter connected to relay output _I1.
The circuit is provided with a PNP transistor 91, an FET 41 having a drain connected to the base of the PNP transistor 91 and a gate connected to a relay output terminal _I2 , a resistor 92 connected to the relay output terminal _I1 and the base of the PNP transistor 91, and a resistor 42 connected to the connection point between the collector of the PNP transistor 91 and the source of the FET 41 and the relay output terminal _I2 .

Figure 12 shows A, which is said to provide the best sound quality currently available.
Class M amplifier (model number M-1000, sold by Pioneer in Japan)
4) shows a partial circuit diagram of a class AB amplifier in which the constant current bias circuit of the present invention is connected in parallel with a conventional bias circuit.

This circuit consists of four parallel-connected NPN transistors 32
and a PNP transistor 34, and is provided with a variable resistor 96 having one end connected to the relay output terminal _I1 , and a constant voltage element 95 having an anode connected to the other end of the variable resistor 96. This constant voltage element 95 is made by connecting three temperature compensation diodes in series and sealing them in a resin container with good thermal conductivity.
The cathode is connected to _the relay output terminal _I2 , and is attached to the heat sink (cooler) on which the four sets of transistors 32 and 34 are attached.
In order to make the voltage between I _{and 2} more constant, an electrolytic capacitor
It appears that capacitor 94 was connected between relay outputs _I1 and _I2 , but the inventor simply removed this capacitor 94 and inserted the constant current bias circuit of the present invention, which essentially limits only the current value. The result was that the heat sink fin, which before the improvement was too hot to touch for about 2 to 10 minutes after operation, remained warm enough to touch at all times after the improvement. This proves that the amplifier has changed from class A to class AB.

Regarding sound quality, even though there was a three-hour modification time between the listening test before and after the improvement, all four people present, including the inventor, judged that the sound quality after the improvement was superior to that before the improvement.
The source code remained completely unchanged except for the changes mentioned above.

As described above, in the amplifier of the present invention, the bipolar transistors on the positive and negative power supply sides used in the output stage do not enter an OFF state, and therefore the dynamic distortion of the output signal is reduced. Furthermore, even when the class AB power amplifier using the constant current circuit of the present invention is connected to an inductive load such as a speaker,
The power NPN and PNP transistors are not turned off, which has the advantage of reproducing even the most subtle sounds very realistically.
It can be used in PA applications, and is particularly suited to use with integrated circuit operational amplifiers found in other musical instruments.

Claims (6)

[Claims] 1. A SEPP comprising: an input stage having an inverting input terminal and a non-inverting input terminal; a voltage amplifier stage operatively connected to the input stage; an output terminal connected to first and second relay outputs of the voltage amplifier stage, respectively; a first transistor having an emitter or a source connected to the output terminal via a first output resistor; and a second transistor having an emitter or a source connected to the output terminal via a second output resistor.
an output stage; a constant current bias circuit connected between the first and second relay output terminals, the current value of which is controlled by a control voltage; and a low-pass filter that averages the voltage appearing between the first and second output resistors and then applies the averaged voltage to the constant current bias circuit as the control voltage to control the idle current between the first and second transistors, wherein the constant current bias circuit comprises a junction FET whose drain is connected to the relay terminals. 2. The amplifier of claim 1, wherein said first transistor is an NPN transistor and said second transistor is a PNP transistor. 3. The first transistor is an N-channel MO transistor.
SFET, and the second transistor is a P-channel MO
2. The amplifier of claim 1, which is an SFET. 4. The constant current bias circuit comprises a junction type N-channel transistor having a drain connected to the first relay output terminal.
a PNP transistor having an emitter connected to the source of the N-channel FET and a collector connected to the second relay output terminal, a capacitor connected between the gate of the N-channel FET and the base of the PNP transistor,
2. The amplifier of claim 1, wherein the gate of said channel FET is connected to said first output resistor via a resistor, and the base of said PNP transistor is connected to said second output resistor. 5. The constant current bias circuit includes an NPN transistor having a collector connected to the first relay output terminal;
a junction type P-channel FET having a source connected to the emitter of the NPN transistor and a drain connected to the second relay output terminal, a capacitor connected between the base of the NPN transistor and the gate of the P-channel FET, and
2. An amplifier according to claim 1, wherein the base of said N-channel transistor is connected to said first output resistor, and the gate of said P-channel FET is connected to said second output resistor via a resistor. [Claim 6] An amplifier as described in claim 1, wherein the constant current bias circuit comprises junction type N- and P-channel FETs whose drains are each connected to the relay output terminal and whose sources are interconnected, and the control voltage is applied between the gates of the N- and P-channel FETs.