JPH07101826B2 - Differential amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A constant current type differential amplifier circuit including an emitter resistor is provided for the purpose of obtaining a maximum output amplitude under the same power supply voltage. And the other transistor has only a collector-side load resistance, and the base potential of the one transistor with respect to the base potential of the other transistor so that the maximum output voltage without distortion is taken out from the collector of the other transistor. It is configured to apply a predetermined bias voltage and an input signal to the potential.

[Industrial application field]

The present invention relates to a differential amplifier circuit, and more particularly to a constant current type differential amplifier circuit including an emitter resistor.

Normally, the power supply voltage of a communication device or the like is fixed to a constant value depending on the constituent parts of the device, so it is necessary to maximize the characteristics of the amplifier or the like within the range of this constant value.

[Conventional technology]

FIG. 4 shows an example of a conventional differential amplifier circuit. The transistors Q1 and Q2 form a differential pair, and R _E1 and R _E2 are the base inputs V _b1 and V _{b2 of the} transistors Q1 and Q2. Is an emitter resistance provided to widen the dynamic range of R _c2 , and R _c2 is a load resistance for extracting an output from the collector of the transistor Q2. Further, the base potential of the transistor Q2 side is fixed to V _ref , the input signal V _in is added only to the transistor Q1 side, and the output is taken out from the transistor Q2 side. Further, here, _a current mirror is formed by the transistors Q3 and Q4 and the resistor R _a to form a balanced transistor.
The emitter resistance and collector resistance R _{c2 of} Q1 and Q2 are R _E1 = R _E2
= 1 / 2R _c2 has realized a 2I _E constant current source by each emitter current I _E.

FIG. 5 is a diagram showing the waveform of each part in the case of a gain of 1 when the maximum amplitude that allows the differential pair of FIG. 4 to operate linearly is input, and this circuit configuration is the most conventional differential amplifier circuit. The power supply voltage can be effectively used, that is, a signal with a large amplitude can be handled with a low power supply voltage V _EE .

[Problems to be Solved by the Invention]

In such a differential amplifier circuit, the base input V _b1 must be increased in order to further increase the amplitude V _out-PP of V _c2 shown in the waveform diagram of FIG. 5, but this base input V _b1 When is increased, V _c2 becomes saturated as shown by the chain line. That is, it can be seen that V _c2 shown in FIG. 5 has the maximum output between V _{ref and} GND.

Therefore, it is necessary to lower V _b2 further by lowering the value of V _ref , but then V _e2 will also drop, and due to the balance of the differential circuit, it is not necessary to lower V _b1 and V _e1 together. In the end, V _a will decrease and ΔV ₁ will decrease.

This ΔV ₁ cannot be made smaller than this because the transistor Q3 needs to be at least about 0.8V in order to function as a current mirror, that is, as a current source, and therefore the input amplitude V _b1 cannot be made larger than this. .

Therefore, it is an object of the present invention to obtain the maximum output amplitude under the same power supply voltage in a constant current type differential amplifier circuit including an emitter resistor.

[Means for Solving the Problems]

In the case of the differential amplifier circuit as shown in FIG. 4, its gain G is almost determined by the ratio of the resistance on the emitter side and the resistance on the collector side as in the following equation.

G = R _c2 / (r _e1 ＋ R _E1 ＋ R _E2 ＋ r _e2 ) (1) where r _e1 and r _e2 are the emitter resistances at the operating points of the transistors Q1 and Q2, and are usually used by balancing the differential pair. If so, the same value will be obtained and r _e1 = r _e2 = V _T / I _E (V _T ≈26 mV), but R _E1 , R _E2 >> r _e1 , r _E2 Select R _E1 and R _E2 Then, it can be seen that G≈R _c2 / (R _E1 + R _E2 ) = R _c2 / R _E (where R _E = R _E1 + R _E2 ) (2).

Then, even if the gain G is set as in the above equation (2), the constant current I _E flowing through the current mirror does not change.

Therefore, in the present invention, as shown in the principle diagram of FIG. 1, one transistor Q1 has only the emitter side resistance R _E , the other transistor Q2 does not include the emitter side resistance, and the other transistor Q2 has the collector side resistance. It is configured to have only the load resistance R _c . Further, the transistor Q1 is connected to the base potential V _ref of the transistor Q2 so that the maximum output voltage without distortion is taken out from the collector of the transistor Q2.
A predetermined bias voltage V _B and an input signal S are applied to the base potential of the.

[Action]

Conventionally, the emitter resistance, which was previously divided into R _E1 and R _E2 , is turned to the transistor Q1 side to make it a resistor R _E , so that the base potential of the transistor Q2 can be made closer to the power supply voltage V _EE side, so that the transistor Q2 The collector amplitude of can be made large.

When the collector amplitude V _c2 ′ in this case is obtained in the example of the gain G = 1, as shown in the waveform diagram of FIG. 2, V _out-PP ′ = (| V _EE │−ΔV ₁ −V _BE2 ) (3 ). Here, V _BE2 is the base-emitter voltage of the transistor Q2.

In contrast, the collector amplitude V _c2 shown in Fig. 4, V _out-PP = a _{(| -ΔV 1 -V BE2 | V} EE) × 2/3 (4). This is because, as shown in FIG. 5, when the gain is 1, the amplitude of V _{c2 and} the amplitude of V _b1 are equal.

It can be seen from equations (3) and (4) that V _out-PP ′ is V
_This means that it has an output amplitude 1.5 times that of _out-PP .

Note that this is V when the gain is larger than “1”.
_{Since in} is only decreased and V _out is the same, again, a larger amplitude can be obtained under a constant power supply voltage.

〔Example〕

FIG. 3 shows an embodiment of the differential amplifier circuit according to the present invention. In this embodiment, the emitter side resistance R _E of the transistor Q1 and the collector side resistance R _c of the transistor Q2 are 2 kΩ.
The transistors Q3 to Q5 (the same emitter current as that of the transistor Q4 flows to the emitters of the transistors Q3 and Q5) which also form a current mirror are used as constant current sources. And the power supply voltage V _EE (−5.2V)
Below, resistors R1 to R3 having the illustrated resistance values are used so that an emitter current of 1.8 mA flows through each of the transistors Q3 to Q5. Therefore, the base potential V of the transistor Q1
_b1 ′ and the collector potential V _c2 ′ of the transistor Q2 are both 1.8 V as an example of gain “1”, the emitter potential V _e1 ′ of the transistor Q1 is −2.6 V, the base potential V _b2 ′ of the transistor Q2 is −3.6 V, and the resistance is The emitter potential of the transistor Q2 connected to R _E becomes −4.4V.

The input signal S (V _in) is inputted to the transistor Q1 through the capacitor C1, the output signal V _out from the collector via a capacitor C2 of the transistor Q2 is generated, the base potential V _b1 of the transistor Q1 'and The bias voltage V shown in FIG. 1 is applied between the base potential V _b2 ′ of the transistor Q2.
The voltage of 1.8V corresponding to _B is applied.
Furthermore, 0.8V is applied between the collector and emitter of transistor Q3.
The required voltage (ΔV ₁ ) is applied.

Therefore, in the above equations (3) and (4), V _EE = −5.2V, V
_BE2 = -0.8 V, is calculated by substituting each [Delta] V ₁ = -0.8 V, the _{V out-PP '= 3.6VV out} -PP = 2.4V.

As described above, in the case of the gain 1, it can be understood that the conventional circuit can handle only 2.4V, but the present invention can linearly handle a signal of 3.6V.

Further, even when the gain is not 1, a larger output amplitude can be obtained in the same manner.

〔The invention's effect〕

As described above, according to the differential amplifier circuit of the present invention, the emitter resistance of the transistor on the output take-out side is removed, and a predetermined bias voltage is applied to the base potentials of both transistors to obtain the maximum amplitude without distortion. Since the output voltage is generated, a signal having a larger amplitude can be obtained even with the same power supply voltage, and the circuit is particularly effective for a buffer amplifier or the like.

[Brief description of drawings]

FIG. 1 is a circuit diagram for explaining the principle of a differential amplifier circuit according to the present invention, FIG. 2 is an operation waveform diagram of the present invention, and FIG. 3 is an implementation of a differential amplifier circuit of the present invention. FIG. 4 is a circuit diagram showing an example, a circuit diagram showing a conventional differential amplifier circuit, and FIG. 5 is an operation waveform diagram of a conventional example. In FIG. 1, Q1, Q2 ... Transistors, R _E ... Emitter side resistance, R _c ... Collector side resistance, V _B ... Bias voltage, V _ref ... Transistor Q2
Base potential of. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A constant current type differential amplifier circuit including an emitter resistor, wherein one transistor (Q1) has only an emitter side resistor (R _E ) and the other transistor (Q2) is a collector side load resistor. (R _c ), the one transistor with respect to the base potential (V _ref ) of the other transistor (Q2) so that the maximum output voltage without distortion is taken out from the collector of the other transistor (Q2). A differential amplifier circuit characterized in that a predetermined bias voltage (V _B ) and an input signal (S) are applied to the base potential of (Q1).