JPH0710195B2 - Motor control circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to the technical field of speed control of a motor, and more particularly to a control circuit for constant-speed stable rotation of a motor.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional motor control circuit used for controlling a disc motor of a still video floppy recorder. In FIG. 4 (a), 1 is a disc motor and 2 is a rotational phase of the motor. Rotating phase detector (Phase Generator; abbreviated as PG hereinafter), 3 is a detector 2
A PG waveform shaping circuit that shapes the output of the output to a TTL level that can be used as a digital signal, 4 is an oscillation circuit for generating the clock necessary for operating this control circuit, and 6 is a clock of the oscillation circuit 4. , A frequency dividing circuit for producing a rotation reference frequency signal, 28 is a preset circuit for determining the rising and falling points of a digital trapezoidal wave and a ramp function, 29 is a digital trapezoidal wave A phase comparison counter 30 for latching is a latch circuit for latching the digital trapezoidal wave from the phase comparison counter 29 with a rotation phase signal and outputting phase error information.

Reference numeral 31 is a pulse width modulation (PW) that modulates the phase error information of the latch circuit 30 into a pulse width and converts it into analog voltage information.
M) circuit, 32 is a loop filter for smoothing the ripple component in the output of the pulse width modulation circuit 31 and performing phase compensation in the control loop, 13 is a current required for the motor 1 according to the output of the loop filter 32 In the case of a brushless motor, it is a motor driver that further distributes current to each phase of the motor 1.

Further, FIG. 4B is a diagram showing a digital trapezoidal wave, in which 33 is the axis of the number of count bits of the phase comparison counter 29, and the arrow indicates the increasing direction. 34 is the time axis and 35
Is a digital trapezoidal wave output from the phase comparison counter 29,
36 is the output of the PG waveform shaping circuit 3 (see FIG. 4 (c)), 37
Indicates a latch point in the latch circuit 30. Next, the operation will be described. When the motor 1 rotates, the detector 2 outputs the rotation phase information, and the small signal of the detector 2 is
The PG waveform shaping circuit 3 shapes the waveform to a TTL level. The clock generated by the oscillation circuit 4 is divided by the frequency dividing circuit 6 to the reference rotation frequency, and based on the reference rotation frequency signal and the digital trapezoidal wave information in the preset circuit 28, the phase comparison counter At 29, a digital trapezoidal wave 35 is output.

The rotation phase information signal 36 from the PG waveform shaping circuit 3 is latched on the digital trapezoidal wave at a point 37 in the latch circuit 30, and a quantized phase error is output. This quantized phase error is a pulse width modulation circuit. At 31, converted to analog voltage. Since the output of this pulse width modulation circuit is a digital waveform containing analog components, it is necessary to smooth this and also to perform phase compensation in the loop, so the loop filter 32 compensates and smoothes it. Is done. Then, a supply current corresponding to the output voltage of the loop filter 32 is supplied to the motor 1 by the motor driver 13, and a feedback loop is formed by the above circuits, whereby the motor rotation phase is locked at the reference rotation frequency phase. Then
Constant speed stable rotation can be performed.

[Problems to be solved by the invention]

Since the conventional motor control circuit is configured as described above, it is necessary to smooth the output of the pulse width modulation circuit, and it is necessary to insert an analog smoothing filter for that purpose. Since it is made, there is a problem that the circuit configuration becomes complicated.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a motor control circuit capable of removing an analog filter for smoothing and simplifying the circuit configuration.

[Means for solving problems]

A motor control circuit according to the present invention compares a phase of a rotation phase detector for detecting a rotation phase of a motor with a reference rotation frequency signal and a phase of a rotation phase signal of the motor detected by the rotation phase detector to rotate the motor. A phase comparator that outputs a signal that indicates the phase delay and lead of the phase signal, and a binary value that outputs a count direction instruction signal that indicates the counting direction in the up or down direction according to the signal that indicates the phase delay and lead Quantization circuit, the pulse train from the reference oscillator having a frequency sufficiently higher than the output of the phase comparator, counting in the up direction or the down direction according to the counting direction instruction signal, to the output after the phase comparison A sequential loop filter that removes existing noise, and a pulse is added to the reference frequency signal according to the output of the sequential loop filter or The pulse increasing / decreasing circuit to be removed, a frequency dividing circuit for smoothing the output of the pulse increasing / decreasing circuit, an F / V conversion circuit for performing F / V conversion on the output of the frequency dividing circuit, and an F / V conversion circuit And a motor drive circuit that controls the current supplied to the motor according to the output voltage.

[Action]

According to the present invention, with the above-described configuration, according to the two states of the phase delay state and the lead state,
The pulse train from the reference oscillator having a frequency sufficiently higher than the output from the phase comparator is counted in a sequential loop filter, thereby removing the noise present in the output after the binary quantization from the output of the phase comparator. do it,
Generate a pulse amplified signal that does not respond to noise immediately, increase or decrease the pulse of the reference frequency signal based on this, smooth it by dividing it, and perform frequency / voltage conversion, then use the motor driver to rotate the motor rotation phase. To control.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings. First
FIG. 3A shows a motor control circuit according to an embodiment of the present invention. In the drawing, the same reference numerals as those in FIG. Reference numeral 7 is a reference rotation frequency signal f ₂ generated by the frequency dividing circuit 6.
And a phase comparator for comparing the phase of the rotation phase signal f ₃ which is the output of the PG waveform shaping circuit 3, and 8 outputs the output of the phase comparator 7 into a binary value of a phase lead and a phase delay. Quantizing circuit for quantizing, 9 is a sequential loop filter for removing noise components existing in the output after binary quantization,
Reference numeral 10 is a pulse increasing / decreasing circuit for adding or removing a pulse to / from the output f ₁ of the reference oscillation circuit 4, and 11 is an output of the pulse increasing / decreasing circuit 10.
Frequency divider for smoothing f ₅ , 12 is the output of frequency divider 11 f ₆
It is an F / V conversion circuit for converting the frequency information of the phase fluctuation of into a voltage.

Further, FIG. 1 (b) shows a concrete example of the phase comparator 7, and FIGS. 1 (c) and (d) show the input waveforms f ₂ and f ₃ thereof, respectively.
FIG. 1 (e) shows the output f ₄ of the phase comparator, and T1 and T2 respectively show the output pulse width after the phase comparison.

FIG. 1 (f) is a specific example of the binary quantization circuit 8 and the sequential loop filter 9. In the figure, 14 is 2
Value quantization circuit 8 and sequential loop filter 9
8a is its counter up input, 8b is its count down input, and
Is its reset input.

FIGS. 1 (g) to (n) are timing charts showing waveforms of respective parts of the block diagram of FIG. 1 (a).
16 is the output f ₁ of the reference oscillator circuit 4, and 17 is the output of the frequency divider circuit 6.
f ₂ and 18 are the outputs f ₃ of the PG waveform shaping circuit ₃ , and 19 is the phase comparator 7
The first view output f in the case of the configuration as shown in (b) _4, 20 is the output f ₅ in the case of the binary quantization circuit 8 and the sequential loop filter 9 in configuration of FIG. 1 (c) ,twenty one
Is the output f ₆ of the pulse increasing / decreasing circuit 10, 22 is the output of the frequency dividing circuit 11
f ₇ and 23 are outputs of the F / V conversion circuit 12.

Next, the operation will be described. When the disk motor 1 in FIG. 1 (a) rotates, the rotation phase detector 2 detects the rotation phase of the motor 1, and the PG waveform shaping circuit 3 shapes the detected phase information, and a TTL level rectangular wave f ₃ Output as. On the other hand, the clock f ₁ generated by the reference oscillation circuit 4 is frequency-divided by the frequency dividing circuit 6 to generate the reference rotation frequency f 2. If the phase comparator 7 is an exclusive OR type phase comparator as shown in FIG. 1 (d), f ₂ and f ₃
A signal such as f ₄ is output by the signal of. Here, when the pulse width duty of the phase comparison output f ₄ is 50% output (T ₁ = T ₂
Phase lock point, the phase lead information is
T ₂ −T ₁ and the phase delay information is T ₁ −T ₂ , which is, for example, “1” (“H” level) for phase lead and “0” (“L” level) for phase delay. A circuit having both the circuit characteristics of the binary quantization circuit 8 and the sequential loop filter 9 as shown in FIG. 1 (f) in order to quantize into a binary value and further remove the noise component of the phase comparator output. Quantize at.

FIG. 1 (f) shows a circuit that has both the characteristics of both circuits 8 and 9
It shows an example realized using the two-stage bidirectional counter 14,
The up input 8a of the counter 14 has an output f after phase comparison.
₄ , inverted input of f ₄ to down input 8b , And the reference oscillator circuit 4 for clock input.
Output f ₁ is input, and the count center number of the 2N-stage bidirectional counter 14 is set to N (that is, the count amount when T ₁ = T ₂ ),
When the count 2N terminal which is the output section and the count 0 terminal have outputs, the counter itself is reset (15).

With this configuration, the quantized phase error information that is the difference between T ₁ and T ₂ is applied to the 2N terminal and 0 terminal of the 2N-stage bidirectional counter 14.
When the noise component in the output of the phase comparator 7 is removed and f ₅ is output as shown in FIG. 1 (k), for example, when T ₁ > T ₂ and a phase delay occurs, the countdown time is longer. Becomes longer and a pulse is generated at 0 output. At this time, the pulse adding / removing circuit 10 is configured to perform pulse removal when inputting phase delay information and pulse addition when inputting phase advance information. When the pulse is increased or decreased, the output f ₁ of the reference oscillation circuit 4 is changed. The half frequency f1 / 2 should be the center output frequency of the pulse increase / decrease circuit 10 (f1 / 2 when additions are not removed)
If) configured to output itself, when the phase delay occurs, phase lag information output (FIG. 1 (k) refer) by f1 / 2 or more pulse rejection output f ₆ (first sequential loop filter 9 (See FIG. 1) is output according to the period in which the phase delay occurs. This is smoothed by the frequency dividing circuit 11 (see FIG. 1 (m)), and the smoothed output 22 is F /
When F / V conversion is performed by the V conversion circuit 12, in the case where the F / V conversion circuit has a characteristic that the low frequency direction is the voltage rising direction,
The phase error is output as an analog voltage output as shown in the timing chart 23.

This analog voltage output 23 is converted by the motor drive circuit 13 into a supply current amount. When the motor 1 is a brushless motor, the motor drive circuit 13 has therein a distributor for each phase of the motor 1.

With the above circuit configuration, a closed loop is formed, the motor rotation phase is locked to the phase of the reference rotation frequency, and the disk motor 1 can rotate at a constant speed and stably.

As described above, in the present embodiment, the pulse width output after phase comparison is quantized into binary values of leading or lagging of the phase, and after passing through the sequential loop filter to remove the noise component of the quantized output, Pulses are added or removed from the reference oscillator circuit output according to the quantized output period, the phase error information is converted to the amount of FM fluctuation, then digitally smoothed by the frequency divider circuit, and the F / V converter circuit is used. , Since it is configured to feed back as an analog drive voltage, the complicated circuit required for generating a digital trapezoidal wave unlike the conventional circuit is unnecessary, the circuit configuration is simplified, and the loop filter is digitized. It is possible to provide at low cost those with excellent temperature characteristics and control performance.

In the above embodiment, the case where the controlled object is a disk motor for driving the floppy disk of the electronic still camera has been described as an example, but other motors may be used as long as they require constant speed and stable rotation. The same effect as that of the above embodiment is obtained.

Further, in the above embodiment, the detection system is provided with only the rotational phase detector 2. However, as shown in FIG. 2, the frequency generator 24 detects the rotational speed of the motor 1 and outputs the FG waveform. The waveform is shaped by the shaping circuit 25, and the analog voltage is converted by the F / V conversion circuit 26, which is added to the output of the F / V conversion circuit 12 of the rotation phase control loop to simultaneously form the speed control loop. In addition to the effects of the above-described embodiment, it is possible to improve the synchronization characteristics at the start of the motor 1 and the steady characteristics.

In addition, as shown in Fig. 3, FG in the above speed control loop
The rotation speed error information after waveform shaping may be digitally frequency-added with the output of the frequency dividing circuit 11 of the phase control loop by the adding circuit 27, and this may be F / V converted. By configuring, even the addition part of the speed control system is digitized, and the characteristics of the system are similar to those of the system shown in Fig. 2; It is possible to obtain the system that has been set up.

〔The invention's effect〕

As described above, according to the motor control circuit of the present invention, the rotation phase detector that detects the rotation phase of the motor, the reference rotation frequency signal, and the phase of the rotation phase signal of the motor detected by the rotation phase detector. And a phase comparator that outputs a signal indicating the phase delay and lead of the rotation phase signal of the motor, and a counting direction that supports the up or down counting direction according to the signal indicating the phase delay and lead. A binary quantizing circuit that outputs a supporting signal and a pulse train from a reference oscillator having a frequency sufficiently higher than the output of the phase comparator are counted in an up direction or a down direction according to the counting direction supporting signal. A sequential loop filter for removing noise existing in the output after the phase comparison, and a reference frequency signal according to the output of the sequential loop filter. Pulse adding / removing circuit, a frequency dividing circuit for smoothing the output of the pulse increasing / decreasing circuit, an F / V converting circuit for F / V converting the output of the frequency dividing circuit, and Equipped with a motor drive circuit that controls the supply current to the motor according to the output voltage of the V conversion circuit, and removes noise by counting pulse trains with a frequency sufficiently higher than this from the output of the phase comparator in a sequential filter However, by increasing or decreasing the pulse of the above pulse train and dividing the increased or decreased pulse train to obtain a smoothed motor control output, the control system from the motor rotation detector to the F / V converter is The processing of the control signals required to configure the device can be performed in binary, and it is extremely resistant to ambient temperature changes, and the system is simple, inexpensive, and highly controllable. .

[Brief description of drawings]

FIG. 1 is a diagram showing a disk motor control circuit according to an embodiment of the present invention, and FIG. 1 (a) is a block configuration diagram thereof.
FIG. 1 (b) is a diagram showing a concrete configuration example of the phase comparator of FIG. 1 (a), and FIGS. 1 (c) to (e) are the input / output waveforms of FIG. 1 (b). Fig. 1 (f) shows 2 of Fig. 1 (a).
The figure which shows the specific example of a value quantization and a sequential loop filter, and FIG. 1 (g)-(n) is a timing chart figure which shows the operation timing of the block diagram of FIG. 1 (a). FIG. 2 is a block diagram showing another embodiment of the present invention, FIG. 3 is a block diagram showing still another embodiment of the present invention, and FIG.
The figure shows the conventional control circuit of the disk motor.
FIG. 4A is a block diagram thereof, FIG. 4B is a diagram showing a digital trapezoidal wave in a conventional disc motor control circuit, and FIG. 4C is rotational phase information of FIG. 4A. It is a figure which shows a signal. 1 ... Motor, 2 ... Rotation phase detector, 3 ... PG waveform shaping circuit, 4 ... Reference oscillation circuit, 5 ... Crystal oscillator, 6,11
...... Dividing circuit, 12,26 …… F / V conversion circuit, 13 …… Motor drive circuit, 14 …… 2 N-stage bidirectional counter, 7 …… Phase comparator, 8 …… Binary quantization circuit, 9 …… Sequential loop filter, 10 …… Pulse increase / decrease circuit, 24 …… Frequency generator, 25 …… FG waveform shaping circuit, 27 …… Adding circuit, 28 ……
Preset circuit, 29 …… Phase comparison counter, 30 …… Latch circuit, 31 …… Pulse width modulation circuit, 32 …… Loop filter. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (3)

[Claims] 1. A rotation phase detector for detecting a rotation phase of a motor, and a phase of the rotation phase signal of the motor by comparing a reference rotation frequency signal and a phase of the rotation phase signal of the motor detected by the rotation phase detector. A phase comparator that outputs a signal indicating the delay and advance of the phase, and a binary quantization circuit that outputs a counting direction instruction signal that indicates the counting direction in the up or down direction according to the signal indicating the delay and the advance of the phase. , A pulse train from a reference oscillator having a frequency sufficiently higher than the output of the phase comparator is counted in an up direction or a down direction in accordance with the counting direction instruction signal to eliminate noise existing in the output after the phase comparison. Sequential loop filter to be removed, and pulse increase / decrease to add or remove pulses to / from the reference frequency signal according to the output of the sequential loop filter A circuit, a frequency dividing circuit for smoothing the output of the pulse increasing / decreasing circuit, an F / V converting circuit for performing F / V conversion on the output of the frequency dividing circuit, and an output voltage of the F / V converting circuit. And a motor drive circuit for controlling a current supplied to the motor. 2. An F / V conversion output of a speed generator output for detecting the rotation speed of the motor is added to the output of the F / V conversion circuit in an analog manner. The motor control circuit according to item 1. 3. The motor control according to claim 1, wherein an output of a speed generator for detecting a rotation speed of the motor is digitally added to an output of the frequency dividing circuit. circuit.