JPH07101983B2 - Gate control device for thyristor valve - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention supplies a gate pulse to a thyristor valve in which a plurality of thyristors used for direct current power transmission or the like are connected in series or in parallel. The present invention relates to a gate control device for a thyristor valve.

(Prior Art) FIG. 3 shows an embodiment of a conventional gate control device for a thyristor valve. A system gate pulse generator 1A,
The B-system gate pulse generator 1B has the same configuration and includes flip-flop circuits 2A and 2B, AND circuits 3A and 3B, wasted circuits 4A and 4B, amplifier circuits 5A and 5B, switching elements 6A and 6
B, LED for optical cyclistr trigger 7A-1 to 7A-N ・ 7B-1
~ 7B-N, LED for optical gate pulse monitor 8A / 8B, DC power supply 9A
・ 9B, resistors 10A ・ 10B, ride guides 11A ・ 11B, optical-electrical signal conversion circuits 12A ・ 12B and one-shot circuits 14A ・ 14B, inverting circuits 15A ・ 15B, flip-flop circuits 16A ・ 16B Phase detection circuits 13A and 13B, on-delay circuits 17A and 17B, protection circuits 18A and 18B and on-delay circuits 20A and 20B, wasshot circuits 22A and 22B, inverting circuit 23A
23B and forward voltage signal abnormality detection circuits 19A and 19B that are composed of flip-flop circuits 24A and 24B. The thyristor bulb 25 is an optical thyristor 26-1 to 26-
N, voltage dividing resistors 27-1 to 27-N, forward voltage detectors 28-1 to 28N,
It is composed of a reverse voltage detector 29 and the like. The A system gate pulse generator 1A, the B system gate pulse generator 1B, and the thyristor valve 25 are connected via ride guides 30-1 to 30-N. The photoelectric converter 31 includes an optical-electrical signal conversion circuit 32.
-1 to 32-N, 33, and an OR circuit 34. The thyristor bulb 25 and photoelectric converter 31 are light guide 35-
1 to 35-N, 36 are connected.

When a forward voltage is applied to the optical thyristors 26-1 to 26-N of the thyristor valve 25, forward voltage signals are detected by the forward voltage detectors 28-1 to 28-N. The detected forward voltage signal is transmitted as an optical signal to the optical-electrical signal conversion circuits 32-1 to 32-N of the photoelectric converter 31 by the light guides 35-1 to 35-N. The electrical signals converted by the optical-electrical signal conversion circuits 32-1 to 32-N are input to the OR circuit 34. The OR circuit 34 outputs the forward voltage signal FV of the thyristor valve 25.

On the other hand, the phase control signal PHS indicating the conduction period of the thyristor valve 25, which is output from the control device (not shown), is input to the flip-flop circuits 2A and 2B. Outputs of flip-flop circuits 2A and 2B, phase control signal PHS 'and forward voltage signal FV
Is input to the AND circuits 3A and 3B, and when the AND condition is satisfied, its output is input to the one-shot circuits 4A and 4B. The one-shot circuits 4A and 4B output pulse signals, are amplified by the amplifier circuits 5A and 5B, and output this signal as a firing command to drive the switching elements 6A and 6B. When these switching elements 6A and 6B are turned on, the optical thyristor trigger LEDs 7A-1 to 7A-N, 7B-1 to 7B
B-N generates an optical signal by the current from the DC power supplies 9A and 9B, and is transmitted to the optical thyristors 26-1 to 26-N as optical gate pulses through the light guides 30-1 to 30-N. It will be fired.

When the thyristor valve 25 is ignited, the forward voltage becomes almost "0", so the forward voltage signal FV becomes "0", and the AND circuits 3A, 3B.
Condition is not satisfied and the optical gate pulse is not output, that is, the phase control signal PHS 'exists or the phase control signal PHS' exists when the forward voltage is applied to the thyristor valve 25. Thyristor valve in period 2
When a forward voltage is applied to 5, an optical gate pulse is output,
The thyristor valve 25 will be fired.

When a reverse voltage is applied to the optical thyristors 26-1 to 26-N of the thyristor bulb 25, the optical thyristors 26-1 to 26-N are extinguished, and the reverse voltage signal is detected by the voltage sending detector 29, and The signal is transmitted by the light guide 36 to the optical-electrical signal conversion circuit 33 of the photoelectric converter 31. Optical-electrical signal conversion circuit
The electric signal converted by 33 is input to the on-delay circuits 17A and 17B as the reverse voltage signal RV of the thyristor valve 25.
Reverse voltage signal R during the period when phase control signal PHS is "0"
When the width of V is longer than the time limit T _{1 of} the on-delay circuits 17A and 17B, the output “1” of the on-delay circuits 17A and 17B resets the outputs of the flip-flop circuits 2A and 2B and the phase control signal PHS ′. Set to 0 ". FV when PHS 'signal becomes "0"
Even if the signal becomes "1", the conditions of the AND circuits 3A and 3B are not satisfied, so that the optical gate pulse is not generated. Therefore, the optical thyristors 26-1 to 26-N do not fire and remain in this state until the PHS signal from the control device (not shown) becomes "1" in the next cycle. In addition, the time limit T _{1 of} the on-delay circuit 17A / 17B
Is determined from the reverse recovery time of the optical thyristors 26-1 to 26-N.

The optical signals from the optical gate pulse monitor LEDs 8A and 8B are monitored by the light guides 11A and 11B as optical gate pulse monitors.
It is transmitted to the optical-electrical signal conversion circuits 12A and 12B. The electrical signals converted by the optical-electrical signal conversion circuits 12A and 12B are the one-shot circuits 14A and 14B of the gate pulse open phase detection circuits 13A and 13B.
Entered in.

If the optical gate pulse of the A-system gate pulse generator 1A is not generated for some reason and the output of the optical-electrical signal conversion circuit 12A continues for a time T ₂ or more of the one-shot circuit 14A,
That is, if the optical gate pulse is not output for the time period T ₂ or more of the one-shot circuit 14A, the output of the one-shot circuit 14A becomes "0" and it is inverted by the inverting circuit 15A, and the set signal becomes "1". Set circuit 16A. The output "1" of the flip-flop circuit 16A is the gate pulse open phase signal PF-A of the gate pulse open phase detection circuit 13A.
Is transmitted to the protection circuit 18A. The protection circuit 18A performs an appropriate protection operation such as stopping the A system gate pulse generator 1A in which an abnormality has occurred, and continues the operation by the optical gate pulse of the B system gate pulse generator 1B which remains as the system.

Although the gate pulse open phase abnormality of the A system gate pulse generator 1A has been described here, the same applies to the gate pulse open phase abnormality of the B system gate pulse generator 1B.

For some reason, the forward voltage signal FV remains “0” even if the forward voltage is applied to the thyristor valve 25, or the time delay T of the on-delay circuit 20A of the forward voltage signal abnormality detection circuit 19A is increased. For a short FV signal of ₃ or less, the output of the on-delay path 20A becomes “0”. When such a state continues for the time period T ₄ of the one-shot circuit 22A or more, the output of the one-shot circuit 22A becomes "0", which is inverted by the inverting circuit 23A and the set signal becomes "1". Set circuit 24A. The output "1" of the flip-flop circuit 24A is transmitted to the protection circuit 18A as the forward voltage non-signal FVF-A of the forward voltage signal abnormality detection circuit 19A, and the A system gate pulse generator 1A which has become abnormal is appropriately stopped. Perform a protective action.

Although the forward voltage signal abnormality of the A-system gate pulse generator 1A has been described here, the same applies to the forward voltage signal abnormality of the B-system gate pulse generator 1B.

(Problems to be Solved by the Invention) However, the conventional gate control device having such a configuration has the following problems. This will be described with reference to FIG.

For some reason, the flip-flop circuit 2A of the system A gate pulse generator 1A is Kitaichi abnormal time T _a later, when the phase control signal PHS 'is not reset, became leave becomes "1", the thyristor valve As soon as the forward voltage is applied to 25 and the forward voltage signal FV is input to the AND circuit 3A, the condition of the AND circuit 3A is satisfied and the optical gate pulse GP-A
Occurs, the phase control does not work, and the thyristor valve 25 is ignited. When the thyristor valve 25 is ignited, the forward voltage becomes almost “0”, so the width of the FV signal becomes extremely short. The width of this FV signal becomes shorter than the time period T ₃ of the on-delay circuit 20A of the forward voltage signal abnormality detection circuit 19A, and the output a of the on-delay circuit 20A becomes "0". Therefore, the one-shot circuit 22A is not triggered. In such a state, when the time period T _{4 of} the one-shot circuit 22A elapses, the output b of the one-shot circuit 22A becomes "0", which is inverted by the inverting circuit 23A and the set signal becomes "1". set. The output of the flip-flop circuit 24A becomes "1" and is transmitted to the protection circuit 18A as a forward voltage non-signal FVF-A, and the protection circuit 18A stops the protection of the A system gate pulse generator 1A.

On the other hand, after the time T _a , for example, at the time T _b , the B-system gate pulse generator 1B does not satisfy the AND condition in the AND circuit 3B because the FV signal is “0” even if the PHS ′ signal is “1”. Pulse GP-B does not occur. This state is the time limit T ₂ of the one-shot circuit 14B of the gate pulse open phase detection circuit 13B.
After a lapse of time, the output c of the one-shot circuit 14B becomes "0" and is inverted by the inverting circuit 15B and the set signal becomes "1", so that the flip-flop circuit 16B is set. The output of the flip-flop circuit 16B becomes "1" and is transmitted to the protection circuit 18B as the gate pulse open phase signal PS-B, and the protection circuit 18B also stops the protection of the B system gate pulse generator 1B. Alternatively, the width of the FV signal is the forward voltage signal abnormality detection circuit.
On-delay circuit of 19B is shorter than the time limit T _{3 of} 20B, so it is a one-shot circuit as in the case of A-system gate pulse generator 1A.
When 22B is not triggered, the forward voltage no signal FVF-B is sent to the protection circuit 18B when the time period T ₄ elapses, and the protection circuit 18B
As a result, the B-system gate pulse generator 1B is protected and stopped.

A system gate pulse generator 1A, B system gate pulse generator 1B
When the protection gates are stopped together and the optical gate pulse is not generated and the thyristor valve 25 is not ignited, the voltage waveform V _VAL of the thyristor valve 25 becomes a sine wave as shown in FIG.

As described above, due to the failure of the A-system gate pulse generator 1A,
In case of abnormal FV signal, B system gate pulse generator
If the optical gate pulse GP-B of 1B cannot be generated, or if an abnormal FV signal is detected, even the B system gate pulse generator 1B, which is a sound system of the dual system, is protected and stopped, and the entire system becomes There was a problem that it stopped.

An object of the present invention is to stop protection of only the failed gate pulse generator in the case of a failure in which the gate pulse of the other gate pulse generator cannot be generated normally due to the failure of one gate pulse generator, and the other Is to provide a gate control device for a thyristor valve that can continue to operate.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides an AND between an energization period command signal of a thyristor valve and a forward voltage signal of the thyristor valve, as shown in FIG. Under the condition that a forward voltage is applied to the thyristor valve for a predetermined period, a pulse generating means for supplying an ignition signal to the thyristor valve, a monitor means for generating a pulse signal synchronized with an output pulse of the pulse generating means, A forward voltage abnormality signal is output when a pulse signal that is generated and disappears when the forward voltage disappears and a pulse signal from the monitor means on the other side are applied, and if any of these pulse signals does not occur for a predetermined period. If the forward voltage signal abnormality detecting means and the pulse signal of the monitoring means disappear, and the ignition signal is not generated for a desired period longer than the predetermined period. Two sets of gate pulse open phase detection means for generating a gate pulse open phase signal and two sets of protection means for applying the forward voltage abnormality signal and the gate pulse open phase signal to stop the supply of the ignition signal to the thyristor valve are provided. It is characterized in that it is composed of a double system.

(Operation) With the configuration described above, when the gate pulse generator (1A) of the A system fails, for example, as shown in FIG. 2, the forward voltage T ₃ forward voltage is applied to the thyristor valve 25 for the scheduled period. pulse signal is applied to disappear by generated gone forward voltage conditions, the output signal of the forward voltage signal abnormality detecting means 19A of the pulse signal to output a forward voltage abnormality signal when the predetermined time period T ₄ does not occur FVF -A causes the gate pulse generator 1A of the A system to stop the gate pulse GP-A after the T ₄ period, but generates the gate pulse of the other side to the forward voltage signal abnormality detecting means 19B of the gate pulse generator 1B of the B system. the gate pulse generator 1B of the B system within the period T ₂ since the pulse signal synchronized with the firing signal of the vessel and an OR circuit 21B is applied via the and T _2> T ₄ generates a gate pulse GP-B Because it can be done, A type gate Even if the pulse generator 1A fails, the B-system gate pulse generator 1B can continue to operate the thyristor valve.

(Embodiment) The configuration of an embodiment of the present invention will be described with reference to FIG. The A-system gate pulse generator 1A and the B-system gate pulse generator 1B have almost the same configuration, but the configuration of the forward voltage signal abnormality detection circuits 19A and 19B is different from that of the embodiment of the prior art as follows. ing.

In one embodiment of the present invention, OR circuits 21A and 21B are added, the output of the on-delay circuits 20A and 20B is input to one of the inputs, and the optical-electrical signal conversion for gate pulse monitoring of the other phase is input to the other input. Input the output of circuits 12A and 12B. Further, the outputs of the OR circuits 21A and 21B are input to the one-shot circuits 22A and 22B.

That is, the output of the optical-electrical signal conversion circuit 12A, 12B was input to the one-shot circuit 14A, 14B of the gate pulse open phase detection circuit 13A, 13B, respectively, in the present invention, the optical-electrical signal conversion circuit The output of 12A is output to the one-shot circuit 14A of the gate pulse open phase detection circuit 13A and the OR circuit 21B of the forward voltage signal abnormality detection circuit 19B of the B-system gate pulse generator 1B to the output of the optical-electrical signal conversion circuit 12B. One shot circuit 14B of gate pulse open phase detection circuit 13B and OR circuit 21A of forward voltage signal abnormality detection circuit 19A of A system gate pulse generator 1A
It is configured to input to each of the two.

In addition, the time limit T ₂ of the one-shot circuits 14A and 14B of the gate pulse open phase detection circuits 13A and 13B is set to the forward voltage signal abnormality detection circuit 19A.
・ It is configured to be longer than the time limit T _{4 of the} 19B one-shot circuits 22A and 22B.

Structure of thyristor valve 25 and photoelectric converter 31, connection between A system gate pulse generator 1A, B system gate pulse generator 1B and thyristor valve light guides 30-1 to 30-N, thyristor valve 25 and photoelectric converter 31 Light guide
The connection by 35-1 to 35-N, 36 is the same as that of the embodiment of the prior art.

A system gate pulse generator 1A, B system gate pulse generator 1B
When both are normal, the operation of the embodiment of the present invention is similar to the operation of the embodiment of the prior art.

The operation when the A-system gate pulse generator 1A becomes abnormal will be described with reference to FIGS. 1 and 2.

For some reason, the A system gate pulse generator 1A
If _a failure occurs in which the phase control signal PHS ′ remains “1” after T _a , the forward voltage of the thyristor valve 25 is detected, and as soon as the forward voltage signal FV is input to the AND circuit 3A, the AND circuit 3A turns off. When the condition is satisfied, the optical gate pulse GP-A is generated, the phase control does not work, and the thyristor valve 25 is ignited. When the thyristor valve 25 is ignited, the forward voltage becomes almost “0”, so the width of the FV signal becomes extremely short and is shorter than the time limit T ₃ of the on-delay circuit 20A of the forward voltage signal abnormality detection circuit 19A. The output a of the on-delay circuit 20A becomes "0". On the other hand, B-series gate pulse generator 1B is time T _b after,
AND circuit 3 because the FV signal is "0" even if the PHS 'signal is "1"
The condition B is not satisfied, and the optical gate pulse GP-B is not generated. Therefore, the output GPM of the optical-electrical signal conversion circuit 12B-
B becomes "0". Therefore, since the inputs of the OR circuit 21A of the forward voltage signal abnormality detection circuit 19A of the A system gate pulse generator 1A are both "0", the output d of the OR circuit 21A becomes "0" and the one-shot circuit 22A is not triggered. From the previous FV signal,
When such a state elapses the time period T ₄ of the one-shot circuit 22A, the output b of the one-shot circuit 22A becomes "0" and is inverted by the inverting circuit 23A and the set signal becomes "1", so that the flip-flop circuit 24A. Set. The output of the flip-flop circuit 24A becomes "1" and no forward voltage signal FVF-A
Is transmitted to the protection circuit 18A as a result of the protection circuit 18A, the system A gate pulse generator 1A detects an abnormality and stops protection, and an operation of a protection circuit (not shown) causes an optical gate pulse to be output after time T _c. Disappear.

On the other hand, the time T _{c at which} the A system gate pulse generator 1A stops protection
In the former B-system gate pulse generator 1B, the width of the FV signal is shorter than the time period T ₃ of the on-delay circuit 20B of the forward voltage signal abnormality detection circuit 19B as in the case of the A-system gate pulse generator 1A described above. The output a of the on-delay circuit 20B becomes "0". However, since the A-system gate pulse generator 1A generates an optical gate pulse, the output GPM-A of the optical-electrical signal conversion circuit 12A becomes "1". Therefore, one input of the OR circuit 21B of the forward voltage signal abnormality detection circuit 19B becomes "1", and its output d becomes "1", triggering the one-shot circuit 22B. Therefore, the width of the FV signal is the time T of the on-delay circuit 20B.
Even when the time shorter than _{3 is} longer than the time limit T _{4 of} the one-shot circuit 22B, the one-shot circuit 22B is still provided with the trigger, so the output b of the one-shot circuit 22B remains "1". It is inverted at 23B, the set signal remains "0", and the flip-flop circuit 24B is not set. Therefore, even if the FV signal becomes abnormal due to the failure of the A-system gate pulse generator 1A, the forward voltage non-signal FVF-B of the B-system gate pulse generator 1B is not output and remains at "0". The pulse generator 1B is not protected. On the other hand, PH
Since the FV signal becomes "0" before the S'signal becomes "1", the condition of the AND circuit 3B of the B system gate pulse generator 1B is not satisfied, and the optical gate pulse GP-B is not generated. The output GPM-B of the electric signal conversion circuit 12B becomes "0". In such a state, when the time period T ₂ of the one-shot circuit 14B of the gate pulse open phase detection circuit 13B elapses, its output c becomes "0" and is inverted by the inversion circuit 15B, so that the set signal becomes "1". The flip-flop circuit 16B is set. The output of the flip-flop circuit 16B becomes "1" and is transmitted to the protection circuit 18B as the gate pulse open phase signal PF-B, and the protection circuit 18B tries to stop the protection of the B system gate pulse generator 1B. However, the time period T ₂ of the one-shot circuit 14B of the gate pulse open phase detection circuit 13B of the B-system gate pulse generator 1B is the time period T ₂ of the one-shot circuit 22A of the forward voltage signal abnormality detection circuit 19A of the A-system gate pulse generator 1A. Since it is set longer than _{4, when the} A system gate pulse generator 1A stops protection at time T _c after the time limit T ₄ of the one-shot circuit 22A has elapsed, A
When the optical gate pulse GP-A from the system gate pulse generator 1A disappears and the PHS 'signal of the B system gate pulse generator 1B becomes "1", the condition of the AND circuit 3B is established, and the optical gate pulse GP-B becomes Is generated. Therefore, the thyristor valve 25
Is ignited by the optical gate pulse GP-B of the B-system gate pulse generator 1B. Since the optical gate pulse GP-B has already been generated after the time T ₂ of the one-shot circuit 14B of the gate pulse open phase detection circuit 13B has passed, the one-shot circuit
The input of 14B becomes "1". Therefore, the output c of the one-shot circuit 14B remains "1" as shown in FIG.
The flip-flop circuit 16B is not set because it is inverted in 15B and the set signal remains "0". Therefore, the gate pulse open phase signal PF-B is not output and remains "0" as shown in FIG. 2, and the B system gate pulse generator 1B continues to operate without being stopped for protection. That is, the B-system gate pulse generator 1B can continue to operate without the forward voltage signal abnormality detection circuit 19B or the gate pulse open phase detection circuit 13B operating. The above is the case where the A system gate pulse generator 1A is abnormal, but the same is true when the B system gate pulse generator 1B is abnormal.

In the above description, the gate pulse open phase detecting means is
Although the gate pulse open phase signal is generated when the ignition signal to the thyristor valve is not generated for a desired period after the ignition signal is lost, the invention is not limited to such a signal, for example, a thyristor valve The gate pulse open phase signal may be generated when the state in which the ignition signal is not supplied to the thyristor valve continues for a desired period despite the presence of the energization period command signal.

As described above, according to the present invention, the failure mode in which the forward voltage signal of the thyristor valve becomes abnormal due to the failure of one gate pulse generator and the gate pulse of the other gate pulse generator cannot be normally generated. In this case, it is possible to provide a gate controller for the thyristor valve, which can stop the protection of the failed gate pulse generator and keep the other healthy gate pulse generator in operation.

[Brief description of drawings]

FIG. 1 is a block diagram of a gate control device for a thyristor valve showing an embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of an embodiment of the present invention, and FIG. 3 is a conventional thyristor valve. FIG. 4 is a configuration diagram of the gate control device of FIG. 4, and FIG. 4 is a diagram showing a time chart for explaining the operation of the conventional gate control device of the thyristor valve. 1A ... A system gate pulse generator, 1B ... B system gate pulse generator, 2A / 2B ... flip-flop circuit, 3A / 3B ... AND circuit, 4A / 4B ... one-shot circuit, 5A / 5B ... … Amplifier circuit, 6A ・ 6B …… Switching element, 7A-1 to 7A-N ・ 7B-1 to 7B-N …… LED for optical thyristor trigger, 8A ・ 8B …… LED for optical gate pulse monitor, 9A ・ 9B ...... DC power supply, 10A ・ 10B ...... Resistance, 11A ・ 11B ...... Light guide, 12A ・ 12B …… Optical-electrical signal conversion circuit, 13A ・ 13B …… Gate pulse open phase detection circuit, 14A ・ 14B …… One Shot circuit, 15A ・ 15B …… Inversion circuit, 16A ・ 16B …… Flip-flop circuit, 17A ・ 17B …… On-delay circuit, 18A ・ 18B …… Protection circuit, 19A ・ 19B …… Forward voltage signal abnormality detection circuit, 20A・ 20B …… on-delay circuit, 21A ・ 21B …… OR circuit, 22A ・ 22B …… one-shot circuit, 23A ・ 23B …… anti Circuits, 24A / 24B ... Flip-flop circuits, 25 ... Thyristor valves, 26-1 to 26-N ... Optical thyristors, 27-1 to 27-N ... Voltage dividing resistors, 28-1 to 28-N ... … Forward voltage detector, 29 …… Reverse voltage detector, 30-1 to 30-N …… Light guide, 31 …… Photoelectric converter, 32-1 to 32-N, 33 …… Optical-electrical signal conversion circuit , 34 ... OR circuit, 35-1 to 35-N, 36 ... Light guide, PHS / PHS '... Phase control signal, FV ... Forward voltage signal, RV ... Reverse voltage signal, FVF-A / FVF -B: No forward voltage signal, PF-A / PF-B: Gate pulse open phase signal, GPM-A / GPM-B: Optical gate pulse monitor signal, V _VAL: Thyristor valve voltage waveform.

Claims (2)

[Claims] 1. A pulse generating means for supplying an ignition signal to the thyristor valve under an AND condition of an energization period command signal of the thyristor valve and a forward voltage signal of the thyristor valve, and a pulse synchronized with an output pulse of the pulse generating means. A monitor means for generating a signal, a pulse signal generated under the condition that a forward voltage is applied to the thyristor valve for a predetermined period and disappeared when the forward voltage disappears, and a pulse signal from the monitor means on the other side is applied. And a forward voltage signal abnormality detecting means for outputting a forward voltage abnormality signal when one of these pulse signals does not occur for a predetermined period, and a desired period ignition longer than the predetermined period after the pulse signal of the monitor means disappears. Gate pulse open phase detection means for generating a gate pulse open phase signal when no signal is generated; A protective pulse stop phase signal is applied to stop the supply of the ignition signal to the thyristor valve, and two sets of each of the above units are provided.
A gate control device for a thyristor valve, characterized by being configured with a heavy system. 2. A pulse generating means for supplying an ignition signal to the thyristor valve under an AND condition of a thyristor valve energization period command signal and a forward voltage signal of the thyristor valve, and a pulse synchronized with an output pulse of the pulse generating means. A monitor means for generating a signal, a pulse signal generated under the condition that a forward voltage is applied to the thyristor valve for a predetermined period and disappeared when the forward voltage disappears, and a pulse signal from the monitor means on the other side is applied. The forward voltage signal abnormality detecting means for outputting a forward voltage abnormality signal when any of these pulse signals does not occur for a predetermined period, and a point to the thyristor valve in spite of the energization period command signal of the thyristor valve. A gate pulse that generates a gate pulse open phase signal when there is no arc signal for a desired period longer than the predetermined period. A phase failure detector, the forward voltage abnormality signal and the gate pulse phase loss signal is applied with a protective means for stopping the supply of the firing signal to the thyristor valve, each of said means, each of two sets provided 2
A gate control device for a thyristor valve, characterized by being configured with a heavy system.