JPH07104482B2 - Automatic focus adjustment device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic focus adjustment device for an optical device such as a camera, and more particularly to an analog signal process for calculating a phase difference detected when detecting a focus of an image pickup optical system. The present invention relates to an automatic focus adjusting device suitable for use in an automatic focus adjusting device for a camera.

[Conventional technology]

An automatic focus adjusting device used in a conventional automatic focus adjusting device of an optical device such as a camera has a configuration shown in FIG. 12, and further includes a condenser on a further rear side of an image pickup equivalent surface 2 located on the rear side of a photographing lens 1. The lens 3, the separator lens 4, and the phase difference detection device are sequentially arranged.

The phase difference detection device is a CCD that receives a pair of subject images formed by the separator lens 4 and photoelectrically converts them.
And the like, and a processing circuit 7 for determining the in-focus state based on an electrical signal generated according to the luminous intensity distribution in each pixel of the line sensors 5, 6.

The image formation on the line sensors 5 and 6 approaches the optical axis 8 side in the front focus state in which the subject image is located in front of the imaging equivalent surface 2, and conversely from the optical axis 8 in the rear focus state. When it is moved away and in focus, it is at a predetermined position between the front pin and the rear pin. Therefore, the processing circuit 7 determines the in-focus state by detecting the position of the image formation from the optical axis 8 based on the electric signals generated by the respective line sensors 5 and 6. A phase difference detection method is used to detect the position of image formation on the line sensors 5 and 6. This method uses the following equation (1)
By calculating the correlation calculation value of a pair of image formations on the line sensors 5 and 6 by the calculation based on, the focusing state is determined based on the relative movement amount (phase difference) of these image formations until the correlation calculation value becomes minimum. Determine.

However, l is an integer from 1 to 9 and indicates the relative movement amount.

However, when l = 1, the shift operation is not performed,
The shift operation is performed when l ≧ 2.

For example, B (k) is an electrical signal output from each pixel of the line sensor 5 in time series, R (k + 1-1) is an electrical signal output from each pixel of the line sensor 6 in time series, and l When the calculation of the above equation (1) is performed every time the value is changed from 1 to 9, correlation calculation values H (1), H (2), ... H
(9) is obtained. For example, when the correlation calculation value H (5) is the minimum value, it is set in advance as the in-focus state, and when the correlation calculation value at the position deviated from this is the minimum value, the deviation amount, that is, l The phase difference up to = 5 can be detected as the focus shift (defocus amount).

The structure of the conventional processing circuit 7 is shown in FIG. An analog electric signal B generated by each pixel of the line sensors 5 and 6
(K) and R (k) are converted into 8-bit digital data by the A / D converter 9, and a microcomputer
The data is temporarily stored in a RAM (Random Access Memory) 11 via 10, and then the calculation of the above formula (1) is performed based on these digital data.

[Problems to be solved by the invention]

However, in such a conventional automatic focus adjustment device, since the calculation processing of the phase detection at the time of detecting the focus of the image pickup optical system is performed by the digital signal processing using the microcomputer or the like, the high speed and In order to perform a highly accurate operation, an expensive A / D converter or the like is required, and a rounding error caused by the quantization of a microcomputer that performs the operation causes a decrease in the operation accuracy,
Further, there is a problem that the load of designing a computer program for arithmetic processing becomes large and a storage device for storing a large amount of digital data is required, so that the number of parts is large and the device becomes large. .

The present invention has been made in view of such circumstances,
An object of the present invention is to provide an automatic focus adjustment device having a simple configuration and capable of performing focusing control of an imaging optical system on a subject at high speed and with high accuracy.

[Means for solving problems]

In order to achieve the above object, the present invention detects the relative position of a pair of optical images of a subject to determine whether or not the imaging optical system is in the in-focus state. In an automatic focus adjustment device that performs focusing by driving the imaging optical system in the optical axis direction to reach the focused state based on the target position, a plurality of photoelectric conversion elements arranged in a line and A CCD shift register unit that transfers charges read out from the photoelectric conversion element in the horizontal direction, and a CCD that is arranged in parallel in the CCD shift register unit and that transfers charges bidirectionally in parallel with the CCD shift register unit. A pair of sensors including a floating gate and an output unit that sequentially outputs an analog electric signal corresponding to an optical image on a pixel-by-pixel basis based on the charges transferred to the CCD floating gate. When a pair of analog electric signals corresponding to the optical image of is output, the charge of the CCD floating gate is transferred to the CCD shift register unit, and the CCD shift register unit transfers one pixel in the horizontal direction, and then the charges are again transferred. To the CCD floating gate to perform a correlation operation between the sensor means for non-destructively outputting a pair of analog electric signals while displacing each pixel unit in a predetermined cycle, and the pair of analog electric signals output from the sensor means. An analog calculation means for outputting a correlation calculation value; a means for obtaining a pixel shift amount that minimizes the correlation calculation value based on the correlation calculation value output in time series from the analog calculation means; and an imaging optical system. A defocus amount is calculated from the driving unit that drives in the optical axis direction and the obtained pixel shift amount, and the imaging light is calculated according to the defocus amount. It is characterized in that and a control means for controlling the driving means to drive the system to a focusing position on the optical axis.

[Action]

In the automatic focus adjusting device according to the present invention, a pair of sensors forming a sensor means in which a plurality of photoelectric conversion elements forming one pixel are arranged in a line via an image pickup optical system are provided respectively to an optical image of a subject. Is imaged.

From the sensor means, a pair of analog electric signals corresponding to the luminous intensity distributions of the pair of optical images are non-destructively output while being shifted for each pixel unit at a predetermined cycle. The pair of analog electric signals output from the sensor means are subjected to correlation calculation by the analog calculation means, and correlation calculation values are output in time series.

The correlation calculation value output from the analog calculation means is compared in magnitude by the comparison means, and based on the comparison result, the control means determines from the pixel position at the time of focusing of the pixel position of the sensor means having the minimum correlation calculation value. The amount of deviation is calculated, the defocus amount is calculated from the amount of deviation, and the driving unit is controlled so as to drive the imaging optical system by the defocus amount in the direction in which the imaging optical system is in the focused state.

〔Example〕

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of a camera equipped with an automatic focus adjustment device to which the present invention is applied. In the figure, the zoom lens 20 includes a focus lens group 20A for forming a subject image on the focal plane, a variator lens group 20B for changing the focal length, and a compensator lens for correcting defocus caused by movement of the focal length. It is composed of a group 20C and master lens groups 20D and 20E. A diaphragm 22 is arranged between the compensator lens group 20C and the master lens group 20D. Also, the master lens group 20
A beam splitter 24 is arranged between D and 20E.

The focus lens group 20A is held by a first inner cylinder (not shown) and is inserted into the first outer cylinder. The focus lens group 20A can be moved in the optical axis direction by rotating the first outer cylinder, and the rotation of the outer cylinder is performed by the DC motor 66. DC motor 66 is a motor drive circuit
It is designed to be driven to rotate by a drive signal output from 68. The absolute position of the focus lens group 20A that moves to a predetermined position in accordance with the rotation of the first outer cylinder is determined from the position data based on the gray code output from the focus lens position detection unit 70 provided in the first outer cylinder. can do. The position data based on the gray code is created by the pattern electrode formed in the focus lens position detection unit 70, and the position data indicating the moving position of the focus lens group 20A is output to the control circuit 86.

The control circuit 86 is composed of a microcomputer or the like, and controls each part of the camera including focus control. However, in the present embodiment, control other than focus control is out of the scope of the present invention, and therefore description thereof is omitted.

The rotating shaft of the DC motor 66 is connected to the first outer cylinder via a gear mechanism, and the first outer cylinder is rotated by the DC motor 66. The rotation amount is a disc 64A having a large number of slits radially formed and a photo interrupter 6
It is detected by an encoder 64 consisting of 4B.

The DC motor 66 detects the amount of movement of the focus lens group 20A.
The rotation amount of the disc is detected by a detector that counts the number of slits in the disk with slits, and the detected value and the focus lens group 20A
May be configured to be associated with the movement amount of

The variator lens group 20B and the compensator lens group 20C are both held by a second inner cylinder (not shown) and internally passed through the second outer cylinder. A cam groove is formed inside the second outer cylinder, and a pin protruding from the outer side of the second inner cylinder is located in the cam groove. Although the magnification of the zoom lens changes due to the rotation of the second outer cylinder, the subject image is always formed on the light receiving surface of the CCD 42 for image pickup. The magnification of the zoom lens can be checked from the zoom information (focal length fz of the zoom lens in this embodiment) by the gray code output from the zoom lens detection unit 72 provided in the second outer cylinder. The zoom information output from the zoom lens detector 72 is input to the control circuit 86.

The light that has passed through the diaphragm is passed through the beam splitter 24 to the imaging optical system.
Branched to the AF optical system.

The light split by the beam splitter 24 is AF (Auto Foc
us) lens 26, reflecting mirror 28, sensor optical system 30 through AF
The light is received by the sensor means 32.
The sensor optical system is composed of condensers 3 and separator lens 4 shown in FIG.

The aperture of the diaphragm 22 is adjusted by a servomotor (not shown) which is driven and controlled by the control circuit 86.

The light passing through the zoom lens is moved upward by 90 ° by the reflecting mirror 34.
It is reflected and enters the beam splitter 36. Reflector 34
Is kicked upward during shooting, whereby incident light passes through the low-pass filter 38 and the shutter 40 and the CCD 42 for imaging
An image is formed on the light receiving surface of. Electric charges corresponding to the subject image are accumulated on the light receiving surface of the CCD 42, and an electric signal corresponding to the electric charge pattern is output to the recording unit 44.

The low-pass filter 38 is provided to remove unnecessary components of incident light so that interference fringes are not generated, and the shutter 40 is for adjusting the light receiving time of the CCD 42. The recording unit 44 is configured to generate a video signal showing a subject image based on the input signal and record it on a recording medium such as a magnetic sheet.

The light incident on the beam splitter 36 is directly guided to the finder optical system via the imaging lens 44, and a part of the light of the beam splitter 36 is received by the light receiving element 46.

The electric signal photoelectrically converted by the light receiving element 46 is a control circuit.
The control circuit 86 controls the aperture value of the aperture 22 and the shutter speed of the shutter 40 based on the input signal.

The finder optical system includes a reflecting mirror 48, a relay lens 50, and an eyepiece lens 52.

A strobe 53 is installed on top of the camera body.
Light emitting element 12 used as auxiliary light when the brightness of the field light is insufficient when performing automatic focus adjustment in the body of 53.
Is provided.

The control circuit 86 is a circuit that controls and controls the camera body.
The control circuit 86 is connected to a power switch, an operation section 88 such as a shutter release button, and a display section (not shown) for displaying various data.

Now, the photoelectrically converted analog electric signal output from the sensor means is input to the analog calculation means 74, and the correlation calculation is performed by the analog calculation means 74. Sensor means 32
The structure of the analog calculation means 74 is shown in FIG. In the figure, the sensor means 32 comprises a reference image sensor 320, a reference image sensor 321, a reference reading section 322 and a reference reading section 323. The reference image sensor 320 and the reference image sensor 321 are the line sensor 5 of FIG. , 6 and a CCD (charge storage device) for transferring signal charges generated for each pixel by a plurality of charge transfer elements.

Further, the reference reading unit 322 and the standard reading unit 323 are adapted to output analog electric signals (hereinafter, referred to as pixel signals) relating to the subject image photoelectrically converted by the image sensors 320 and 321 in time series at predetermined timings. ing.

The analog calculation unit 74 is composed of an analog calculation unit 740, a control signal generation unit 742, and an AGC circuit 744.

The analog operation 740 includes a reference extension 322 and a standard extension 323.
The phase difference detection is calculated based on the pixel signals R (k) and B (k) that are output while being shifted for each pixel unit that is output, and the result of the operation is output to the output terminal 745.

The control signal generation unit 742 generates various control signals for controlling the operation timing of the entire device, and, for example, a charge transfer clock signal for performing a transfer operation of the CCD in the image sensors 320, 321 and the reading units 322, 323. Pixel signal R at
A control signal and the like for causing the output operation of (k) and B (k) to be performed at a predetermined timing synchronized with the charge transfer clock signal are generated.

The AGC circuit 744 detects to the control signal generation unit 742 that the signal charge generated in each pixel of the image sensors 320 and 321 is detected, and that when the predetermined charge amount is detected, the calculation of the phase difference detection should be started. Order.

FIG. 3 shows a specific circuit constructed based on the block diagram shown in FIG. A circuit will be described in association with each block in FIG. 2. The reference image sensor 320 and the standard image sensor 321 have substantially the same configuration, and the light receiving unit has photoelectric conversion elements Dr1 to Drn and Db1 to Dbn which are pixels.
100 and 101, storage sections 102 and 103 formed of CCDs for storing the signal charges generated in the respective light receiving sections 100 and 101 for each pixel, and signal charges transferred from the storage sections 102 and 103. It is composed of shift register units 104 and 105 formed by CCDs that take in and transfer charges in the horizontal direction.

That is, the storage units 102 and 103 and the shift register units 104 and 105 have the charge transfer elements Tr1 to Trn, Tb1 to Tbn, Cr1 to Crn, and Cb1 to Cbn corresponding to the photoelectric conversion elements Dr1 to Drn, Db1 to Dbn, The storage units 102 and 103 store the signal charges in the shift register unit 10
4 and 105 are transferred in parallel, and the shift register unit 104 transfers them in the horizontal direction. As will be described later, unlike the shift register unit 104, the shift register unit 105 on the reference image sensor side does not transfer the signal charges in the horizontal direction.

Reference numerals 106 and 107 denote conductive layers formed on the surface of the channel portion that transfers the signal charges from the light receiving portions 100 and 101 to the storage portions 102 and 103, which are formed of polysilicon layers and serve as potential barrier portions.

Reference numerals 108 and 109 denote transfer gates that control the movement of signal charges.

Further, floating gates Fr1 to Frn and Fb1 to Fbn are formed adjacent to the respective charge transfer elements Cr1 to Crn and Cb1 to Cbn, and the floating gates Fr1 to Frn and Fb1 to Fb are formed.
bn is a MOS type FET Mr1 ~ whose control signal CE is supplied to the gate
MOS type FET Qr1 ~ which is connected to the reset terminal RES via Mrn, Mb1 ~ Mbn and performs multiplex operation by applying the channel switching signals GH1 ~ GHn to the gate.
The common contacts Pr and Pb are connected via Qrn and Qb1 to Qbn, and the common contacts Pr and Pb are connected to the contacts Pr0 and Pb0 via impedance conversion circuits 110 and 111, respectively.

The impedance conversion circuits 110 and 111 both have the same circuit configuration, and MOS type FETs Ir1, Ir2, Ib1 and Ib2 that connect drain / source paths in series between the power supply VDD and the ground terminal, and MOS
Type FET Ir1 and Ib1 are connected in parallel between the gate and source, and when refresh signal φR is applied, the common contacts Pr and Pb are powered.
It has MOS type FETs Ir3 and Ib3 clamped to VDD, and is a MOS type FET
The gates of Ir2 and Ib2 are biased to a predetermined potential.

Next, the positional relationship between the shift register units 104 and 105 and the floating gates Fr1 to Frn and Fb1 to Fbn will be described with reference to FIG.

The photoelectric conversion elements and charge transfer elements of the light receiving section 100, the storage section 102, and the shift register section 104 on the side of the reference image sensor 320 are formed with 48 pieces each with an equal pitch width W, and are formed by four sections on both sides. , 2nd block IR, IIR
The floating gates Fr1 to Fr40 are connected to the charge transfer elements Cr1 to Cr40 of the third block IIIR consisting of 40 parts excluding
And 32 floating gates Fr1 to Fr3
It is classified into a fourth block IVR consisting of 2 and the remaining fifth block VR. And the floating gates Fr1 to F
One end of r40 is connected to the reset terminal RES via the MOS type FETs Mr1, Mr2, ... Of FIG. 3, and the floating gates Fr1 to Fr32 therein are contacted via the MOS type FETs Qr1 to Qrn of FIG. It is connected to Pr. That is, in FIG. 3, the portions of the third and fourth blocks IIIR and IVR of FIG. 4 are shown as representatives, and other IR, IIR, and VR portions are omitted, but these are signal It is a reserve area that operates when transferring charges in the horizontal direction.

On the other hand, the light receiving unit 101 and the storage unit 10 on the reference image sensor 321 side.
3, the photoelectric conversion element and the charge transfer element of the shift register unit 105 have the same pitch width W (reference image sensor
The floating gate Fb1 is adjacent to the charge transfer elements Cb1 to Cb32 of the third block IIIB except for the first and second blocks IB and IIB, each of which is formed of 40 pieces on each side. ~ Fb32 is attached. One end of each of the floating gates Fb1 to Fb32 is connected to the MOS type FETs Mb1 to Mbn and Qb1 to Qbn shown in FIG. That is, FIG. 3 shows the third block II of FIG.
Shown for IB.

Further, the light receiving portion 100 is formed with a distance l1 from the optical axis 90, and the light receiving portion 101 is formed with a distance l2 (= l1 + 4 · W) obtained by adding the four pitch width 4W to the distance l1.

Next, the phase difference detection device according to this embodiment is integrated into a single chip as a semiconductor integrated circuit device, and the phase difference detection device is connected from the image sensor 100 (101) to the floating gates Fr1 to Frn.
The structure will be described based on the schematic sectional view of FIG. 5 shown from (Fb1 to Fbn).

In FIG. 5, a plurality of N ⁺ type layers are formed on a part of the P type diffusion layer (P-well) formed on the surface of the N type semiconductor substrate, so that photoelectric conversion of the light receiving unit 100 (101) is performed. An element group is configured. Also, a SiO ₂ layer (not shown) on the semiconductor substrate
The barrier unit 106 (107) that generates the signal STS via the storage unit 1
02 (103), the transfer gate electrode layer forming each charge transfer element, the transfer gate 108 (109) forming the gate electrode layer, and the shift register section 104 (105) forming each charge transfer element forming the transfer gate electrode layer. Is attached. Further, next to the shift register units 104 and 105,
Floating gates Fr1 to Frn and Fb1 to Fbn are composed of polysilicon layers and the electrode layer Al clamped to the power supply VDD.
Has been accumulated. The electrode layer Al is formed so as to cover the entire upper surfaces of the plurality of floating gates Fr1 to Frn and Fb1 to Fbn formed. The MOS type FETs Mr1 to Mrn and Mb1 to Mbn are connected to one end of each floating gate.

In addition, the light receiving portion 100 (1
01) is provided with a lateral overflow gate (LOG) 90 via a SiO ₂ layer (not shown), and a lateral overflow drain (LOD) is provided on the surface portion of the semiconductor substrate adjacent to the lateral overflow gate 90. ) 92 is formed.

The overflow gate 90 is supplied to the power supply voltage Vcc or the voltage VBA via a switch 94 that can be switched manually or automatically.
(VBA <Vcc) is supplied.

Now, the reset signal φFG applied to the reset terminal RES
Is set to the same potential as the power supply VDD and the "H" level control signal CE
After the floating gates Fr1 to Frn and Fb1 to Fbn are clamped to the power supply VDD via the MOS type FETs Mr1 to Mrn and Mb1 to Mbn, the MOS type FETs Mr1 to Mrn and Mb1 to Mbn are turned off again, and the fifth As shown by the dotted line in the figure, a deep potential well is formed in the semiconductor substrate, and the shift register 10
4 (105) signal charge flows into the region under the floating gate. The voltage drop corresponding to each amount of the inflowing signal charges causes the floating gates Fr1 to Frn (Fb
1 to Fbn), the imaging pattern on the light receiving unit 100 (101) can be detected as a voltage signal.

On the other hand, after setting the reset terminal RES to the ground potential, the MOS type FE
When the floating gates Fr1 to Frn and Fb1 to Fbn are set to “L” level by turning on T Mr1 to Mrn and Mb1 to Mbn, the potential well in the region under the floating gate becomes shallow, and the signal charge is again transferred to the shift register section. 104 (10
You can return to 5). Since such movement of the signal charges is performed nondestructively, the reading of the signal charges can be repeated many times.

On the other hand, unnecessary charges of the signal charges generated by photoelectric conversion by the light receiving unit 100 (101) are lateral overflow gates.
The 90 is clamped to the power supply voltage Vcc (> VBA) to be discharged to the lateral overflow drain (LOD) region 92. Therefore, a photoelectric conversion element belonging to a specific range among a plurality of photoelectric conversion element groups forming the light receiving unit 100. In order to detect the voltage signal by flowing only the signal charge of the above into the area under the floating gates Fr1 to Frn (Fb1 to Fbn), the signal charge generated in the photoelectric conversion element outside the above specific range is lateral overflow as described above. It may be discharged to the drain region 92.

In this way, the signals generated through the floating gates Fr1 to Frn and Fb1 to Fbn are converted into time series signals R (k) and B by the multiplex operation of the MOS FETs Qr1 to Qrn and Qb1 to Qbn.
It is converted into (k) and output to the terminals Pr0 and Pb0 of the analog operation unit 740.

The control signal generator 742 uses the channel switching signal CH1 of a predetermined cycle.
To CHn, storage units 102 and 103 and transfer clock signal Tf, gate signal TG of transfer gates 108 and 109, transfer clock signals φr1 to φr4 and φb1 to φb of shift register units 104 and 105.
4, enable signal EN, clear signal CLR and control signal CE,
φSH and φSH are generated at a predetermined timing.

Next, the operation of the phase difference detection by the phase difference detection device shown in FIGS. 2 and 3 will be described together with the timing chart of FIG.

Before time t0, the photoelectric conversion elements Dr1 to Drn, Db1 to Dbn
When the AGC circuit 744 detects that a predetermined signal charge has been generated, the AG signal becomes “H” level, and the start signal STR (generated in association with the release button of the camera, etc.) applied at time t0 is generated. The arithmetic processing starts synchronously. First, to the reset terminal 28, a reset signal φR having a constant cycle Ta
Occurs. Also, during the period from time t0 to t3, the charge transfer elements of the shift register units 104 and 105 (see FIG. 4).
4 phase clock signals .phi.r1 to .phi.r4 and .phi.b1 to .phi.b4 are generated which cause the charge transfer based on the four phase driving method for one pitch.

At time t1 during charge transfer by this charge transfer element, the control signal CE becomes "H" level and the MOS type FET Mr1
~ Mrn, Mb1 to Mbn are turned on, the reset signal φFG is inverted from "L" to "H" level, so that the floating gates Fr1 to Fr40 and Fb1 to Fb32 are connected to the power supply voltage VD.
Clamped to the potential of D, the control signal CE becomes "L" level at time t2, and the MOS type FETs Mr1, Mr2, ..., Mb1, Mb
The floating gates are kept at the potential as they are because of high impedance. This allows
A potential well as shown in FIG. 5 is formed in the semiconductor substrate below the floating gate. And the time
Since the transfer gates 108 and 109 are turned on by the gate signal φTG at a time slightly before t2, the storage units 102 and 1
The signal charge of 03 is transferred to the corresponding charge transfer element of the shift register units 104 and 105. Then, the signal charge is further transferred to each of the potential wells by the time the transfer operation of the charge transfer element is completed at time t4.

Next, in the period from time t4 to t5, the channel switching signal
CH1 to CH32 are output and M that constitutes the multiplexer circuit
The OS type FETs Qr1 to Qrn and Qb1 to Qbn are turned on, and the time series signal for each pixel is output to the contacts Pr0 and Pb0. Contact Pr
The signal waveforms of 0 and Pb0 appear as shown in CQi of FIG. 6, for example. That is, each floating gate Fr1 to Frn, Fb1 to Fb
A voltage drop corresponding to the signal charge of each pixel is generated at bn, and a voltage waveform that is lowered by the voltage drop with respect to the power supply voltage VDD appears at the contacts Pr0 and Pb0.

Next, the configuration of the analog operation unit 740 shown in FIG. 2 will be described with reference to FIG. This analog operation unit 740 is composed of a switched capacitor integrator, and a signal line extending from a terminal Pr0 (see FIG. 3) has a switching terminal 140, a capacitive element Cs1, and a switching element which are connected in series.
Connected to the inverting input terminal of the differential integrator 142 via 141,
Both ends of the capacitive element Cs1 are connected to the ground terminal via the switching elements 143 and 144.

On the other hand, the signal line extending from the terminal Pb0 (see FIG. 3) has a differential integrator 142 via a switching element 145, a capacitive element Cs2, and a switching element 146 which are connected in series.
Of the capacitive element Cs2 is connected to the ground terminal via the switching elements 147 and 148. A switching element 150 and a capacitive element CI, which are connected in parallel with each other, are connected between the inverting input terminal and the output terminal 149 of the differential integrator 142.

Further, the inverting / inverted input terminal of the analog comparator 151 is connected to the signal line extending from the terminals Pr0 and Pb0,
The input terminal is connected to the input terminal of the channel select circuit 152, and the channel select circuit 152 is a select for controlling “on” and “off” of the switching elements 140, 141, 143, 144, 145, 146, 147, 148. Signal φ1, φ2, φ
Generates KA and φKB.

In the analog comparator 151, the level of the signal to be operated is R
When (k) ≧ B (k), “H” level, R (k) <B
In the case of (k), the polarity signal Sgn (k) of "L" level is output, and the voltage levels of the select signals φ1, φ2, φKA, and φKB are determined according to the level of the polarity signal Sgn (k). ing.

Next, the operation of the analog operation unit 740 having such a configuration will be described based on the timing chart of FIG.

First, after the switching element 150 is turned “on” by a reset signal φ _RST from a reset means (not shown) to discharge the unnecessary charge of the capacitive element C _I , the switching element 150 is turned “off” again. The operation shown in is started.

From the reference reading unit 322 and the standard reading unit 323 of the sensor means 32, as shown in FIG.
(K) and B (k) are output. When the signal to be operated has a relationship of R (k) ≧ B (k) as in the period from time t1 to t2, the polarity signal Sgn (k) becomes “H”, and FIG.
Rectangular-wave select signals φ1, φ2, φKA, and φKB as shown in (C), (D), and (E) are generated. Here, the select signals .phi.1 and .phi.2, .phi.KA, and .phi.KB are generated at timings that do not become "H" at the same time.

On the other hand, as in the period from time t3 to t4, the processed signal R (k)
In the relationship of <B (k), the polarity signal Sgn (k) becomes “L”, and the select signal φKA whose phase is opposite to that of the times t1 to t2,
φKB occurs. The select signals φ1 and φ2 are generated at the same timing regardless of the level of the polarity signal Sgn (k).

These select signals φ1, φ2, φKA, and φKB cause switching elements 144 and 14 in the first half cycle T _F1 of the period t1 to t2.
8 and the switching elements 140 and 147 are turned “on”, the operated signal R (k) is charged in the capacitive element Cs1, and the capacitive element C
The unnecessary charge of s2 is discharged. Next, in the second half period TR1 of the period t1 to t2, the switching elements 143 and 141 are “on”.
Therefore, the charges of the capacitive element Cs1 and the capacitive element C _I are coupled, and at the same time, the switching elements 145 and 146 are turned “on” and the switching elements 147 and 148 are turned “off”. ) Is supplied to the differential integrator 142 via the capacitive element Cs2. As a result, the electric charge q (k) shown in the following equation (2) is accumulated in the capacitive element C _I.

On the other hand, the signal to be operated is R (k) <B from time t3 to time t4.
In the case of (k), the switching elements 144 and 148 and the switching element 14 in the first half period T _F2 of the period t3 to t4.
3, 145 are turned on, the signal to be operated B (k) is charged in the capacitive element Cs2, and the unnecessary charge in the capacitive element Cs1 is discharged. Next, in the period TR2 in the latter half of the period t3 to t4, the switching elements 147 and 146 are turned on, so that the capacitive element Cs2
And the charge of the capacitive element C _I are coupled, and at the same time, the switching elements 140 and 141 are turned “on”, and the switching element 14
Since the signals 3 and 144 are “off”, the signal R (k) to be operated is supplied to the differential integrator 142 via the capacitive element Cs1. As a result, the electric charge q (k) shown in the following equation (3) is accumulated in the capacitive element C _I.

As is clear from the above equations (2) and (3), this analog operation unit 740 always accumulates in the capacitive element C _I a charge corresponding to the value obtained by subtracting the low-level calculated signal from the high-level calculated signal. Therefore, the time-series processed signal R (1),
When R (n), B (1), ..., B (n) are repeatedly processed, the absolute value H of the difference between these signals is obtained as a voltage at the output terminal 745, as shown in the following expression (4). .

When the calculation of the above equation (4) is completed, the reference reading unit 322 transfers the signal charges held in the shift register unit 104 of the reference image sensor 320 by one pitch with respect to the signal charges of the other shift register unit 105. Then, the signal charges whose phases are shifted from each other are read again in time series, and the analog calculation unit 74
0 performs the arithmetic processing of the above equation (4). Then, the phase of the signal charges of the shift register units 104 and 105 is further shifted, and this is repeated. This phase shift corresponds to the relative movement amount l, and the correlation calculation value when the movement amount l is sequentially changed can be obtained as the following equation (5) and detected as a voltage from the output terminal 745. .

That is, the above equation (5) corresponds to the above equation (1), and the correlation calculation values H (1), H (2), ... H (l) are obtained by analog signal processing.

Next, in the period from time t10 to t11, the previous time t6 to t1
The same process as 0 is repeated a predetermined number of times, and the correlation calculation value between the pattern that is sequentially shifted in the shift register unit 104 and the pattern of the shift register unit 105 that is not shifted is obtained.

In the above process, where l is the number of shift operations, And corresponds to the correlation calculation value by the digital signal processing described in the conventional example [see Formula (1)].

10 (a) to 10 (c) show waveform examples of the signal Vout obtained from the output terminal 745 by eight times of shift operation, and the minimum value is obtained when l = 4 as shown in FIG. 10 (a). When a pattern of different correlation calculation values occurs, it can be identified that it is in focus. When the correlation calculation value is the minimum when l <4 as shown in FIG. L as shown in FIG.
When it becomes minimum when> 4, it is in the rear focus state, and the focus and the shift amount can be simultaneously detected by the value of l.

As described above, according to this embodiment, since the correlation calculation value is calculated by analog signal processing, the calculation speed is extremely high, and the circuit can be unitized, so that it can be manufactured as a semiconductor integrated circuit device. Is suitable. In particular, the relative accuracy of the capacitors in the semiconductor integrated circuit is extremely excellent, and in combination with the unitization of the circuit, highly accurate calculation becomes possible.

Furthermore, since a floating gate is provided in the shift register so that signal charges can be repeatedly read out nondestructively, a storage device for storing a signal of a pattern related to a subject image is not required, and a small phase difference detection device can be provided. Can be provided.

Return to FIG. 1 again. As described above, analog calculation means
The analog calculation unit 740 in 74 calculates the correlation calculation value H (l), and the correlation calculation value H (l) is input to the comparator 78 via the sample hold circuit 76 or directly. The correlation calculation value H (l) (l is 1
The above integers are sequentially output as H (1), H (2), ..., But the non-inverting input terminal of the comparator 78 is previously output by the sample hold circuit 76 controlled by the timing pulse generator 80. The correlation calculation value output from the analog calculation means 74 is held. Here from the analog calculation means 74 last time,
Let H (l-1) be the output correlation calculation value and H (l) be the correlation output value output this time.
The magnitude relation with (l) is compared by the comparator 78.

The control circuit 86 outputs, to the motor drive circuit 68, a control signal for driving and controlling the DC motor 66, which is drive means for performing focus adjustment of the zoom lens 20, based on the comparison result of the comparator 78.

Next, the contents of the automatic focus control processing program executed by the control circuit 86 are shown in FIG. In the figure, when the program is started, the timing pulse generator 80
Upon receiving the control signal from 86, a timing pulse is output to the sample hold circuit 76, and the sample hold circuit 76 outputs the correlation operation value H (l) output from the analog operation means 74.
Is sampled and held at a predetermined cycle (step 50
0). Next, the correlation calculation value H (l-1) previously output by the analog calculation means 74 and held by the sample hold circuit 76 and the correlation calculation value H (l) output this time are stored.
The magnitude comparison with is performed by the comparator 78 (step 50).
1).

When it is determined in step 501 that H (l-1) <H (l), the count value j of the soft counter in the control circuit 86
Is incremented and the process returns to step 501 (step 5
02).

Here, the soft counter is a shift amount (relative movement amount) j in pixel units between the reference image sensor 320 and the standard image sensor 321 when performing analog correlation calculation by the analog calculation means 74 (j = 1 to 9 in this embodiment). ) Is a counter that counts.

When it is determined in step 501 that H (l-1)> H (l), the contents of the soft counter at that time j
Is taken in (step 503), and defocus calculation is performed (step 504). The defocus calculation is performed as follows. That is, it is assumed that the relative operation amount is j = k and the correlation calculation value H (l) is minimized during focusing. When the relative movement amount when the correlation calculation value H (l) at the time of out-of-focus is the minimum is j, the relative movement amount at which the correlation calculation value H (l) at the time of out-of-focus becomes the minimum and at the time of focusing The difference n with the relative movement amount that minimizes the correlation calculation value H (l)
Is n = k- (j + 1) (7) (n has a positive or negative sign). Next, the focus lens group 20A of the zoom lens 20
The defocus amount (Fig. 1) is Δd, and the correlation calculation value H is
When the defocus amount per pixel unit on the image sensors 320 and 321 where (l) is the maximum is Δx, the defocus amount Δd is Δd = Δx · n (8).

In the above formula (7), K = 5 in this embodiment. The symbol n indicates the direction in which the focus lens group 20A is driven in the optical axis direction of the image pickup optical system, and corresponds to the rotational drive direction of the DC motor 66.

The control circuit 86 calculates the defocus amount Δd by the above equations (7) and (8), and further, according to the defocus amount, the motor 66 so as to move the focus lens group 20A to the in-focus position on the optical axis thereof. A control signal for driving the motor is output to the motor drive circuit 68 (step 505).

As a result, focus adjustment is performed so that the focus lens group 20A, and further the zoom lens 20, are in focus.

In the above embodiment, the case where the automatic focus adjustment device according to the present invention is applied to the camera has been described, but the present invention is not limited to this, and may be applied to other optical devices such as a distance measuring device. Of course.

〔The invention's effect〕

As described above, in the present invention, the relative position of the pair of optical images of the subject is detected to determine whether or not the imaging optical system is in focus. In an automatic focus adjustment device that performs focusing by driving the imaging optical system in the optical axis direction until it reaches a focused state based on the position, a plurality of photoelectric conversion elements forming one pixel are arranged in a line. Including a pair of sensors that are installed,
The pair of sensors photoelectrically converts the pair of optical images, and an analog electrical signal corresponding to one optical image generated by the photoelectric conversion and an analog electrical signal corresponding to the other optical image are generated for each pixel unit in a predetermined cycle. A sensor means for non-destructively outputting while shifting, an analog calculating means for performing a correlation calculation of a pair of analog electric signals output by the sensor means, and outputting a correlation calculation value, and a time series output from the analog calculating means Comparing means for sequentially comparing the calculated correlation values with each other, driving means for driving the image pickup optical system in the driving direction, and output signals of the comparing means, and output from the analog calculating means based on the comparison output. The pixel position of the sensor means that minimizes the correlation calculation value is calculated, and the shift amount from the pixel position at the time of focusing of the pixel position is calculated. And a control means for controlling the driving means so as to drive the imaging optical system to the in-focus position on the optical axis according to the defocus amount. According to the invention, it becomes possible to perform the focus control of the imaging optical system with respect to the subject with a simple configuration at high speed and with high accuracy.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a camera provided with an automatic focus adjustment device to which the present invention is applied, and FIG. 2 is a block diagram showing a configuration of an embodiment of a phase difference detection device in FIG. 3 and FIG. 3 are circuit diagrams showing a concrete circuit configuration of the embodiment of FIG. 2, and FIG. 4 is an explanation showing arrangements of a light receiving section, a storage section, a shift register section and a floating gate of a reference section and a reference section. 5 and 5 are vertical cross-sectional views schematically showing cross sections of a light receiving portion, a storage portion, a shift register portion, and a floating gate, and FIG. 6 is a timing chart for explaining the circuit operation of FIG. FIG. 7 is a circuit diagram showing a specific circuit configuration of the analog operation unit in FIG. 3, FIG. 8 is a timing chart showing the operation of the analog operation unit, and FIG.
The figure is an explanatory diagram for explaining the calculation process of the correlation calculation value,
FIG. 10 is an explanatory view showing the principle for determining the in-focus state from the correlation calculation value, and FIG. 11 is a flow chart showing the contents of the automatic focus control processing program executed by the control circuit.
FIG. 12 is a schematic configuration diagram showing the configuration of a conventional automatic focus detection device, and FIG. 13 is a block diagram showing the configuration of the phase difference detection device in FIG. 20 …… Zoom lens, 32 …… Sensor means, 68 …… Motor drive circuit, 74 …… Analog computing means, 76 …… Sampling hold circuit, 78 …… Comparator, 86 …… Control circuit.

Claims (1)

[Claims] 1. A relative position of a pair of optical images of a subject is detected to determine whether or not an imaging optical system is in a focused state, and when it is not in a focused state, based on the relative position. In an automatic focus adjustment device that performs focusing by driving the imaging optical system in the optical axis direction until it reaches the focused state, a plurality of photoelectric conversion elements arranged in a line and reading from each photoelectric conversion element are performed. CC that transfers the generated charge horizontally
A D shift register section, a CCD floating gate which is provided in parallel with the CCD shift register section, and in which charges are transferred in parallel bidirectionally between the CCD shift register section, and a charge transferred to the CCD floating gate. A pair of sensors having an output unit that sequentially outputs an analog electrical signal corresponding to an optical image for each pixel unit, and a pair of analog electrical signals corresponding to a pair of optical images are output from the output unit, The charge of the CCD floating gate is transferred to the CCD shift register unit, and the CCD shift register unit outputs 1
After transferring in the horizontal direction for pixels, each charge is transferred again to the CCD floating gate to non-destructively output a pair of analog electric signals while shifting for each pixel unit in a predetermined cycle, and the sensor means. An analog calculation unit that performs a correlation calculation on a pair of analog electric signals that are output and outputs a correlation calculation value, and a pixel that has a minimum correlation calculation value based on the correlation calculation values that are output in time series from the analog calculation unit. A deviation amount, a driving unit that drives the imaging optical system in the optical axis direction thereof, a defocus amount is calculated from the calculated pixel deviation amount, and the imaging optical system is adjusted according to the defocus amount. An automatic focus adjustment device comprising: a control unit that controls a drive unit so as to drive to a focus position on the optical axis.