JPH07105087A - Information processing system - Google Patents

Abstract

(57) [Abstract] [Purpose] To obtain an information processing system capable of effectively using a system bus. [Configuration] The page transfer detector 20 includes a secondary storage device 4,
A page transfer detection signal P that detects the page transfer of the transfer required storage information between the main storage devices 3 and indicates the presence or absence of the page transfer
Output T to CMU controller 60 '. At this time, CMU
The controller 60 'sequentially writes the transfer required storage information input from the system bus side I / F 12 to the DM 61 via the DM write controller 69, and simultaneously stores the transfer required storage information on the main storage device 3. The tag address of the physical address information is sequentially written in TM62.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system having a buffer storage device for holding a part of information held in a main storage device, and particularly to a main storage device in a system adopting a virtual storage system. The present invention relates to an information processing system that efficiently transfers information held in a device to a buffer storage device.

[0002]

2. Description of the Related Art A central control unit (hereinafter referred to as Central Processing
Unit: In the following, "CPU" may be abbreviated)
With the increase in speed, in information processing systems, for example, a virtual memory system and a buffer memory device (Cache Memory Unit: may be abbreviated as “CMU”) have been adopted. These are methods for efficiently using a limited storage area as hardware resources. The former aims to secure a vast storage area and the latter aims to speed up the input / output (access) speed of information. .

First, the virtual memory system will be described. C
As the amount of information processed by the PU increases, there is a demand for expanding the storage area that can be handled. On the other hand, the storage device that can be installed in the information processing system is determined by physical and cost factors, and it is difficult to provide a storage area required. The virtual storage method is a method for securing a storage area that efficiently requests this limited storage device.

An information processing system adopting a virtual storage system is a storage device using a magnetic medium or the like which is relatively inexpensive and capable of increasing the capacity, and an operating speed which is relatively expensive and is not so easy to increase the capacity. Is generally provided with a high-speed semiconductor storage device, and the former is usually a secondary storage device and the latter is a main storage device.
rage).

The CPU obtains the information held in the storage device by using the address information (address) indicating the position in the memory area where the information is stored. An address in the virtual memory system is a storage area (logical space) that can be controlled by the CPU.
There is a logical address indicating an address in the area and a physical address indicating an address in an area (physical space) where the semiconductor memory device is physically provided.

There are various techniques for associating a logical address with a physical address. For example, in the page map pin virtual memory system, the logical address is incremented from the upper address (logical page address) indicating the page number and the top address of the page. Lower address to indicate (offset address)
The page size of the logical space and the page size of the physical space are matched by dividing the physical address into the upper address (physical page address) and the offset address and managing them.

When the CPU executes the program, an area corresponding to the logical space is secured on the secondary storage device and the program is temporarily stored in the area on the secondary storage device. Here, since the area secured on the secondary storage device is managed equivalently to the logical space, the area on the secondary storage device will be referred to as a logical space or a logical page hereinafter.

On the other hand, an area smaller than the area secured on the secondary storage device is secured in the physical space on the main storage device, and a part of the program is transferred from the logical space in page units. Since the page to be transferred is dynamically changed according to the execution status of the CPU, whether the logical page has been transferred in the physical space or not, and if it has been transferred, the assigned physical page number is assigned to each logical page. It is necessary to provide a page conversion table to hold.

Now, the relationship between the page conversion table and the page size will be described. When the page size is increased, the number of pages in the logical space is reduced, and the size of the page conversion table can be reduced. On the other hand, when a program smaller than the page size is executed, there are disadvantages such as an unused area in the page, which makes it impossible to effectively use the hardware resources, and the overhead time for page transfer increases. Generally, the page size is determined to be an appropriate amount in consideration of these points.

The operation of allocating a logical page and a physical page will be described with reference to FIG. When the CPU outputs the logical address, the logical page including the logical address is uniquely determined. Next, it is determined whether or not the logical page is allocated to the physical page, that is, whether or not the logical page is transferred to the physical page, by referring to the flag in the page conversion table.

When assigned, desired physical information is supplied to the CPU by referring to the physical space using the physical address obtained by converting the logical address.
When it is not assigned, it is called a page fault. At this time, in the address translation table, a free physical page is assigned to the logical page and the logical page is transferred.
A physical address obtained by converting a logical address is used to refer to the physical space, and desired information is supplied to the CPU.

During the page transfer, the CPU stops executing instructions and waits for the completion of the page transfer. When there is no free physical page in the page fault, the already allocated logical page is saved to the secondary storage device to secure the free physical page, and the free physical page is again allocated to the relevant logical page and secondary storage is performed. After the transfer from the device to the main memory device, the physical address obtained by converting the logical address is used to refer to the physical space, and desired information is supplied to the CPU.

For conversion from a logical address to a physical address, the logical address is composed of "logical page address + offset address", the physical address is composed of "physical page address + offset address", and both page sizes are set. Since they match, it can be realized simply by replacing the logical page address with the physical page address. Hereinafter, this operation is called address translation.

The above is the outline of the operation of the virtual memory system.
Recently, segment page mapping virtual memory system that solved the problem when the logical space became large capacity,
There is also a multiple virtual memory system that solves the problem of program relocation, but this is not explained here.

Next, the buffer storage device will be described. Generally, dynamic random access
Although a memory (DRAM) is adopted, the access speed of the DRAM cannot keep up with the improvement of the operating speed of the CPU, and recently, a great weight is required for referring to the main memory of the CPU. As a method to solve this, D
Static R with faster access speed than RAM
Although there is a means of adopting an AM (SRAM) as a main storage device, it is difficult to secure a large-scale storage capacity because an SRAM has a lower degree of integration and a higher unit price of memory elements than a DRAM. The buffer storage device is a method of efficiently using the storage device employing this SRAM.

The buffer memory unit (CMU) is a device that holds the information referred to by the CPU among the information held in the main memory together with the address information. This takes advantage of the temporal locality of access to the main memory by the CPU. Temporal locality is a property that "the information that has been referenced once is likely to be re-referenced immediately afterwards". For example, in a program that performs repetitive operations, a certain instruction is repeatedly referred to. Can be said to have temporal locality. The buffer memory is currently a CPU
The information referred to by is retained in the SRAM capable of high-speed operation, and when re-referenced by the CPU, the information retained in the SRAM is supplied to the CPU to realize the high-speed operation.

The operation of the information processing system having the CMU will be described with reference to FIG. The CMU described here performs a write-through operation as a main memory update method.

<Read Operation / Write Operation> When the CPU starts the read operation, an address is first input to the CMU. In the CMU, the information desired by the CPU is C
It is judged whether or not it is held in the MU. When it is held, it is called a cache hit, and when it is not held, it is called a cache miss. Hereinafter, the case where the read operation and the write operation are performed in order of Case 1 to Case 4 in FIG. 6 will be described as an example.

In case 1, when the CPU requests the information Ia at the address A and the CMU makes a cache miss to this, the CMU uses the address A from the CPU to refer to the main memory (MS). When the CPU supplies the information Ia desired by the CPU, the CMU holds the information Ia in the CMU together with the address information (address A),
At the same time, the information Ia is output to the CPU.

Next, in case 2, when the CPU requests the new information Ib at the address B and the CMU also makes a cache miss, the CMU refers to the main memory device using the address B from the CPU. To do. From main memory to C
When the information Ib desired by the PU is supplied, the CMU holds the information Ib in the CMU together with the address information (address B) and outputs the information Ib to the simultaneous CPU.

Next, in case 3, the CPU again
When the CMU makes a cache hit by requesting the information Ia at the address A, the CMU supplies the CPU with a copy of the information Ia held in the CMU without referring to the main storage device. When the processing of the CPU further progresses, a copy of the information in the main storage device is held in the holding area of the CMU, and new information cannot be held. Method to selectively discard and retain new information.

Next, in case 4, the CPU sends the information I
When a write operation is requested to the holding area of the information Ib at the address B using c, the CMU holds the information I held inside itself.
Address B output from CPU for updating b to information Ic
To output the information Ic to the main storage device. Then, the main memory device writes the information Ic in the holding area of the information Ib and updates the information.

Although not shown in FIG. 6, the cache miss in the write operation is the same as the cache hit operation except that the information in the CMU is not updated.

The specific operation inside the buffer memory device will be described below with reference to FIG. As shown in FIG. 7, the buffer storage device holds DM (data memory) 61 which holds a part of the contents of the main storage device, and TM (which holds a part of the address in the main storage device of the information held in the DM 61. Tag memory) 6
2. VB (significant information storage unit) 63 indicating whether or not the contents held in TM62 are significant, and an entry for generating a signal for designating a storage area of DM61, TM62, VB63 with an address input from the outside as an input Decoder 64, T
It comprises a tag / address comparing section 65 for judging whether or not the output of M62 and a part of the address input from the outside match, a CMU control circuit 60 for controlling the operation of each section inside the buffer memory device, and the like.

The structure of the CMU 6 will be described below with reference to FIG. The external address signal EAD output from the CPU side I / F 11 is input to the address controller 614 and the address output controller 615. Address controller 61
4 processes the external address signal EAD by dividing it into an external tag address signal ETA and an entry address signal EEA. External tag output from the address controller 614
The address signal ETA is input as one input of the TM write controller 67 and the tag / address comparator 65.
The external entry address signal EEA output from the address controller 614 is input to the entry decoder 64. The entry decoder 64 decodes the external entry address signal EEA, converts it into a signal designating an operation area, and TM (tag memory) 62, VB (significant bit storage) 63 and DM (data memory) 61. To transmit.

The tag information SS62 of the TM62 is input as the other input of the tag / address comparator 65, and the address comparator 65 compares the tag information SS62 with the external tag / address signal ETA. Tag address comparator 6
The comparison result of 5 is input to the hit determiner 66 together with the output of VB63, and the hit determiner 66 generates a hit signal HT based on these signals.

Information input from the CPU side I / F 11 is input to the DM 61 to the main memory device write controller 612 and D.
Input via the M-light controller 68,
Information input from the bus side I / F 12 is input via the DM light controller 69. The output of the DM 61 is output to the CPU side I / F 11 via the information output controller 611.

The CMU controller 60 receives the input signals of the hit signal HT and the write signal WR, and the I / O on the system bus side.
Based on the main memory control signal MSC input / output to / from F12, the TM write controller 67 and the DM write controllers 68, 6
9, information output controller 611, main memory write controller 6
12 and the control signals for controlling the address output controller 615 are output to control the operation of the CMU 6. further,
The CMU controller 60 also outputs a significant signal VD that makes the contents of VB significant.

The operation of the CMU 6 having such a configuration will be described. In the read operation, it is first determined whether or not the buffer storage device holds the information requested by the CPU. That is, DM from a part of the address input from the CPU
61, TM62, TM6 which specifies the area to be operated in VB63 and which is specified by a part of the address
It is determined whether the contents of 2 and a part of the address match. At the same time, VB specified by a part of the address
63 It is determined whether the information inside is significant.

TM62 outputs do not match, or V
When the output of B63 is not significant, it is determined that a cache miss has occurred and the main memory is accessed using the address.
Obtain the information desired by the CPU. At the same time, the information obtained from the main memory and a part of the address are held in the storage areas in the DM 61 and TM 62 designated by the part of the address. Further, a signal indicating significance is written in the storage area in VB63 designated by a part of the address.

When the outputs of TM62 match and the output of VB63 is significant, it is determined that a cache hit has occurred, and the information held in the storage area in DM61 specified by the address is output to the CPU. To do.

In the write operation, the address input from the CPU and the information input from the CPU are output to the main storage device and written to the main storage device. At the same time, it is determined whether the contents of the memory area of the TM62 specified by a part of the address match a part of the address, and if they match, the information input from the CPU is specified by the address. The value is stored in the storage area of the DM 61, and a value indicating significance is written in the storage area in the VB 63 specified by the address.

When the buffer memory device is used, desired information can be immediately supplied to the CPU when a cache hit occurs. Also, since it is not necessary to refer to the main storage device, the CM
The system bus connecting U and main memory has the advantage that other peripherals can be used.

Next, the operation of the information processing system employing the virtual storage system and the buffer storage device will be described with reference to FIGS. 8 and 9. Here, FIG. 8 is a block diagram showing an example of the configuration of the information processing system, and FIG. 9 is a flowchart showing the operation of the peripheral device with respect to the access of the CPU. The information processing system includes a main storage device (MS) 3 on the system bus 7,
The secondary storage device (SS) 4, the direct memory access controller (DMAC) 5 and the CMU 6 are connected to each other, and the memory management unit (MMU) 2 is interposed between the CMU 6 and the CPU 1. In addition,
The CMU 6 is a physical buffer storage device that stores a physical address as address information.

Referring to FIG. 9, in step S1, the CPU
When 1 outputs the access request, in step S2, MM
When U2 determines that the storage content of the page of the access address, which is the logical address output by the CPU 1, exists in the main memory device 3, the access address is translated, the physical address in the main memory device 3 is output, and it does not exist. If so, a page fault is generated in the CPU 1.

If a page fault does not occur in step S2, the process proceeds from step S3 to step S5 without passing through step S4, and the CMU 6 is accessed using the physical address converted by the MMU 2.

On the other hand, when a page fault occurs in step S2, the process moves from step S3 to step S4.
A page swap operation is performed in step S4. The details will be described below.

The CPU 1 interrupts the access, assigns the logical page to the physical page by referring to the address translation table, and issues an instruction to the DMAC 5 to transfer the logical page (shoo-in).

When there is no free physical page, the transferred physical page is saved in the secondary storage device before swap-in to obtain a free physical page (swap out), and the logical page is allocated again. And DMAC
In accordance with an instruction from the CPU 1, the transfer unit 5 transfers the storage content of the logical page on the secondary storage device 4 as transfer required storage information to a free physical page on the main storage device 3 via the system bus 7.

Thereafter, the CPU 1 restarts the interrupted access, and accesses the CMU 6 by using the physical address on the main storage device 3 in which the transfer required storage information is stored in step S4.

In step S5, the CMU 6 caches the CPU 1 for access based on the physical address.
A hit / cache miss is determined. If a cache hit, a read operation or write operation is determined in step S6. If a cache miss, step S1.
At 0, it is determined whether it is a read operation or a write operation.

When a cache hit occurs in step S5 and the operation of the CPU 1 is determined to be a read operation in step S6, the CMU 6 does not access the main storage device 3 in step S7, and the physical address stored therein is stored in the CMU 6. The corresponding holding information is provided to the CPU 1.

On the other hand, in step S5, the cache
If it is a hit and it is determined that the operation of the CPU 1 is a write operation in step S6, the CMU 6 determines in step S9.
Then, the information of the page designated by the physical address of the main storage device 3 is updated, and the held information corresponding to the physical address inside the CMU 6 is also updated in step S8 in parallel with step S9.

When a cache miss occurs in step S5 and the operation of the CPU 1 is determined to be a read operation in step S10, the CMU 6 updates the stored contents of the page designated by the physical address of the main storage device 3 in step S11. Is performed, and step S11 is performed in parallel with step S11.
In 12, the holding information corresponding to the physical address inside the CMU 6 is also updated.

On the other hand, in step S5, the cache
If a mistake is made and the operation of the CPU 1 is determined to be the write operation in step S10, the CMU is executed in step S13.
6 updates the storage contents of the page designated by the physical address of the main storage device 3.

In the information processing system employing the virtual memory system and the buffer memory device, the CPU obtains desired data from the main memory device by the above procedure.

[0047]

When a page fault occurs in a request address from a CPU in a system adopting a virtual memory system, page transfer is performed from a secondary memory device to a main memory device via a system bus. During this time, the data request from the CPU is stopped, so that the data is not retained in the buffer storage device. With the completion of page transfer, CP
The request address is output again from U. Since the information stored in the request address at this time exists only in the main storage device, the buffer storage device always performs the cache miss operation to access the main storage device via the system bus.

In this operation, since the information transferred via the system bus at the time of page transfer is transferred again via the system bus by the cache miss operation of the buffer memory device, the use efficiency of the system bus is lowered. There was a problem that it would end up.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain an information processing system capable of effectively using a system bus.

[0050]

An information processing system according to a first aspect of the present invention is a CP for accessing with logical address information of a logical address space in a virtual memory system.
U, a system bus, a first storage device that holds a part of the storage contents of the logical address space in a physical address space narrower than the logical address space, and a storage device that stores all the storage contents of the logical address space A second storage device that
A buffer storage device that stores a part of the storage contents of the first storage device and is capable of reading and writing faster than the first and second storage devices, and the CPU stores logical address information desired to be accessed. When the storage content of certain access address information is present in the first storage device, if the storage content of the access address information is further present in the buffer storage device, the buffer storage device is directly accessed; otherwise, the system is accessed. When the first storage device is accessed via a bus and the storage content of the access address information does not exist in the first storage device, the storage content of the access address information held in the second storage device The transfer-required storage information that is the above is stored in a storage area corresponding to predetermined physical address information in the physical address space in the first storage device. A virtual storage system is adopted in which an access request is again made with the access address information after executing a transfer process between storage devices for transfer via a system bus. The buffer storage device is a part of the physical address space. Address holding means for holding address information as buffer address information, and buffer storage in which storage contents held in the storage area of the first storage device specified by the buffer address information are associated with the buffer address information. Content holding means for holding as information, and the first and second
Transfer detecting means for detecting the presence / absence of execution of the inter-storage-device transfer processing between the storage devices, and receiving the detection result, and the detection result instructing execution of the inter-storage-device transfer processing. At this time, the transfer-requiring storage information and the physical address information on the first storage device storing the transfer-requiring storage information are stored in the content holding means and the address holding means as the buffer storage information and the buffer address information, respectively. And control means for holding each.

Preferably, as in the information processing system according to claim 2, when the storage content of the access address information exists in the first storage device, the logical address information is converted into the physical address information. Further, the CPU may be configured to access the buffer storage device or the first storage device with the physical address information.

Preferably, as in the information processing system according to claim 3, the buffer storage device associates with the buffer address information whether or not the buffer storage information held in the content holding means is significant. Further, the control means controls access to only the buffer storage information corresponding to the buffer address information that the significance instruction means has instructed to be significant, and the detection result is stored between the storage devices. When the execution of the transfer process is instructed, the buffer storage information and the buffer address information corresponding to the transfer storage required information and the physical address information on the first storage device storing the transfer required storage information are significant. The contents of the significance indicating means may be changed so that

Preferably, as in the information processing system according to claim 4, the CPU instructs execution of the inter-storage-device transfer processing when the storage content of the access address information does not exist in the first storage device. Output a transfer command for receiving the transfer command via the system bus, and when the transfer command instructs execution of the inter-storage-device transfer process, the first and second independent CPUs are provided. An inter-storage device transfer control means for controlling the inter-storage device transfer process between the storage devices may be further provided.

Preferably, as in the information processing system according to claim 5, the transfer command of the CPU is given to the inter-storage device transfer control means via the buffer storage device, and the transfer of the buffer storage device is performed. The detection means may be configured to receive the transfer command and output the detection result based on the transfer command.

Preferably, as in the information processing system according to claim 6, the transfer required storage information is continuously output from the first storage device to the first storage device for each predetermined unit storage amount. It may be information provided.

[0056]

In the buffer storage device of the information processing system according to any one of claims 1 to 6, the presence / absence of execution of the inter-storage device transfer process between the first and second storage devices is detected and the detection result is displayed. When the transfer detection means for outputting and the detection result instruct the execution of the transfer processing between storage devices, the transfer required storage information and the physical address information on the first storage device storing the transfer required storage information are respectively buffer stored. The information holding means and the address holding means respectively hold the information and the buffer address information as control information.

Therefore, if the CPU does not execute the inter-storage device transfer process between the first and second storage devices when the storage contents of the access address information do not exist in the first storage device, the contents of the buffer storage device will be described. The holding means and the address holding means can hold the transfer required storage information and the physical address information on the first storage device storing the transfer required storage information as buffer storage information and buffer address information, respectively.

[0058]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing the configuration of an information processing system adopting a virtual storage system according to an embodiment of the present invention. As shown in the figure, in the information processing system, a main storage device (MS) 3, a secondary storage device (SS) 4, a direct memory access controller (DMAC) 5 and a CMU 6'are connected to a system bus 7. And CM
A memory management unit (MMU) 2 for performing memory management such as converting a logical address requested by the CPU 1 into a physical address used in the main storage device 3 is interposed between the U 6 ′ and the CPU 1. Also, CM
U6 'is a physical buffer storage device that stores a physical address as address information.

FIG. 2 is a flowchart showing an access operation of the CPU to each storage device in the information processing system shown in FIG. Referring to FIG. 2, step S
When the CPU 1 outputs the access request at 21, the MMU 2 performs address conversion of the access address when it is determined that the storage content of the page of the access address which is the logical address output by the CPU 1 exists in the main storage device 3 at step S22. Then, the physical address on the main storage device 3 is output, and if it is determined that the physical address does not exist, a page fault is generated.
Occurs in PU1.

If no page fault occurs in step S22, the steps from step S23 to step S23 are performed.
Immediately without passing through steps S24 and S25, the process immediately proceeds to step S26, and the CMU 6'is accessed using the physical address converted by the MMU 2.

On the other hand, if a page fault occurs in step S22, the process proceeds from step S23 to step S24, and the page swap operation is performed in step S24. The details will be described below.

The CPU 1 interrupts the access, refers to the address translation table, assigns the logical page to a free physical page, and transfers the logical page to the DMAC.
Give instructions to 5 (shuppin).

Here, when there is no free physical page in the main storage device 3, one of the transferred logical pages is selected by a predetermined existing means, written back to the secondary storage device 4, and then discarded. Obtain a free physical page on the main storage device 3 (swap out). Further, the CPU 1 controls the DMAC 5 to transfer the logical page to the physical page. Then, according to the instruction from the CPU 1, the DMAC 5 transfers the storage contents of the logical page on the secondary storage device 4 to the empty physical page on the main storage device 3 via the system bus 7 as transfer required storage information.

Since the information of the logical page on the system bus at this time is very likely to be referred to by the CPU 1 in the near future, the transfer required storage information is stored in the above step S25 in parallel with step S24. It is sequentially fetched and held in the CMU 6'corresponding to the empty physical page.

After the processing of steps S24 and S25 is completed, the CPU 1 resumes the interrupted access, and in step S26, the CMU 6'is designated by using the physical address on the main storage device 3 in which the transfer required storage information is stored. to access.

In step S26, the CMU 6'determines the cache hit / miss of the access of the CPU 1 based on the physical address. If it is a cache hit, in step S27 it is determined whether it is a read operation or a write operation. If it is a cache miss, step S31
Then, it is determined whether it is a read operation or a write operation.

If a cache hit occurs in step S26 and the operation of the CPU 1 is determined to be a read operation in step S27, the CMU is executed in step S28.
The reference numeral 6 ′ provides the CPU 1 with the stored information corresponding to the physical address stored therein without accessing the main storage device 3.

On the other hand, if a cache hit occurs in step S26 and it is determined in step S27 that the operation of the CPU 1 is a write operation, C is determined in step S30.
The MU 6'updates the information of the page designated by the physical address of the main storage device 3 and, in parallel with step S30, also updates the held information corresponding to the physical address inside the CMU 6'in step S29.

If a cache miss occurs in step S26 and it is determined in step S31 that the operation of CPU 1 is a read operation, CMU 6'is determined in step S32.
Refers to the read information of the page designated by the physical address of the main storage device 3 and provides it to the CPU 1, and in step S33, holds the read information in association with the physical address inside itself.

On the other hand, if a cache miss occurs in step S26 and it is determined in step S31 that the operation of the CPU 1 is a write operation, the CMU is executed in step S34.
Reference numeral 6 updates the information of the page designated by the physical address of the main storage device 3.

As described above, in the information processing system of this embodiment, when there is an access request from the CPU 1 and a page fault occurs, transfer required storage information between the secondary storage device 4 and the main storage device 3 is used as in the conventional case. Page transfer is performed, and the transfer required storage information is held in the CMU 6'in correspondence with the physical address on the main storage device 3.

Therefore, when the page transfer is completed, C
When the same request address is output again from PU1, C
A cache hit always occurs in the MU 6 ', and data transfer is performed between the CPU 1 and the CMU 6'without accessing the main storage device 3 via the system bus 7.
As a result, the information transferred via the system bus at the time of page transfer is not transferred again via the system bus, so that the usage efficiency of the system bus can be improved.

FIG. 3 is an explanatory diagram showing the internal structure of the CMU 6'in the information processing system shown in FIG. CMU
Before describing the internal structure of 6 ', the direct mapping method will be described first. In the CMU of the direct mapping method, the physical space is divided into a plurality of areas having the same storage capacity, and the number of each area (upper part of the physical address, hereinafter referred to as "tag address") and the offset value in each area ( The storage area in the CMU is managed by the lower part of the physical address, hereinafter referred to as "entry address"). All storage areas in CMU 6'are
Access is made by address, and only the tag address is held as buffer address information. This is the direct mapping method. Here, for simplification of description, the area size of the buffer storage device and the page size of the virtual storage system are the same.

Next, the internal structure of the CMU 6'will be described. CP
The external address signal EAD, which is a physical address output from the U side I / F 11, is input to the address controller 614, the page transfer detector 20 and the address signal controller 613. The address controller 614 controls the external address signal E
AD is divided and output as an external tag address signal ETA for instructing a tag address and an entry address signal EEA for instructing an entry address.

The external tag address signal ETA output from the address controller 614 is input as one input of the TM write controller 67 and the tag address comparator 65. The external entry address signal EEA output from the address controller 614 is input to the entry decoder 64. The entry decoder 64 is an external entry
The address signal EEA is decoded and converted into a signal designating an operation area, and then TM (tag memory) 62, VB (significant bit storage unit) 63 and DM (data memory) 61.
To transmit.

The TM 62 stores the tag address of the storage data stored in the DM 61 as the tag information SS 62, and the DM 61 stores the data corresponding to the tag address in the TM 62.

The tag information SS62 of TM62 is inputted as the other input of the tag / address comparator 65, and the address comparator 65 compares the tag information SS62 with the external tag / address signal ETA. Tag address comparator 6
The comparison result of 5 is input to the hit determiner 66 together with the output of VB63. The hit determiner 66 generates a hit signal HT indicating a cache hit / cache miss based on the output of the address comparator 65 and the output of VB63.

Information input from the CPU side I / F 11 is input to the DM 61 to the main memory write controller 612 and D.
Input via the M-light controller 68,
Information input from the bus side I / F 12 is input via the DM light controller 69. The output of the DM 61 is output to the CPU side I / F 11 via the information output controller 611.

The page transfer detector 20 receives information input from the system bus side I / F 12 and the external address signal E.
Based on the write signal WR input from the AD and CPU side I / F 11, the page transfer of the storage information required to be transferred between the secondary storage device 4 and the main storage device 3 is detected, and the page transfer is instructed. The detection signal PT is sent to the CMU controller 6
Output to 0 '.

The CMU controller 60 'has a hit signal HT,
The CMU controller 60 'is based on the input signals of the page transfer detection signal PT and the write signal WR, and the main memory control signal MSC which is input / output to / from the system bus side I / F 12.
Is also the TM light controller 67, DM light controller 6
8, 69, the information output controller 611, the main memory write controller and the address signal controller 613 are outputted to control the operation of the CMU 6 '. further,
The CMU controller 60 'also outputs a significance signal VD that validates the contents of VB.

The basic operation of the CMU 6'such as cache hit / miss under the control of the CMU control circuit 60 'will be described below. When the external address signal EAD from the CPU side I / F 11 is input to the address controller 614, the external entry address signal EEA is input from the address controller 614 to the address comparison unit 64.

Then, by the entry decoder 64,
The operating areas of DM61, TM62 and VB63 are determined. The tag information SS62 of the TM62 and the external tag address signal ETA are compared by the address comparator 65, and based on the comparison result of the address comparator 65 and the output of VB63, the hit determiner 6 determines whether the cache hit / miss occurs. A hit signal HT instructing the determination is output to the CMU control circuit 60 '.

When there is a cache miss and the access of the CPU 1 is a read operation, the CMU controller 60 'controls the address signal controller 613 to output the external address signal EAD to the system bus. Also, the main storage device 3
To access the main memory device control signal MSC. The information supplied from the main storage device 3 is written to the DM 61 via the DM write controller 69, and simultaneously output to the CPU side I / F 11 via the information output controller 611. When the information is written in the DM 61, the external tag address signal ETA is transmitted to the T via the TM write controller 67.
The significant signal VD is written in a predetermined area of M62.
Is enabled, TM6 among the flags in VB63
The part corresponding to the above-mentioned predetermined area 2 is validated.

When there is a cache miss and the access of the CPU 1 is a write operation, the CMU controller 60 'causes the CP
The main memory write controller 612 outputs the information input from the U side I / F 11 to the system bus side I / F 12.
And the address signal controller 613 to output the external address signal EAD to the system bus. Further, in order to access the main memory device 3, the main memory device control signal M
Output SC.

When there is a cache hit and the CPU1 access is a read operation, the CMU controller 60 'outputs D
The information output controller 611 is controlled to output the output of M61 to the CPU side I / F 11. The operation when a cache hit occurs and the access of the CPU 1 is a write operation except that the DM 61 is simultaneously updated when the information input from the CPU side I / F 11 is output to the system bus side I / F 12. , Cache miss and CPU1
Is the same as when the access is a write operation.

In addition to the normal CMU operation such as cache hit / miss, the CMU 6'detects page transfer caused by a page fault by the MMU 2 and fetches information. The operation at this time will be described.

When the page transfer detector 20 detects page transfer, it outputs a page transfer detection signal PT. At this time, the CMU controller 60 'outputs a signal indicating the page transfer state to the address controller 614. The address controller 614 resets the counting function of the entry address in response to this signal. After that, until the page transfer is completed, that is, until the counting function for counting the information amount (number of pages) of the transfer required storage information is completed,
According to the instruction of the CMU controller 60 ', the entry address is counted and automatically output. On the other hand, the system bus side I
The information input from the / F12 is used as the DM light controller 69.
The external tag address signal ETA of the physical address of the main memory 3 supplied from the I / F 12 on the system bus side at the same time is sequentially written to the DM 61 via the address signal controller 613, address controller 614 and TM write controller. The data is sequentially written in the TM 62 via 67. When the page transfer is completed, the normal CMU operation is resumed. At this time, no information is output to the CPU side I / F 11.

FIG. 4 shows a configuration example of the page transfer detector 20 shown in FIG. As shown in FIG. 4, the page transfer detector 2
0 is a control address holder 21 that holds a DMAC control address that is an access address of the control register of the DMAC 5, a start request value holder 22 that holds a start request value that instructs the start of page transfer by the DMAC, and External information signal EIS obtained from the bus I / F 12 side
A bit selector 23 that outputs only a signal at a predetermined bit position of information, and a control register that compares the output of the control address holder 21 with the external address signal EAD.
The address comparator 24 and the request value comparator 2 for comparing the output value of the bit selector 23 and the output value of the start request holder 22.
5, and a condition determiner 26 for determining the start of page transfer between the secondary storage device 4 and the main storage device 3 based on the output values of the control register / address comparator 24 and the request value comparator 25.

Before explaining the operation of the page transfer detector 20 shown in FIG. 4, first, the CP before the page transfer is started.
The operation of U will be described. Inside the DMAC 5 shown in FIG. 1, there are a DMAC control register for controlling the operation mode of the DMAC itself, in addition to a register for designating a transfer source address, a transfer destination address and a transfer byte number which are parameters for information transfer. These registers are assigned to predetermined addresses and are accessed for controlling the DMAC 5. When performing information transfer using the DMAC5,
The CPU always writes a value indicating the information transfer start request to a predetermined bit position in the control register of the DMAC 5. Since the access to the control register of the DMAC 5 is performed via the buffer memory device 6 ', the page transfer detector 20 can detect the presence or absence of the page transfer operation by detecting this operation.

The operation of the page transfer detector 20 will be described below. When the external address signal EAD is input,
The control register / address comparator 24 compares the external address signal EAD with the DMAC control address to detect whether the access of the CPU 1 is directed to the DMAC control register.

At the same time, the request value comparator 25 compares the output of the bit selector 22 with the bit selector 23 to determine a predetermined bit position of the external information signal EIS (bit indicating the presence or absence of an information transfer start request). The request value comparator 25 detects whether or not (position) is a value indicating an information transfer start request.

Then, the condition determiner 26 is composed of both detectors 2
When the results of both detectors 24 and 25 show a coincidence based on the outputs of 4 and 25 and the write signal WR, that is,
A page for instructing the page transfer operation when the access of the CPU 1 targets the DMAC control register and the predetermined bit of the external information signal EIS has a value indicating the information transfer start request and the access of the CPU is the write operation. The transfer detection signal PT is output. Here, D held by the control address holder 21 and the start request value holder 22
The MAC control address and the start request value may be written in advance by the CPU 1 or may be designated by an external signal. In the information processing system in which the DMAC5 may be used for other than page transfer,
The page transfer can be detected by monitoring the writing to the register holding the transfer source address or the transfer destination address in C.

In the present embodiment, an example of direct mapping is shown, but the present invention can also be applied to a virtual memory type information processing system that employs another mapping such as a set way associative type. Of course.

[0094]

As described above, in the buffer storage device of the information processing system according to the first to sixth aspects of the present invention, the inter-storage device transfer process between the first and second storage devices is executed. Transfer detection means for detecting the presence / absence of the presence and outputting a detection result; and on the first storage device storing the transfer required storage information and the transfer required storage information when the detection result instructs execution of the transfer processing between storage devices. And the control means for causing the content holding means and the address holding means to hold the physical address information as buffer storage information and buffer address information, respectively.

Therefore, when the CPU does not execute the inter-storage device transfer process between the first and second storage devices when the storage contents of the access address information are not present in the first storage device, the contents of the buffer storage device are executed. The holding means and the address holding means can hold the transfer required storage information and the physical address information on the first storage device storing the transfer required storage information as buffer storage information and buffer address information, respectively.

As a result, when the CPU executes the inter-memory-device transfer processing between the first and second memory devices and requests another access with the same access address information, the first memory device is always accessed. Since the data transfer can be executed between the CPU and the buffer storage device without the need, the usage efficiency of the system bus can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an information processing system that is an embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of the information processing system of FIG.

FIG. 3 is a block diagram showing an internal configuration of the buffer storage device of FIG.

FIG. 4 is a block diagram showing an internal configuration of the page transfer detector of FIG.

FIG. 5 is an explanatory diagram showing the concept of a virtual storage device.

FIG. 6 is an explanatory diagram showing an operation example of a conventional buffer storage device.

FIG. 7 is a block diagram showing an internal configuration of a conventional buffer storage device.

FIG. 8 is a block diagram showing a configuration of a conventional information processing system.

FIG. 9 is a flowchart showing the operation of a conventional information processing system.

[Explanation of symbols]

 1 CPU 2 MMU 3 Main memory 4 Secondary memory 5 DMAC 6'CMU (buffer memory) 7 System bus 20 Page transfer detector

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[Procedure amendment]

[Submission date] February 2, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 6

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction content]

There are various techniques for associating a logical address with a physical address. For example, in the page map pin virtual memory system, the logical address is incremented from the upper address (logical page address) indicating the page number and the top address of the page. Lower address to indicate (offset address)
Similarly, the physical address is also divided into an upper address (physical page address) and an offset address for management, and the page sizes of the logical space and the physical space are matched.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0028

[Correction method] Change

[Correction content]

The CMU controller 60 receives the input signals of the hit signal HT and the write signal WR, and the I / O on the system bus side.
Based on the main memory control signal MSC input / output to / from F12, the TM write controller 67 and the DM write controllers 68, 6
9, information output controller 611, main memory write controller 6
12 and Outputs each control signal for controlling the address output controller 615 controls the operation of CMU6. Furthermore, C
The MU controller 60 outputs a significant signal V that makes the content of VB significant.
D is also output.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0038

[Correction method] Change

[Correction content]

The CPU 1 interrupts the access, refers to the address translation table, allocates the logical page to the physical page, and issues an instruction to the DMAC 5 to transfer the logical page ( swap-in ).

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0062

[Correction method] Change

[Correction content]

The CPU 1 interrupts the access, refers to the address translation table, assigns the logical page to a free physical page, and transfers the logical page to the DMAC.
Give instructions to 5 ( swap in ).

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0091

[Correction method] Change

[Correction content]

At the same time, the request value comparator 25 compares the output of the bit selector 22 with the bit selector 23 to determine a predetermined bit position of the external information signal EIS (bit indicating the presence or absence of an information transfer start request). position) detects whether a value indicating the information transfer start request in main Motomechi comparator 25.

Claims (6)

[Claims] 1. A CPU for accessing with logical address information of a logical address space in a virtual memory system, a system bus, and a part of storage contents of the logical address space is held in a physical address space narrower than the logical address space. First to do
And a second storage unit for holding all storage contents of the logical address space.
And a buffer storage device that stores a part of the storage contents of the first storage device and can read and write faster than the first and second storage devices, and the CPU desires access. When the storage content of the access address information, which is the logical address information, exists in the first storage device, if the storage content of the access address information is further present in the buffer storage device, the buffer storage device is directly accessed to exist. Otherwise, the first storage device is accessed via the system bus, and if the storage content of the access address information does not exist in the first storage device, the access held in the second storage device. The transfer-necessary storage information, which is the storage content of the address information, corresponds to predetermined physical address information in the physical address space in the first storage device. In an information processing system of a virtual memory system, which executes an inter-storage device transfer process of transferring to a storage area via the system bus, and again requests access with the access address information, wherein the buffer storage device is the physical address space Address holding means for holding a part of the above address information as buffer address information, and storage contents held in the storage area of the first storage device specified by the buffer address information as the buffer address information. Content holding means for holding as buffer storage information associated with each other; transfer detection means for detecting whether or not the inter-storage-device transfer processing between the first and second storage devices is executed and outputting a detection result; When the detection result is received and the detection result instructs execution of the transfer process between storage devices, the transfer required storage information and the transfer required storage And a control means for causing the content holding means and the address holding means to hold the physical address information on the first storage device storing the information as the buffer storage information and the buffer address information, respectively. Information processing system. 2. When the stored content of the access address information is present in the first storage device, the CPU further comprises address conversion means for converting the logical address information into the physical address information. 2. The buffer storage device or the first storage device is accessed by physical address information.
Information processing system described. 3. The buffer storage device further comprises a significance indicating means for indicating whether or not the buffer storage information held in the content holding means is significant, in association with the buffer address information, and the control means: When only the buffer storage information corresponding to the buffer address information that the significance indicating unit has designated as significant is accessible, and the detection result indicates execution of the inter-storage-device transfer processing, the transfer storage required. Changing the contents of the significance indicating means such that the buffer storage information and the buffer address information corresponding to the physical address information on the first storage device storing the information and the transfer required storage information are significant Item 2. The information processing system according to item 2. 4. The CPU, when the stored content of the access address information does not exist in the first storage device,
Outputs a transfer command for instructing execution of the inter-storage device transfer process, receives the transfer command via the system bus, and is independent of the CPU when the transfer command instructs execution of the inter-memory device transfer process. 4. The information processing system according to claim 3, further comprising an inter-storage device transfer control means for controlling the inter-storage device transfer process between the first and second storage devices. 5. The transfer command of the CPU is given to the inter-storage device transfer control means via the buffer storage device, and the transfer detection means of the buffer storage device receives the transfer command and receives the transfer command. The information processing system according to claim 4, wherein the detection result is output based on. 6. The information processing system according to claim 5, wherein the transfer-necessary storage information is information continuously output from the first storage device to the first storage device for each predetermined unit storage amount. .